Parameter extraction technique for HBT equivalent circuit usingcutoff mode measurement

A parameter extraction method based on the S-parameter measurements of the heterojunction bipolar transistors (HBTs) biased to cutoff is proposed. This method is applied to confirm the results for the RF probe pad and interconnection pattern parasitics obtained from the special test structures, and to determine some of the device capacitances of the HBT. The remaining device parameters are extracted by the S-parameter measurements of the devices biased to the active mode. The extraction technique gives good agreement between the equivalent circuit and the measured S-parameters of the HBT including probe pads and interconnections     

Analysis of power/ground-plane EMI decoupling performance using thepartial-element equivalent circuit technique

The design of printed circuit (PC) boards with decoupling capacitors has been the subject of debate and different opinions for many years. The design and electrical impact of the capacitors has been difficult to separate from all other electrical interactions occurring on a conventional PC board populated with integrated circuits. This work demonstrates how the partial-element equivalent circuit (PEEC) modeling technique can be used to accurately predict the performance of various decoupling design strategies. Computer modeling using the PEEC approach is very flexible due to the ease of mixing physical geometries with a large number of circuit elements. Also, the compute time for such practical mixed EM and circuit problems are relatively short. Using this technique, the usual iteration between a number of different designs of test boards can be avoided. We show that the change of the voltage across the PC board, or the voltage gradient, can be used as an effective tool for the improvement of the decoupling efficiency     

A SPICE modeling technique for GaAs MESFET IC's

A vertically integrated device modeling technique for GaAs IC's is presented for use in circuit simulation. Most of the SPICE2 capability can be utilized for modeling the gate transit time and parasitic effects. A computer program has also been developed to extract model parameters from the measured device data.     

Accuracy and stability improvements of integral equation modelsusing the partial element equivalent circuit (PEEC) approach

The partial element equivalent circuit (PEEC) technique is a formulation which transforms an electric field integral equation (EFIE) into a full-wave equivalent circuit solution. In this paper, improvements are made to the PEEC model through the development of a refined method of computing both the partial inductances as well as the coefficients of potential. The method does not increase the number of unknowns. In addition, damping is added to the PEEC model in order to further reduce nonphysical resonances which may occur above the useful frequency range, The observations and solutions presented in this paper are especially important for time domain solvers. The effectiveness of the method is illustrated with several examples     

Stability of discretized partial element equivalent EFIE circuitmodels

The instabilities associated with integral equation techniques for-the solution of electromagnetic problems in the time domain are well known. Instabilities may be due to either the numerical technique used for the time integration, or problems created by the discrete representation for the numerical solution of the problem. In this paper, we concentrate on the discretization issue. The stability problem occurs for various discretizations and formulations. Here, we use the partial element equivalent circuit (PEEC) formulation of the electric field integral equation (EFIE) in the circuit domain. This leads to a better understanding of the issues at hand. We show why the discretized model can be unstable and we suggest a circuit motivated technique to stabilize the solution     

Equivalent circuit modelling of lossy coupled lines using SPICE software

A new skin effect equivalent circuit and a propagation line equivalent circuit for time domain simulation on a single line have been presented in previous work (T. Vu Dinh et al., 1990) SPICE simulations have proved the accuracy and efficiency of the proposed method. This concept is extended for coupled line modelling. A dual line device is analysed as a typical example of the usual cases. The method has successfully been extended to N lossy coupled lines. The results show a good agreement with those obtained by other methods.<>     

Physical scaling rules for AlGaAs/GaAs power HBTs based on asmall-signal equivalent circuit

Physical scaling rules for AlGaAs/GaAs heterojunction bipolar transistors (HBTs) containing 2-16 emitter fingers are demonstrated, the parameter extraction is based on a small signal equivalent circuit. The scaling parameters compare favorably with the measured data from the process control monitor     

A nonlinear equivalent circuit for IMPATT diodes

A lumped nonlinear equivalent circuit is developed for Read-type IMPATT diodes, using the carrier transport equations for the device. The validity of this circuit is not restricted to sinusoidal signal waveforms. It can be used for quantitative calculations of device performance as well as for qualitative predictions of the general features of IMPATT diode behavior. The general equivalent circuit is further simplified for the case of sinusoidal excitation and its application is demonstrated by simple examples.     

Modeling noise correlation behavior in dual-collectormagnetotransistors using small signal equivalent circuit analysis

We present a distributed small signal equivalent circuit model based on hybrid-π for modeling of the low-frequency noise correlation behavior in dual-collector magnetotransistors (MTs). The model is based on the assumption that the noise sources at the emitter-base junction of the transistor are spatially correlated; the degree of spatial correlation in noise sources being limited by the intrinsic base spreading resistance. This gives rise to a degradation in correlation of terminal collector noise currents at high current, or injection, levels due to nonuniformities in the dc bias current distribution     

A simple equivalent circuit analysis of rectangular folded-waveguide slow-wave structure

A simple yet accurate equivalent circuit model was developed for the analysis of slow-wave properties (dispersion and interaction impedance characteristics) of a rectangular folded-waveguide slow-wave structure. Present formulation includes the effects of the presence of beam-hole in the circuit, which were ignored in existing approaches. The analysis was benchmarked against measurement as well as with 3D electromagnetic modeling using MAFIA for two typical slow-wave structures operating in Ka- and Q-bands, and close agreements were observed. The analysis was extended for demonstrating the effect of the variation of beam-hole radius on the RF interaction efficiency of the device.     

A new current scaling pixel circuit for AMOLED

A new active-matrix organic light-emitting diode (AMOLED) pixel design, composed of four polycrystalline silicon thin-film transistor (poly-Si TFT) and one capacitor, is proposed by employing a novel current scaling scheme. The simulation results, based on the measured characteristics of an OLED and poly-Si TFTs, show that the proposed pixel design would scale down the data current more effectively, so as to guarantee a lower charging time compared with the conventional current mirror structure, as well as successfully compensate the variation of the electrical characteristics of the poly-Si TFTs, such as the threshold voltage and mobility.     

频率选择表面等效电路的计算与分析

提出一种利用全波数值计算和等效电路理论反演介质中频率选择表面(FSS)等效电路的方法。该方法物理过程直观,适用于任意形状FSS等效电路的精确求解。采用经典方环型FSS,验证该等效电路提取方法的可行性。最后采用该方法研究圆形缝隙型FSS结构尺寸、介质材料以及电磁波入射角对其等效电路参数的影响规律,为后续FSS等效电路研究及快速设计奠定理论基础。     

Simple technique for analysis of SC networks using general-purpose circuit simulation programs

A new technique is proposed which enables the transformation of a large class of switched-capacitor (SC) networks into equivalent time-continuous (analogue) circuits to analyse them by use of standard, general-purpose circuit simulation programs such as SPICE It is based on a block partitioning, i.e. a total SC network is divided into small building blocks. It is shown how basic SC building blocks like integrators and summers can be modelled by equivalent two-ports containing only resistors, lossless transmission lines and current-controlled voltage sources. Furthermore, some new offset-free SC integrator schemes based on multi-step integration algorithms are also described.     

Equivalent circuit approach for single electron transistor modelfor efficient circuit simulation by SPICE

A new compact DC/transient single electron transistor model for circuit simulation by SPICE is introduced. This model includes newly developed equivalent circuit approach based on the time-dependent master equation and an exact conductance or transient conductance model. The simulation speed of this model is improved compared with that of the previous models     

一种新的应用到硅基有机发光二极管微显示像素电路仿真的OLED SPICE模型

本文介绍了一种新的OLED器件等效电路模型。由于单二极管模型能和多二极管模型一样较好的模拟OLED特性,因此新模型是基于单二极管模型建立的。并且为了保证拟合数据和测试数据有很好的一致性,在新模型中将常量电阻替换成指数电阻。通过与测试数据和其他两种OLED SPICE模型的模拟数据对比,新的模型更符合OLED的电流电压特性。新的模型能直接整合到SPICE电路仿真器中去,并且在OLED整个电压工作范围内拥有较好的仿真精度。     

A new equivalent circuit for piezoelectric ceramic disk resonators

A new equivalent circuit is considered for piezoelectric ceramic radial mode disk resonators. The new circuit has been obtained by connecting a resistance element in series with a commonly used equivalent circuit, so that it is usable for a better simulation of the frequency characteristics of the resonator impedance.     

量子级联激光器的一种新的等效电路模型

采用电路建模方法,通过分析量子级联激光器（QCL,quantum cascade laser）中电子在子能带间跃迁机理和量子阱间的输运特性得到其二层级电子速率方程和光子速率方程,以此建立QCL的等效电路模型。电路模型的建立使得对QCL特性可以用通用电路仿真工具进行模拟仿真,克服了数值分析方法计算复杂,模拟时间长的缺点。...     

A sensitivity analysis of SPICE parameters using an eleven-stage ring oscillator

SPICE is a circuit simulator which predicts node voltages and currents as a function of time from device model parameters. Model parameters are determined by the manufacturing process, but process-induced variations in these parameters occur within a chip or from chip to chip. Values for the model parameters used in simulators are usually obtained from measurements on test structures along the periphery of the circuit or in test chips located at several sites on the product wafer. This paper presents examples of how well model parameters extracted from a test chip can predict the AC response of a dynamic circuit element (MOS ring oscillator) on the same wafer. Simulation results show which model parameters are critical to performance. A comparison between measurement and simulation results is given and the importance of intrachip and intrawafer parameter variations is discussed. For the samples tested, the polysilicon gate linewidth variation was determined to be the primary cause of the ring oscillator frequency variation.     

A sensitivity analysis of SPICE parameters using an eleven-stage ring oscillator

SPICE is a circuit simulator which predicts node voltages and currents as a function of time from device model parameters. Model parameters are determined by the manufacturing process. Process-induced variations in these parameters occur within a chip or from chip to chip and cause corresponding variations in circuit performance. Values for the model parameters used in simulators are usually obtained from measurements on test structures which are found along the periphery of the circuit or in test chips located at several sites on the product wafer. Because of the spatial separation between test structures and the circuits of interest, differences between measured and simulated performance can occur. This paper presents examples of how well model parameters extracted from a test chip can predict the ac response of a dynamic circuit element (ring oscillator) on the same wafer. Simulation results show which model parameters are critical to performance. A comparison between measurement and simulation results is given and the importance of intra-chip and intra-wafer parameter variations is discussed. For the samples tested, the polysilicon gate linewidth variation was determined to be the primary cause of the ring oscillator frequency variation.