1.3 V low close-in phase noise NMOS LC-VCO with parallel PMOS transistors

A new NMOS cross-coupled LC-VCO with parallel PMOS transistors is proposed. The proposed LC-VCO is useful for suppressing flicker noise upconversion and very suitable for low voltage application. It is implemented in 0.18 mum CMOS technology and has superior characteristics to a conventional complementary LC-VCO. Measured phase noise is -93 dBc/Hz at 100 kHz and -116 dBc/Hz at 1 MHz offsets and its core current is only 2 mA for a 1.3 V supply voltage.     

CMOS低相位噪声压控振荡器的设计

基于65 nm CMOS标准工艺库,设计了一个工作频率在10 GHz的具有低相位噪声的CMOS电感电容型压控振荡器。该压控振荡器选用CMOS互补交叉耦合型电路结构,采用威尔逊型尾电流源负反馈技术来降低相位噪声。仿真结果表明,此压控振荡器工作频率覆盖范围为9.9~11.2 GHz,调谐范围为12.3%,中心频率为10.5 GHz,在频率偏移中心频率1 MHz下的相位噪声为-113.3 dBc/Hz,核心功耗为2.25 mW。     

2.5GHz低相位噪声CMOS LC VCO的设计

用0.35μm、一层多晶、四层金属、3.3V的标准全数字CMOS工艺设计了一个全集成的2.5GHz LC VCO,电路采用全差分互补负跨导结构以降低电路功耗和减少器件1/f噪声的影响.为了减少高频噪声的影响,采用了在片LC滤波技术.可变电容采用增强型MOS可变电容,取得了23%的频率调节范围.采用单个16边形的对称片上螺旋电感,并在电感下加接地屏蔽层,从而减少芯片面积,优化Q值.取得了在离中心频率1MHz处-118dBc/Hz的相位噪声性能.电源电压为3.3V时的功耗为4mA.     

An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback

A fully integrated 0.024 mm² differentially tuned 6-GHz LC-VCO for 6+Gb/s high-speed serial (HSS) links in 90-nm bulk CMOS is presented. It is smaller than any LC-VCO reported to date at this frequency. Its size is comparable with ring oscillators but it has significantly better phase noise. A circuit technique is introduced to dynamically set the common-mode (CM) voltage of the differential varactor control signals equal to the VCO's CM. Compared to other commonly used techniques such as replica biasing, this technique does not dissipate any extra power and it accurately tracks the output common-mode voltage of the VCO during the oscillations. Using a differential control a very wide tuning range from 4.5 GHz to 7.1 GHz (45%) is achieved. The VCO has a measured phase noise of -117.7 dBc/Hz at a 3-MHz offset from a 5.63-GHz carrier while dissipating 14 mW from a 1.6-V supply.     

Design and realization of an ultra-low-power low-phase-noise CMOS LC-VCO

A fully integrated cross-coupled LC tank voltage-controlled oscillator(LC-VCO) using transformer feedback is proposed to achieve a low phase noise and ultra-low-power design even at a supply below the threshold voltage. The ultra-low-power VCO is implemented in the mixed-signal and RF 1P6M 0.18-μm CMOS technology of SMIC. The measured phase noise is-125.3 dBc/Hz at an offset frequency of 1 MHz from a carrier of 2.433 GHz,while the VCO core circuit draws only 640μW from a 0.4-V supply.The designed VCO can...     

A 1.3 GHz low-phase noise fully tunable CMOS LC VCO

This paper presents a low-phase noise CMOS LC-VCO, in which a complete compensation of the component spread, due to process variations, can be done. The LC tank is made of a metal-oxide-silicon varactor and a bondwire and a spiral inductor in series. The trade-off between VCO gain variations and phase noise is introduced. The measurements performed on a prototype, powered by a 2-V supply, realized in a digital CMOS process, are presented. The oscillation frequency can be varied in the range 1.1-1.45 G-Hz. The measured phase noise at an offset of 600 kHz from a 1.3-GHz carrier is -119 dBc/Hz, with 6-mA current consumption     

A 5 GHz, 192.6 dBc/Hz/mW FOM, LC–VCO System With Amplitude Control Loop and LDO Voltage Regulator in 0.18 μm CMOS

To reduce phase noise degradation from oscillator tail current sources, this letter presents an inductor-capacitor voltage-controlled oscillator (LC-VCO) biased by triode metal-oxide-semiconductor transistors. The VCO system also includes an amplitude control loop and a voltage regulator to endure process, voltage, and temperature variations and to enhance power supply rejection ratio. Fabricated in a 0.18 mum CMOS process, the measured results show the adopted topology achieves a better phase noise than the conventional saturation current source. At 5.181 GHz, the VCO system demonstrates a phase noise of -104.8 dBc/Hz at 100-kHz offset, and -127.1 dBc/Hz at 1 MHz offset, while dissipating 4.2 mA from a 1.8 V supply voltage. The corresponding figures of merit at 100 kHz and 1 MHz offset are 190.3 and 192.6 dBc/Hz/mW, respectively.     

LC-VCO design optimization at 1/f 2 phase noise performance in 65 nm CMOS technology

A way of analytical calculation in the phase noise modeling of the LC-VCO topology without tail current resource is proposed. The noise current imported by the MOS channel is modeled to give approximate evaluation, and the period of the transistor noise is included in the model. Phase noise introduced by the tank loss resistance is also modeled to evaluate the circuit phase noise performance. The circuit has been implemented in a 65 nm CMOS technology. The chip occupies 951 × 705 um² areas with the buffer and pads. The test result indicates that the VCO core consumes 1.125 mW with a 1.2 V power supply, the frequency of the VCO baseband is from 1.258 to 1.37 GHz, and the multiband frequency is from 0.86 to 1.37 GHz. The best performance of the LC-VCO shows a phase noise of ?129.57 dBc/Hz at 1 MHz offset frequency from a 1.3 GHz carrier, resulting in an excellent FoM of ?191.27 dBc/Hz.     

基于0.35μm SiGe BiCMOS的高纯度频率综合器

介绍了一个基于0.35μm SiGe BiCMOS的整数N频率综合器.通过采用不同工艺来实现不同模块,实现了一个具有良好的杂散和相噪性能的高纯度频率综合器.除环路滤波器外所有的部件均采用差分电路结构.为了进一步减小相位噪声,压控振荡器中采用绑定线来形成谐振.该频率综合器可在2.39～2.72 GHz的频率范围内输出功率OdBm.在100kHz频偏处测得的相位噪声为-95dBc/Hz,在1MHz频偏处测得的相位噪声为-116dBc/Hz.参考频率处杂散小于-72dBc.在3V 的工作电压下,包括输出驱动级在内的整个芯片消耗60mA电流.     

A 10-GHz CMOS quadrature LC-VCO for multirate optical applications

A 10-GHz quadrature LC-VCO (QVCO) fabricated in a 0.13-/spl mu/m CMOS process for 10-Gb/s multirate optical applications is described. Bimodal oscillation behavior (or phase ambiguity) inherent to quadrature LC-VCOs is analyzed theoretically and a cascode-based coupling method is proposed which effectively eliminates bimodal oscillation. Digitally controlled capacitor arrays are used in this design to extend the tuning range of the QVCO to cover multirate operations. The QVCO achieves a jitter generation of only 32 mUI/sub pp/ at 10 GHz and a phase noise of -95 dBc/Hz at 1-MHz frequency offset with only 8 mA of current consumption in the QVCO core.     

2GHz低功耗差分控制的CMOS单片LC压控振荡器

设计了工作在2GHz,差分控制的单片LC压控振荡器,并利用0.18μm CMOS工艺实现.利用模拟和数字(4位二进制开关电容阵列)调频技术,压控振荡器的调频范围达到16.15%(1.8998～2.2335GHz).在2.158GHz工作频率下,在1MHz频偏处的相位噪声为-118.17dBc/Hz.应用给出的开关设计,相位噪声在不同的数字位控制下变化不超过3dB.由于利用pn结二级管作为变容管,在调频范围内,相位噪声仅改变约2dB.压控振荡器在1.8V电源电压下消耗2.1mA电流并能够在1.5V电源电压下正常工作.     

基于0.35μm SiGe BiCMOS的2.5GHz低相位噪声LC压控振荡器的设计

介绍了一个基于0.35μm SiGe BiCMOS工艺的2.5GHz低相位噪声LC压控振荡器.文章重新定义了压控振荡器工作区域.分析表明谐振回路的电感值和偏置电流对振荡器的相噪优化有重要的影响.本文同时分析了CMOS和BJT压控振荡器设计思路的不同.本设计中,采用键合线来实现谐振回路中的电感来进一步提高相噪性能.该VCO和其他模块集成在一起实现了一个环路带宽为30kHz的频率综合器.测试结果表明,当中心频率为2.5GHz时,在100kHz和1MHz的频偏处相噪分别为-95dBc/Hz和-116dBc/Hz.工作电压为3V时,VCO核心电路的电流消耗为8mA.据我们所知,这是国内第一个采用SiGe BiCMOS工艺的差分压控振荡器.     

精确的1.08GHz CMOS电感电容压控振荡器

在0.35μm 2P4M标准CMOS工艺上,设计了一个精确的1.08GHz CMOS电感电容压控振荡器.提出了一种有效计算压控振荡器周期的新方法,采用该方法计算的频率-电压调谐曲线与实验结果吻合得很好.在电源电压3.3V下,消耗电流3.1mA,压控振荡器的相位噪声在10kHz频偏处为-82.2dBc/Hz.芯片面积为0.86mm×0.82mm.     

基于90nmCMOS工艺的低功耗宽带压控振荡器设计

A low power VCO with a wide tuning range and low phase noise has been designed and realized in a standard 90 nm CMOS technology. A newly proposed current-reuse cross-connected pair is utilized as a negative conductance generator to compensate the energy loss of the resonator. The supply current is reduced by half compared to that of the conventional LC-VCO. An improved inversion-mode MOSFET(IMOS) varactor is introduced to extend the capacitance tuning range from 32.8% to 66%. A detailed analysis of the proposed varactor is provided. The VCO achieves a tuning range of 27–32.5 GHz, exhibiting a frequency tuning range(FTR) of 18.4%and a phase noise of –101.38 d Bc/Hz at 1 MHz offset from a 30 GHz carrier, and shows an excellent FOM of –185d Bc/Hz. With the voltage supply of 1.5 V, the core circuit of VCO draws only 2.1 m A DC current.     

Low voltage low noise open loop automatic amplitude control for voltage-controlled oscillators

This paper presents a low voltage low noise open loop automatic amplitude control method for voltage-controlled oscillators (VCO’s). In this method a feedback mechanism keeps the VCO at its optimum amplitude over temperature and process variations and then the loop is broken to avoid noise injection form the control circuitry to the VCO. The loop does not add extra noise to the VCO. Based on the proposed method, a low voltage low noise LC-VCO was designed for a low phase noise application in TSMC 0.18 micron RFCMOS technology. Simulations show considerable improvement in the phase noise with the application of the proposed method.     

A novel concept for phase noise improvement in monolithic differential LC-VCOs

A novel concept for improvement of phase noise in differential LC-VCOs is proposed. Being based on quality factor (Q) enhancement through conversion of the lossy inductor to a virtual inductor conditionally approaching the ideal lossless limit, the basics of the concept are illustrated and explained. Practical realization of the concept is discussed, and its application in design of a CMOS based Giga Hertz range low phase noise monolithic differential LC-VCO is investigated. Advanced Design System (ADS) simulations using CMOS 0.18 μm TSMC RF design kit are used for evaluation.     

Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture

This paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-/spl mu/m CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm/sup 2/ and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL.     

A constant loop bandwidth fractional-N frequency synthesizer for GNSS receivers

正A constant loop bandwidth fractional-TV frequency synthesizer for portable civilian global navigation satellite system(GNSS) receivers implemented in a 130 nm 1P6M CMOS process is introduced.Via discrete working regions,the LC-VCO obtains a wide tuning range with a simple structure and small VCO gain.Spur suppression technology is proposed to minimize the phase offset introduced by PFD and charge pumps.The optimized bandwidth is maintained by an auto loop calibration module to adjust the charge pump current when the PLL output frequency changes or the temperature varies.Measurement results show that this synthesizer attains an in-band phase noise lower than -93 dBc at a 10 kHz offset and a spur less than -70 dBc;the bandwidth varies by±3%for all the GNSS signals.The whole synthesizer consumes 4.5 mA current from a 1 V supply,and its area(without the LO tested buffer) is 0.5 mm~2.     

Low-power low-phase-noise differentially tuned quadrature VCOdesign in standard CMOS

This paper describes the design and optimization of VCOs with quadrature outputs. Systematic design of fully integrated LC-VCOs with a high inductance tank leads to a cross-coupled double core LC-VCO as the optimal solution in terms of power consumption. Furthermore, a novel fully differential frequency tuning concept is introduced to ease high integration. The concepts are verified with a 0.25-μm standard CMOS fully integrated quadrature VCO for zero- or low-IF DCS1800, DECT, or GSM receivers. At 2.5-V power supply voltage and a total power dissipation of 20 mW, the quadrature VCO features a worst-case phase noise of -143 dBc/Hz at 3-MHz frequency offset over the tuning range. The oscillator is tuned from 1.71 to 1.99 GHz through a differential nMOS/pMOS varactor input     

MOS varactors with n- and p-type gates and their influence on an LC-VCO in digital CMOS

The influence of the gate doping type of the MOS varactor on frequency tuning, phase noise, and frequency sensitivity to supply-voltage variations of a fully integrated inductance-capacitance voltage-controlled oscillator (LC-VCO) is presented. Three varactors in multifinger layout with shallow trench isolation (STI) are compared. The polysilicon gate is either entirely n- or p-doped or the fingers have alternating n and p doping. Differences in capacitance and quality factor are shown. Two identical VCOs with the varactors having n gates or np gates are realized. Homogenous doping increases the VCO tuning range to 1.31 GHz (/spl plusmn/20%) in comparison to 1.06 GHz (/spl plusmn/15%) obtained by mixed doping. However, mixed doping has the advantages of more linear VCO frequency tuning, lower close-in phase noise, and reduced maximum sensitivity to variations in supply voltage. Several varactor parameters are introduced. They allow prediction of the influence of varactors on the performance of a given VCO. With a current consumption of only 1 mA from a supply voltage of 1.5 V, both VCOs show a phase noise of -115 dBc/Hz at 1-MHz offset from a 4-GHz carrier and a VCO figure of merit of -185.3 dBc/Hz.