Empirically Verified Thermodynamic Model of Gate Capacitance and Threshold Voltage of Nanoelectronic MOS Devices With Applications to HfO2 and ZrO2 Gate Insulators

A thermodynamic variational model derived by minimizing the Helmholtz free energy of the MOS device is presented. The model incorporates an anisotropic permittivity tensor and accommodates a correction for quantum-mechanical charge confinement at the dielectric/substrate interface. The energy associated with the fringe field that is adjacent to the oxide is of critical importance in the behavior of small devices. This feature is explicitly included in our model. The model is verified using empirical and technology-computer-aided-design-generated capacitance-voltage data obtained on MOS devices with ZrO₂, HfO₂, and SiO₂ gate insulators. The model includes considerations for an interfacial low-k interface layer between the silicon substrate and the high-k dielectric. This consideration enables the estimation of the equivalent oxide thickness. The significance of sidewall capacitance effects is apparent in our modeling of the threshold voltage (V_th) for MOS capacitors with effective channel length at 30 nm and below. In these devices, a variation in high-k permittivity produces large differences in V_th. This effect is also observed in the variance of V_th, due to dopant fluctuation under the gate.     

Modeling of mismatch effect in submicron MOSFETs based on BSIM3model and parametric tests

Mismatch between identically designed MOS transistors plays an important role in the performance of analog circuits. This paper reports a MOS transistor mismatch model applicable for submicron CMOS technology and developed based on the industry standard BSIM3v3 model. A quick way to estimate drain current mismatch based on parametric test data was also suggested     

A time-dependent, surface potential based compact model for MOScapacitors

This paper presents a compact model for metal oxide semiconductor (MOS) capacitors, based on a time-dependent solution for the surface potential. This enables modeling of the frequency dependence of MOS capacitors, which is not possible with existing compact models. The model is implemented in Verilog-A, and is verified against two-dimensional (2-D) numerical device simulations with DESSIS     

A mobility model for carriers in the MOS inversion layer

A mobility model for carriers in the MOS inversion layer is proposed. The model assumes that mobility is a function of the gate and drain fields, and the doping density, which conforms to Thornber's scaling law. Two-dimensional computer simulation combined with the present mobility model can predict experimental drain current within an error of ± 5 percent. The present model is applicable and suitable for designing short-channel MOSFET's, especially in the submicrometer range. The "saturation velocity" in the MOS inversion layer is also discussed, based on Thornber's scaling law. The saturation velocity, as determined from the calculated drain current in the same way as experimentalists have done, is 6.6 × 10⁶cm/s. This is close to what has been claimed to be "saturation velocity in the inversion layer," and is about two-thirds of microscopic saturation velocity. This lower saturation velocity originates from the nonuniform field distribution in the test device, and, therefore, the experimentally reported saturation velocity in the MOS inversion layer is inferred to be a macroscopic average, rather than the microscopic drift velocity.     

New device degradation due to `cold' carriers created byband-to-band tunneling

Device degradation caused by so-called `cold' carriers due to band-to-band tunneling in a MOS drain region is studied. The cold carriers acquire energy from the electric field in the drain region and surmount the Si-SiO₂ barrier. In an n-channel device, injected holes cause a decrease in the tunnel current and a negative MOS threshold-voltage shift opposite to that observed in hot-carrier degradation previously reported. A simple analytical model is presented. This model agrees well with the experimental data in both n- and p-channel devices     

Reexamination of the role of nitrogen in oxynitrides-fixed chargereduction in the p+-polysilicon gate MOS

The problems associated with the use of p⁺-polysilicon gate MOS have been intensively investigated. Although the utilization of oxynitrides has been considered to be effective for the suppression of the threshold voltage (V_T) deviation in the p⁺-polysilicon gate MOSFETs, the investigation revealed that the p⁺-polysilicon gate MOS exhibits significantly different properties when oxynitrides contain no nitrogen at the oxynitride/substrate interface (MOS interface) than it does with usual oxynitrides which contain nitrogen at the MOS interface. This discrepancy arises because, contrary to what is usually considered to be the case, boron diffused into the substrate is not the origin of the negative fixed charge generated in the p⁺-polysilicon gate MOS structures, which is one of the most important factors influencing VT in those structures. We have found fluorine in the p⁺-polysilicon gate MOS structures even when the polysilicon is doped using boron ion implantation. This is a consequence of the use of BF₃ as a boron source. We propose a model in which fluorine is responsible for the negative fixed charge generation and nitrogen at the MOS interface prevents not only the boron penetration but also the negative fixed charge generation by suppressing the fluorine incorporation into the MOS interface     

Short-channel MOSFET VT-VDScharacteristics model based on a point charge and its mirror images

Short-channel MOS transistordV_{T}/dV_{DS}characteristics are expressed by an analytic function of fundamental device parameters. The expression is derived from a simple model of short-channel MOS transistors in threshold condition, which is based on a point charge and its mirror images. With this expression,dV_{T}/dV_{DS}is found to be proportional to1/L^{2}-1/L^{4}, whereLis channel length. Following factors are also found, wherein the source and drain junction depth effect is only logarithmic ondV_{T}/dV_{DS}characteristics,dV_{T}/dV_{SUB}anddV_{T}/dV_{DS}are closely related in short-channel MOS transistors, and short-channel effects are expected to be smaller in MOS transistors on SOS than on bulk silicon, due to a large number of Si/sapphire interface states. This model is simple, and it can be applied to short-channel MOS transistor designing and circuit simulations.     

Gate resistance modeling of multifin MOS devices

This letter studies the effects of geometrical parameters (fin spacing, fin height and polysilicon thickness) on the gate resistance of multifin MOS devices. An effective lumped resistance model derived from distributed RC network is formulated and verified using a two-dimensional simulator. Based on the model, a design guideline for the fin spacing to minimize the gate resistance and RC delay is provided to design multifin MOS devices for high frequency applications.     

Capacitance-voltage characterization of fully silicided gated MOS capacitor

This paper investigates the capacitance-voltage (C-V) measurement on fully silicided (FUSI) gated metal-oxide-semiconductor (MOS) capacitors and the applicability of MOS capacitor models. When the oxide leak-age current of an MOS capacitor is large, two-element parallel or series model cannot be used to obtain its real C-V characteristic, A three-element model simultaneously consisting of parallel conductance and series resistance or a four-element model with further consideration of a series inductance should be used. We employed the three-element and the four-element models with the help of two-frequency technique to measure the Ni FUSI gated MOS capacitors. The results indicate that the capacitance of the MOS capacitors extracted by the three-element model still shows some frequency dispersion, while that extracted by the four-element model is close to the real capacitance, showing little frequency dispersion. The obtained capacitance can be used to calculate the dielectric thickness with quantum effect correction by NCSU C-V program. We also investigated the influence of MOS capacitor's area on the measurement accuracy. The results indicate that the decrease of capacitor area can reduce the dissipation fac-tor and improve the measurement accuracy. As a result, the frequency dispersion of the measured capacitance is significantly reduced, and real C-V characteristic can be obtained directly by the series model. In addition, this pa-per investigates the quasi-static C-V measurement and the photonic high-frequency C-V measurement on Ni FUSI metal gated MOS capacitor with a thin leaky oxide. The results indicate that the large tunneling current through the gate oxide significantly perturbs the accurate measurement of the displacement current, which is essential for the quasi-static C-V measurement. On the other hand, the photonic high-frequency C-V measurement can bypass the leakage problem, and get reliable low-frequency C-V characteristic, which can be used to evaluate whether the full silicidation has completed or not, and to extract the interface trap density of the SiO2/Si interface.     

Closed-form breakdown voltage model for PD SOI NMOS devices considering impact ionization of both parasitic BJT and surface MOS channel simultaneously

This paper reports a compact breakdown voltage model for partially depleted (PD) silicon-on-insulator (SOI) n-metal-oxide-semiconductor (NMOS) devices considering BJT/MOS impact ionization. Via the improved current conduction model considering BJT/MOS impact ionization this compact model provides an accurate prediction of the breakdown behavior of the PD SOI NMOS devices as verified by the experimental data and the MEDICI results. Based on the analytical model, when the gate voltage is lowered, the breakdown voltage decreases due to a stronger function of the parasitic BJT. In the subthreshold region, the breakdown voltage increases at a decreased gate voltage due to a weaker function of the parasitic BJT.     

实用于电路模拟的微米级MOSFET开启电压解析模型的研究

本文在分析了SPICE II-MOS2,MOS3模型中所存在的问题之后,重新建立了一个实用于电路模拟的微米级MOSFET解析模型──MOS5模型(本文仅限于介绍其开启电压模型部分).经实验证明,此模型适用于对不同工艺制得的各种尺寸增强型MOS管的开启电压模拟(L_(eff)≥1.0μm).与原SPICEII-MOS2,MOS3模型相比,此新模型具有参数简单易得、物理意义明确、以工艺参数为主等特点.此模型现已装入SPICE II程序中,达到了实用的目的,并可对VLSI设计与制造起一定的指导作用.     

A model for evaluating talker echo and sidetone in a telephonetransmission network

An objective evaluation model called OPINE (overall performance index model for network evaluation) which is being studied for telephone transmission quality is described. The model estimates an MOS (mean opinion score) by summing psychological values on independent psychological factors, given the physical values of fundamental listening factors such as loss and noise. For the model to incorporate new talking factors such as talker echo and sidestone, evaluation characteristics are studied when both listening and talking factors are present in a telephone transmission system. The interaction of the listening and talking factors is discussed, and it is shown experimentally that these factors are independent of fundamental listening factors. From these results, an extended OPINE is proposed by establishing new psychological factors: talker echo and sidestone. The estimated MOS for composite conditions of listening and talking factors agrees well within the confidence interval of subjective MOS deviation     

Frequency response of charge transfer in MOS inversion layers

The dynamics of charge transfer from a reservoir into an MOS inversion layer, which limits the frequency response of an MOS transistor or a charge-coupled device, is investigated. Using Berman and Kerr's model of space-charge capacitance in the semiconductor, a small-signal distributed model is developed for an MOS structure which transfers charge in an inversion channel due to a variation in the gate voltage. The dynamics of the charge transfer is characterized by a time constant which is determined by the length of the inversion channel and its mobility. Experimental data of gate capacitance vs frequency, taken from a test structure with a diffused source/drain well, are satisfactorily fitted by theoretical curves derived from the model. The channel mobility is precisely determined from the adjusted time constant. The influence of interface states on the capacitance-frequency relationship is also briefly discussed.     

Small-signal analysis of the gate-controlled diode

This paper describes the small signal behavior of MOS gate-controlled diodes. An expression for the capacitance of this device is developed from basic device physics equations. Computer calculations are compared with measured data and the model is seen to predict both the frequency and voltage dependence of the capacitance. The development of this model was made possible through the careful decomposition of teh basic MOS equations into time dependent and static parts.     

A new and improved physics-based model for MOS transistors

An improved MOS device model is derived based upon a first-order model for the dependency of MOS surface mobility on surface field and lateral drain field. A comparison with experimental data shows that a consistent set of physical parameters can be used to describe both long-channel nMOS devices and short-channel devices. The model can form the basis for improved compact MOS models for circuit analysis.     

Large-signal linearity of scaled MOS transistors

The tendency toward linearity between saturated drain current and gate-to-source voltage exhibited by small-dimension MOS transistors is explored from the standpoint of possible exploitation in analog MOS circuits. Nonlinearity is calculated using a simple MOS model which includes the high field dependence of inversion-layer carrier mobility. The nonlinearity for devices with a wide range of channel lengths and gate dielectric thicknesses was measured and is compared to results from the model. Some problems associated with the use of short-channel MOS transistors in analog circuits are discussed.     

神经MOS晶体管在A/D和D/A转换器中的应用

神经MOS晶体管是一种具有多输入栅加权信号控制和阈值可调控的高功能度的新型器件。以神经MOS晶体管的Pspice宏模型为模拟和验证的工具,讨论了基于这种器件的A/D和D/A转换器的设计思想和方法,证明了他能很大程度地减少晶体管数目,简化电路,对实现高密度集成的ULSI系统的设计和实现有重要意义。     

基于BSIM3模型的毫米波MOS变容管建模

提出了应用于毫米波段的MOS变容管的建模方法。针对标准0.18μm CMOS工艺,采用2D器件仿真软件MINIMOS,设计实现了积累型MOS变容管;并提出和分析了基于标准BSIM3模型的MOS变容管的等效电路模型;通过MINIMOS仿真,直接提取电路模型各寄生参数。该模型能方便地在电路设计软件中实现,并能预测最高达40 GHz频率范围内的变容管特性。     

Holding time degradation in dynamic MOS RAM by injection-induced electron currents

The holding time degradation of a dynamic MOS RAM caused by a peripheral MOS device operated in the saturation region is discussed. It is shown that the process taking place is injection of electrons into a positively biased substrate region from a grounded junction. This junction becomes forward biased due to the resistive potential drop on the substrate caused by the high substrate current of the short-channel MOS device operated in the saturation region. The model presented in the literature of secondary-impact ionization of holes in the depletion-region edge being responsible for the degradation phenomenon is shown to be inconsistent with experimental results and theoretically improbable.     

基于回路的MOS电阻阵单像素红外模型建模方法研究

MOS电阻阵目前在红外仿真领域有着广泛的应用和重要的作用。作为红外半实物仿真链路中的核心器件,其成像效果直接关系到最终仿真结果的准确度和置信度。目前的红外仿真数字信号进入电阻阵后会产生一系列图像退化和耦合失真问题,因此需要从MOS电阻阵的成像机理出发,分析其成像原理及能量传递过程,针对单个像元建立符合其自身物理特性的过程及辐射模型。通过输入信号与输出信号的函数关系来量化和验证模型的准确度和置信度。这个模型作为MOS电阻阵的基础模型对未来研究更大规模电阻阵的耦合特性、反向模型及非均匀性校正均有重要的理论基础和实际工程应用价值和意义。