Avalanche multiplication noise characteristics in thin GaAs p+-i-n+ diodes

Avalanche noise measurements have been performed on a range of homojunction GaAs p⁺-i-n⁺ and n⁺-i-p ⁺ diodes with “i” region widths, ω from 2.61 to 0.05 μm. The results show that for ω⩽1 μm the dependence of excess noise factor F on multiplication does not follow the well-established continuous noise theory of McIntyre [1966]. Instead, a decreasing noise factor is observed as ω decreases for a constant multiplication. This reduction in F occurs for both electron and hole initiated multiplication in the thinner ω structures even though the ionization coefficient ratio is close to unity. The dead-space, the minimum distance a carrier must travel to gain the ionization threshold energy, becomes increasingly important in these thinner structures and largely accounts for the reduction in noise     

Carbon-doped base GaAs-AlGaAs HBT's grown by MOMBE and MOCVDregrowth

High-quality GaAs-AlGaAs heterojunction bipolar transistors (HBTs) in which the carbon-doped base layers (p=10¹⁰-10²⁰ cm^-3, 400-800 Å thick) and Sn-doped collector and subcollector layers are grown by metalorganic molecular-beam epitaxy (MOMBE) and a subsequent regrowth using metalorganic chemical vapor deposition (MOCVD) is used to provide the n⁺ AlGaAs emitter and GaAs/InGaAs contact layers are discussed. A current gain of 20 was obtained for a base doping of 10¹⁹ cm^-3 (800 Å thick) in a 90-μm-diameter device, with ideality factors of 1.0 and 1.4 for the base-collector and emitter-base junctions, respectively, demonstrating the excellent regrowth-interface quality. For a base doping of 10²⁰ cm^-3 (400 Å thick), the current gain decreased to 8     

A measurement method of the injection dependence of theconductivity mobility in silicon

A new electrical method to measure the conductivity mobility as a function of the injection level is proposed in this paper. The measurement principle is based on the detection of the voltage drop appearing across a n⁺-n-n⁺ (p⁺-p-p⁺) structure when a current step is forced into it at a given injection level in the intermediate region. This is obtained by using a three-terminal test pattern consisting of p⁺ , n⁺ layers realized on top of a n-n⁺ (p-p ⁺) epitaxial wafer, where the p⁺-n-n⁺ (n⁺-p-p⁺) surface diode is forward biased to monitor the conductivity of the epilayer. The use of separate terminals for injection control and mobility measurement allows this technique to overcome some limitations presented by other electrical methods available in literature, Mobility values measured up to 2·10¹⁷ cm^-3 are in good agreement with those predicted by the Dorkel and Leturcq's model (1981)     

Isolated emitter AlGaAs/GaAs HBT integrated with emitter-down HI2L technology

A process that integrates isolated-emitter heterojunction bipolar transistors (HBTs) with common-emitter HBTs in the emitter-down epi structure on n⁺ substrates is discussed. Overgrowth of the epi onto a p^- implanted region results in back-to-back diodes for ~12-V vertical isolation. Isolated transistors are used in emitter-follower output buffers for heterojunction injection logic (HI ²L) ring oscillators, demonstrating the integration of the two transistor types     

Alpha-particle-induced charge transfer between n+regions in high-density trench DRAM with isolated p-well structures

Alpha-particle-induced charge transfer (ACT) between n⁺ regions inherent in isolated p-well structures is described. The isolated p-well structures in Si ICs such as advanced trench DRAM cells can cause anomalous charge collection through the ACT. The collected charge is evaluated for advanced trench DRAM cells by circuit and device simulations. In addition, this mechanism is compared to charge transfer in devices with ordinary p-well structures by means of simulations of generalized model structures. It is concluded that ACT with isolated p-well structures may cause a significant problem with scaling, whereas ACT with ordinary p-well structures can be avoided by following a proposed scaling law     

Excess Avalanche Noise in In0.52Al0.48As

Avalanche multiplication and excess noise arising from both electron and hole injection have been measured on a series of In_0.52Al_0.48As p⁺-i-n⁺ and n ⁺-i-p⁺ diodes with nominal avalanche region widths between 0.1 and 2.5 mum. With pure electron injection, low excess noise was measured at values corresponding to effective k=beta/alpha between 0.15 and 0.25 for all widths. Enabled ionization coefficients were deduced using a non-local ionization model utilizing recurrence equation techniques covering an electric field range from approximately 200 kV/cm to 1 MV/cm     

InP/InGaAs HBTs with n+-InP contacting layers grown byMOMBE using SiBr4

InP/InGaAs heterojunction bipolar transistors (HBTs) with low resistance, nonalloyed TiPtAu contacts on n⁺-InP emitter and collector contacting layers have been demonstrated with excellent DC characteristics. A specific contact resistance of 5.42×10^-8 Ω·cm², which, to the best of our knowledge, is the lowest reported for TiPtAu on n-InP, has been measured on InP doped n=6.0×10¹⁹ cm^-3 using SiBr₄. This low contact resistance makes TiPtAu contacts on n-InP viable for InP/InGaAs HBTs     

Analytical solutions for the breakdown voltages of punched-through diodes having curved junction boundaries at the edges

Analytical expressions are derived for the breakdown voltages of punched-through diodes having a plane structure terminated with cylindrical and spherical curved boundaries at the edges, through the use of suitable approximations for the electric field in the depletion layer. The expressions derived include both p⁺-i-n⁺and p⁺-p-n⁺(or p⁺-n-n⁺) types and are given in terms of the middle-region (i-layer or p-layer) width, the radius of curvature of the junction edge, the punch-through voltage, and the plane parallel breakdown voltage of p⁺-i-n⁺diodes. The results obtained include a correlation between the middle-region (p-layer) width and the width of the depletion layer in the curved portions of the junction when the applied reverse bias across the diode is just sufficient so that punchthrough takes in the portions where the junction is plane parallel. These results are made use of in the breakdown voltage calculations.     

Alpha-particle-induced charge collection in p-n junction diodes insemi-insulating GaAs substrates

The bias and angle dependences of the alpha-particle-induced charge collected by GaAs p-n junction diodes are investigated. These diodes, in which the n-layer overlays the p-layer, are fabricated in a semi-insulating GaAs substrate by Si and Mg ion implantation. ²⁴¹ Am placed in a vacuum is used as an alpha-particle source with an initial energy of 4.03 MeV and a fluence of 5.4×10^-5/s/μm². The results show that the collected charge is nearly independent of the applied bias. This bias independence may be further evidence that the charge funneling process is not important in semi-insulating GaAs. A model not incorporating funneling can explain the measured angular dependence. Based on this model, the design principle for the buried p-layer structure is discussed     

Soft-error-immune switched-load-resistor memory cell

A soft-error-immune switched-load-resistor memory cell especially suitable for ultrahigh-speed bipolar RAM has been developed. The memory cell is composed of upward sidewall base contact structure (SICOS) transistors and shielded Schottky-barrier diodes (SBDs). Alpha-particle-induced noise charges generated in the p^--substrate are completely shielded by n⁺-buried layers of the transistors and the SBDs. Only the noise charges generated in the transistors or the SBDs active regions are gathered in the collectors of the memory cell. The maximum collected noise charge is reduced to a quarter of that of conventional memory cells using SICOS downward transistors and conventional SBDs. Experiments show that this reduction of the collected noise charge increases soft-error immunity to more than 10⁵ times that of conventional memory cells. This result using hot radiation sources does not directly correspond to the real soft-error rate in the field, but demonstrates the realization of an ultrahigh-speed soft-error-immune memory cell     

Experimental study of the minority-carrier transport at the polysilicon—monosilicon interface

This paper presents the results of an experimental study designed to explore both qualitatively and quantitatively the mechanism of the improved current gain in bipolar transistors with polysilicon emitter contacts. Polysilicon contacts were deposited and heat treated at different conditions. The electrical properties Were measured using p-n junction test structures that are much more sensitive to the contact properties than are bipolar transistors. A simple phenomenological model was used to correlate, the structural properties with electrical measurements. Possible transport mechanisms are examined and estimates are made about upper bounds on transport parameters in the principal regions of the devices. The main conclusion of this study is that the minority-carrier transport in the polycrystalline silicon is dominated by a highly disordered layer at the polysilicon-monosilicon interface characterized by very low minority-carrier mobility. The effective recombination velocity at the n⁺polysilicon-n⁺monosilicon interface was found to be a strong function of fabrication conditions. The results indicate that the recombination velocity can be much smaller than 10⁴cm/s.     

A new random walk model for PCS networks

This paper proposes a new approach to simplify the two-dimensional random walk models capturing the movement of mobile users in personal communications services (PCS) networks. Analytical models are proposed for the new random walks. For a PCS network with hexagonal configuration, our approach reduces the states of the two-dimensional random walk from (3n²+3n-5) to n(n+1)/2, where n is the layers of a cluster. For a mesh configuration, our approach reduces the states from (2n2-2n+1) to (n²+2n+4)/4 if n is even and to (n ²+2n+5)/4 if n is odd. Simulation experiments are conducted to validate the analytical models. The results indicate that the errors between the analytical and simulation models are within 1%. Three applications (i.e., microcell/macrocell configuration, distance-based location update, and GPRS mobility management for data routing) are used to show how our new model can be used to investigate the performance of PCS networks     

A high-gain GaAs/AlGaAs n-p-n heterojunction bipolar transistor on(100) Si grown by molecular beam epitaxy

High-gain GaAs/AlGaAs n-p-n heterojunction bipolar transistors (HBT's) on Si substrates grown by molecular beam epitaxy (MBE) have been fabricated and tested. In this structure, an n⁺-InAs emitter cap layer was grown in order to achieve a nonalloyed ohmic contact. Typical devices with an emitter dimension of 50×50 μm² exhibited a current gain as high as 45 at a collector current density of 2×10³ A/cm² with an ideality factor of 1.4. This is the highest current gain reported for HBT's grown on Si substrates. Breakdown voltages as high as 10 and 15 V were observed for the emitter-base and collector-base junctions respectively. The investigation on devices with varying emitter dimensions demonstrates that much higher current gains can be expected     

Carrier distribution and low-field resistance in short n+-n--n+and n+-p--n+structures

In the present paper, we calculate the potential, field, and carrier distributions in short n⁺-n^--n⁺and n⁺-p^--n⁺devices and estimate the low-field resistance. The results of the calculations present a set of universal curves which may be used to find the minimum carrier density in the sample, the barrier height, the electric field at the boundary, etc. Our calculations show that electron injection becomes very important when the doping level is smaller than 1.5 × 10¹⁴(cm^-3). (T/300 K)/ L²(µm) for GaAs diodes, whereLis the sample length. The low-field resistance of the sample is limited by the thermionic emission of the sample and by the diffusion and drift in the sample. The thermionic emission dominates at low temperatures, in short samples, and the diffusion-drift dominates in longer samples at higher temperatures. The experimental values of low-field resistance for GaAs 0.4-µm n⁺-n^--n⁺devices at 77 and 300 K are in good agreement with the predicted values. The agreement is not so good for 0.25-µm devices and for n⁺-p^--n⁺devices. In the latter case, the disagreement may be due to uncertainty in the doping level because the low-field resistance of the n⁺-p^--n⁺structure is shown to be very sensitive to the doping level of the p-region.     

On the behaviour of buried oxygen implanted layers in highly doped GaAs

Highly doped GaAs substrate material (doping level 10¹⁸ cm⁻³) has been implanted with 350 keV O⁺ ions with doses of 10¹⁴ – 10¹⁶ cm⁻² to produce high resistivity layers which are stable at high temperatures. LPE growth of flat GaAs epilayers onto the implanted wafers was achieved up to doses of about 1 × 10¹⁵ O⁺/cm² and 5 × 10¹⁵O⁺/cm² for RT and 200°C implants, respectively. N-o-n and p-o-n structures (o: oxygen implanted) were fabricated in which breakdown voltages of up to 15 V were obtained. Examples for application of this isolation technique are shown.     

The electron impact ionization rate and breakdown voltage inGaAs/Ga0.7Al0.3As MQW structures

The electron impact ionization rate (α) and breakdown voltage (V_BD) experimentally measured in a p⁺ -i-n⁺ diode structure with a GaAs/Ga_0.7Al _0.3As multiple quantum-well (MQW) i region are discussed. For structures with GaAs wells of 100 Å and barriers that vary from 7 to 60 Å in thickness, it is found that α is always less than α in bulk GaAs and that it decreases with increasing barrier thickness. The normalized V_BD also increases with increasing barrier thickness, confirming a decreasing ionization rate     

Dramatic increases in latchup holding voltage for sub-0.5 μmCMOS using shallow S/D junctions

Large increases in the latchup holding voltage are demonstrated with the use of shallow source-drain junctions in a sub-0.5 μm CMOS process. Holding voltages well above the supply voltage for 2 μm n ⁺/p⁺ spacings are demonstrated without the use of complex processes such as retrograde wells or buried layers. SIMS data is presented to verify the reduction in junction depths to 0.15 μm for the p⁺/n-well and 0.14 μm for the n⁺/p-well junction. The improvement in holding voltage is attributed to reductions in parasitic bipolar transistor gains, due to the increase in base width. Well behaved transistor characteristics are presented using the shallow junction technology     

Electrical characterization of ultra-shallow junctions formed bydiffusion from a CoSi2 layer

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi₂ was implanted with As or with BF₂ and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 ^-10 A/cm² for p⁺/n and 2.7×10^-9 A/cm² for n⁺/p, respectively. The temperature dependence of the reverse current in the p ⁺/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n⁺/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p⁺ /n junctions have an ideal behavior, while the n⁺/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi₂, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n⁺/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness     

Optimization of the germanium preamorphization conditions forshallow-junction formation

Shallow p⁺-n and n⁺-p junctions were formed in germanium preamorphized Si substrates. Germanium implantation was carried out over the energy range of 50-125 keV and at doses from 3×10¹⁴ to 1×10¹⁵ cm^-2. p ⁺-n junctions were formed by 10-keV boron implantation at a dose of 1×10¹⁵ cm^-2. Arsenic was implanted at 50 keV at a dose of 5×10¹⁵ cm^-2 to form the n⁺-p junctions. Rapid thermal annealing was used for dopant activation and damage removal. Ge, B, and As distribution profiles were measured by secondary ion mass spectroscopy. Rutherford backscattering spectrometry was used to study the dependence of the amorphous layer formation on the energy and dose of germanium ion implantation. Cross-sectional transmission electron microscopy was used to study the residual defects formed due to preamorphization. Complete elimination of the residual end-of-range damage was achieved in samples preamorphized by 50-keV/1×10¹⁵ cm^-2 germanium implantation. Areal and peripheral leakage current densities of the junctions were studied as a function of germanium implantation parameters. The results show that high-quality p⁺-n and n⁺-p junctions can be formed in germanium preamorphized substrates if the preamorphization conditions are optimized     

Avalanche Multiplication in InAlAs

A systematic study of avalanche multiplication on a series of In _0.52Al_0.48As p⁺-i-n⁺ and n ⁺-i-p⁺ diodes with nominal intrinsic region thicknesses ranging from 0.1 to 2.5 mum has been used to deduce effective ionization coefficients between 220 and 980 kVmiddotcm^-1. The electron and hole ionization coefficient ratio varies from 32.6 to 1.2 with increasing field. Tunneling begins to dominate the bulk current prior to avalanche breakdown in the 0.1-mum-thick structure, imposing an upper limit to the operating field. While the local model can accurately predict the breakdown in the diodes, multiplication is overestimated at low fields. The effects of ionization dead space, which becomes more significant as the intrinsic region thickness reduces, can be corrected for by using a simple correction technique