AFDX端系统的Linux驱动程序设计与实现

为了满足航空电子系统对确定性和实时性的要求,针对AFDX端系统硬件结构,功能需求和Linux驱动程序的特点,提出了一种满足AFDX协议的Linux内核态驱动程序的实现方法。在Linux内核态驱动程序的实现中先注册一个PCI总线驱动程序,然后在PCI总线驱动程序中注册字符型设备驱动程序。字符型设备驱动程序注册成功后,在其open()函数中注册中断处理程序,利用其ioctl()函数实现初始化表和端口,利用read()和write()函数来读写设备。测试结果显示,该Linux内核态驱动程序的设计和实现是可以满足航空电子系统对确定性和实时性的要求的。     

The influence of parameter initialization on the training time and accuracy of a nonlinear regression model

In order to construct a nonlinear regression model we have to accurately (in some sense) initialize parameters of the model. In this work we performed comparison of several widely used methods and several newly developed approached for initialization of parameters of a regression model, represented as a decomposition in a linear dictionary of some parametric functions (sigmoids). We proposed a general deterministic approach for initialization, providing repeatability of results, reduction of a learning time and in some cases increase of a regression model accuracy; we developed two new algorithms (based on a piecewise-linear approximation and based on local properties of approximable dependency) in the framework of the proposed approach; we developed randomized initialization algorithm (spherical initialization) for effective approximation of high-dimensional dependencies; we improved the classical initialization method SCAWI (by locating centers of sigmoids in sample points), providing a regression model accuracy improvement on specific classes of dependencies (smooth functions and discontinuous functions with a number of local peculiarities in an input domain) when using RProp algorithm for learning; we performed comparison of classical and newly proposed initialization methods and highlighted the most efficient ones.     

Scalable and modular memory-based systolic architectures for discrete Hartley transform

In this paper, we present a design framework for scalable memory-based implementation of the discrete Hartley transform (DHT) using simple and efficient systolic and systolic-like structures for short and prime transform lengths, as well as, for lengths 4 and 8. We have used the proposed short-length structures to construct highly modular architectures for higher transform lengths by a new prime-factor implementation approach. The structures proposed for the prime-factor DHT, interestingly, do not involve any transposition hardware/time. Besides, it is shown here that an N-point DHT can be computed efficiently from two (N/2)-point DHTs of its even- and odd-indexed input subsequences in a recursive manner using a ROM-based multiplication stage. Apart from flexibility of implementation, the proposed structures offer significantly lower area-time complexity compared with the existing structures. The proposed schemes of computation of the DHT can conveniently be scaled not only for higher transform lengths but also according to the hardware constraint or the throughput requirement of the application.     

Analog computational models of concept formation

This paper proposes and describes a method of inductive concept learning, a method suitable for implementation in parallel computational mode with analog VLSI neural-net circuitry. The approach is consonant with the original Perceptron approach. However, weights along linear links are not learned adaptively. Instead, the net depends upon the frequency of occurrence to adjust the strength of activation generated by an input and the attention paid to the input. Of critical importance are the relative magnitudes of the information complexity of the concept to be learned and the complexity of the implementation hardware. If the former exceeds the latter, the concept cannot be learned. The manner in which failure is signaled and hardware complexity is increased is described in this paper.     

System Level Design for Clustered Wireless Sensor Networks

We present a system level design methodology for clustered wireless sensor networks based on a semi-random communication protocol called SERAN, a mathematical model that allows to optimize the protocol parameters, and a network initialization and maintenance procedure. SERAN is a two-layer (routing and MAC) protocol. At both layers, SERAN combines a randomized and a deterministic approach. While the randomized component provides robustness over unreliable channels, the deterministic component avoids an explosion of packet collisions and allows our protocol to scale with network size. The combined result is a high reliability and major energy savings when dense clusters are used. Our solution is based on a mathematical model that characterizes performance accurately without resorting to extensive simulations. Thanks to this model, the user needs only to specify the application requirements in terms of end-to-end packet delay and packet loss probability, select the intended hardware platform, and the protocol parameters are set automatically to satisfy latency requirements and optimize for energy consumption.     

柔性稀疏阵的稳健波束形成

本文将导向矢量失配时的稳健波束形成问题归结为二次锥规划问题,利用高效的内点法求解。该波束形成器成功地应用于存在阵元位置误差的柔性稀疏阵,相对于经典的对角线加载法、特征空间法,在不同的输入信噪比下获得了更好的输出信号干扰加噪声比。仿真结果表明对超稀疏分布的柔性阵,阵元位置误差对输出SINR起决定性影响,而阵列稀疏程度对其影响不大。     

一种基于傅里叶基神经网络的频谱分析方法

该文提出了一种用递推最小二乘法训练傅里叶基神经网络权值的频谱分析方法。其主要思想是采用递推最小二乘法训练傅里叶基神经网络权值,根据权值获得信号的幅度谱和相位谱。该方法不涉及复数的乘法运算和加法运算,便于软件和硬件实现,特别适合于DSP软硬件实现。仿真结果表明,该方法不仅计算精度高,计算速度快,而且具有噪声滤波功能,是一种有效的频谱分析方法。     

Projection based prefiltering for multiwavelet transforms

We introduce a method for initializing the multiwavelet decomposition algorithm. The initialization procedure is the orthogonal projection of the input signal into the space defined by the multiscaling function. The approach will always have a solution, places no restrictions on the input (except that it be contained within L₂ ), and can be implemented in a fast algorithm. We present the details of our approach and compare it with another proposed method of prefiltering     

二进前向多层神经网络实现的研究

文章提出一种硬件实现二进前向多层神经网络及其硬限幅函数的方法。所设计的神经元电路的权值和阈值均为片内存储的整数，可取负值，也可学习，当输入模式要求更大的维数时可以扩展。仿真结果符合要求。     

Performance analysis of LMS adaptive prediction filters

The conditions required to implement real-time adaptive prediction filters that provide nearly optimal performance in realistic input conditions are delineated. The effects of signal bandwidth, input signal-to-noise ratio (SNR), noise correlation, and noise nonstationarity are explicitly considered. Analytical modeling, Monte Carlo simulations and experimental results obtained using a hardware implementation are utilized to provide performance bounds for specified input conditions. It is shown that there is a nonlinear degradation in the signal processing gain as a function of the input SNR that results from the statistical properties of the adaptive filter weights. The stochastic properties of the filter weights ensure that the performance of the adaptive filter is bounded by that of the optimal matched filter for known stationary input conditions     

Mixed Mode VLSI Implementation of a Neural Associative Memory

A mixed mode digital/analog special purpose VLSI hardware implementation of an associative memory with neural architecture is presented. The memory concept is based on a matrix architecture with binary storage elements holding the connection weights. To enhance the processing speed analog circuit techniques are applied to implement the algorithm for the association. To keep the memory density as high as possible two design strategies are considered. First, the number of transistors per storage element is kept to a minimum. In this paper a circuit technique that uses a single 6-transistor cell for weight storage and analog signal processing is proposed. Second, the device precision has been chosen to a moderate level to save area as much as possible. Since device mismatch limits the performance of analog circuits, the impact of device precision on the circuit performance is explicitly discussed. It is shown that the device precision limits the number of rows activated in parallel. Since the input vector as well as the output vector are considered to be sparsely coded it is concluded, that even for large matrices the proposed circuit technique is appropriate and ultra large scale integration with a large number of connection weights is feasible.     

A NEW IMEMENTATION FOR DFT BASED ON DELTA MODULATION

This paper proposes a new implementation for DFT based on delta modulation which isdifferent from the conventional PCM implementation.The hardware structure of the method is multiplier-free,simple and low in cost.Theoretical analyses show that its SNR can approach conventional one's,forinstance,FFT.Computer simulations demonstrate that for deterministic signals,the results agree withtheoretical analyses.For handlimited Gaussian signals,we can still get results similar to the conventionalDFT's if selecting the step size suitably.A hardware structure which simply consists of ROM,an adder andother auxiliary circuits is also given.     

一种不用乘法器的增量调制DFT新结构

本文提出一种基于增量调制(DM)序列的离散傅里叶变换(DFT)结构,它不同于基于脉冲编码调制(PCM)的常规方法。提出这一想法是为了解决在常规的数字信号处理中的乘法运算问题,从而减小系统的复杂性,降低设备成本。我们将看到,本文提出的新的DFT结构取消了A/D变换器和乘法器,可望简化硬件设计、降低造价,而信噪比同样能够达到与常规的处理方法,如FFT相近的结果。计算机模拟表明,对于确定性信号,结果与常规的DFT相一致。对于带限高斯信号,只要适当地选择步长和过采样率系数,同样也能得到与常规DFT相近的结果。我们采用ROM存贮各个系数值,因此,整个运算完全是阅读和求和的过程,因而速度快,硬件结构简单,适用于语音、地震等信号的处理。本文最后给出了硬件实现方案和各个参数的选择方法,同时提供了计算机模拟结果。     

A Practical Parallel Architecture for Stacks Filters

Stack filters belong to the class of non-linear filters and include the well-known median filter, weighted median filters, order statistic filters and weighted order statistic filters. Any stack filter can be implemented by using the parallel threshold decomposition architecture which allows implementing their non-linear processing by means of a collection of identical binary filters (Boolean logic circuits). Although it is conceptually simple and useful to study the filter properties, this architecture is not practical for direct hardware implementation because as many as (M – 1) binary filters are required for a M-valued input signal and M is large in many applications.In this paper we introduce a new parallel architecture for stack filter implementations. The complexity is now proportional to the window width L of the filter, instead of to M. In most applications L is much smaller than M which translates into efficient hardware implementations. The attractive characteristic of ease of design exhibited by the threshold decomposition architecture is kept. In fact, for a given stack filter both in the conventional implementation and in the proposed one, the same binary filter is required. The key concept supporting the new architecture is a modified decomposition scheme which generates L binary signals for a multi-valued input. As an application example, a complex WOS filter is designed and prototyped in an FPGA.     

A new implementation for DFT based on delta modulation

This paper proposes a new implementation for DFT based on delta modulation which is different from the conventional PCM implementation. The hardware structure of the method is multiplier-free, simple and low in cost. Theoretical analyses show that its SNR can approach conventional one's, for instance, FFT. Computer simulations demonstrate that for deterministic signals, the results agree with theoretical analyses. For bandlimited Gaussian signals, we can still get results similar to the conventional DFT's if selecting the step size suitably. A hardware structure which simply consists of ROM, an adder and other auxiliary circuits is also given. This Project is supported by the National Natural Science Fundation of China.     

A co-synthesis approach to embedded system design automation

Embedded systems are targeted for specific applications under constraints on relative timing of their actions. For such systems, the use of pre-designed reprogrammable components such as microprocessors provides an effective way to reduce system cost by implementing part of the functionality as a program running on the processor. However, dedicated hardware is often necessary to achieve the requisite timing performance. Analysis of timing constraints is, therefore, key to determination of an efficient hardware-software implementation. In this paper, we present a methodology for embedded system design as a co-synthesis of interacting hardware and software components. We present a decomposition of the co-synthesis problem into sub-problems, that is useful in building a framework for embedded system CAD. In particular, we present operation-level timing constraints and develop the notion of satisfiability of constraints by a given implementation both in the deterministic and probabilistic sense. Constraint satisfiability analysis is then used to define hardware and software portions of functionality. We describe algorithms and techniques used in developing a practical co-synthesis framework, vulcan. Examples are presented to show the utility of our approach.     

基于FPGA的硬盘控制与加密

本文介绍了硬盘接口和工作原理.提供了一种FPGA实现ATA协议的方式.并且对协议的时序进行了分析和实现.最后详细介绍了存储和加密两个模块的具体实现并且通过数据显示进行了验证.较之传统接口驱动设备,该方案中.硬盘初始化.存储.格式化等功能完全可以脱机使用;另外只需通过USB接口芯片与计算机的USB接口相连.就可以在计算机界面上完成读取.加密等功能.具有很强的实用性和灵活性.     

Advances in binary decision based programmable controllers

Binary decision automata are finite state machines that evaluate switching functions by means of decision rather than Boolean logic. The capability of binary decision machines (BDMs) to evaluate sequential functions is addressed by the authors. The BDM is shown to be less powerful than the deterministic finite automation (DFA) model from automata theory. However, an extended BDM with input control is shown to be equivalent to the DFA and thus can be used to implement finitely computable sequential functions. The use of a BDM finite automaton instead of a more general model is motivated on the basis of expected case time and space complexity analysis. A hardware design following from this analysis is described, and programming methods are discussed     

基于PowerPC的RapidIO高速串行通信设计与实现

提出了采用基于PowerPC架构的MPC8548E为主机的高速串行RapidIO实现方案,详细阐述了硬件设计要点和软件初始化流程,为以PowerPC为处理器的嵌入式操作系统实现设备间的高速互连提供了一套行之有效的解决方案.