Control of bus headways by traffic signal timing methods

Bus bunching causes uneven passenger loadings and increases the average passenger waiting time. Bunching is caused by an unstable relationship between delay in the actual bus arrival time and passenger loading time requirements. An appropriate mathematical representation of this process is provided, and the general mathematical requirements for stabilizing the process is described. It is shown how if the time of arrival is known at certain locations, the traffic signals may be appropriately timed to remove this instability and enable the buses to adhere to their schedule with greater precision. An example demonstrating the performance of the algorithm on a particular bus route is provided.     

Computer-controlled vehicular traffic

It is no exaggeration that a kid on roller skates can propel himself crosstown, from the East River to the North River, on any of Manhattan's midtown streets in considerably less time than that required by a motorist. And we all have had the frustrating experience of spending more time in a bus between an airport and center city than in making the actual flight of 500 km or more. About five years ago, Boston, Mass., got a foretaste of what complete vehicular strangulation can be like when the granddaddy of traffic jams immobilized all surface transportation downtown for more than three hours. But the future may not be completely bleak: thanks to the digital computer, sensor inputs?and a lot of software synthesis?traffic intersections can be placed under machine control to break up the traffic bottlenecks that have become one of the major blights of our cities.     

A TDM-based multibus packet switch

A new packet switch architecture using two sets of time-division multiplexed buses is proposed. The horizontal buses collect packets from the input links, while the vertical buses distribute the packets to the output links. The two sets of buses are connected by a set of switching elements which coordinate the connections between the horizontal buses and the vertical buses so that each vertical bus is connected to only one horizontal bus at a time. The switch has the advantages of: (1) adding input and output links without increasing the bus and I/O adaptor speed; (2) being internally unbuffered; (3) having a very simple control circuit; and (4) having 100% throughput under uniform traffic. A combined analytical-simulation method is used to obtain the packet delay and packet loss probability. Numerical results show that for satisfactory performance, the buses need to run about 30% faster than the input line rate. With this speedup, even at a utilization factor of 0.9, each input adaptor requires only 31 buffers for a packet loss rate of 10^-6. The output queue behaves essentially as an M/D/1 queue     

多无线模块通信构建的公交模拟系统

随着城市获得长足的发展,公交运力不足或堵车等问题,以及报站系统的不准确性,会给人们带来较大的困扰。文中公交模拟系统针对现有公交报站存在的不足,提出通过多个无线模块进行无线通信,并应用单片机作为数据的中央处理装置,实现对于一条线路上的公交车的准确定位。     

Performance Analysis for MPEG‐4 Video Codec Based on On‐Chip Network

In this paper, we present a performance analysis for an MPEG‐4 video codec based on the on‐chip network communication architecture. The existing on‐chip buses of system‐on‐a‐chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on‐chip network is introduced to solve the problem of on‐chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG‐4 video codec based on the on‐chip network and Advanced Micro‐controller Bus Architecture (AMBA) on‐chip bus. Experimental results show that the performance of the MPEG‐4 video codec based on the on‐chip network is improved over 50% compared to the design based on a multi‐layer AMBA bus.     

基于嵌入式流媒体服务器的视频点播系统

移动通信网络流媒体服务资费较高,限制了人们在没有有线电视、宽带互联网连接、无线WiFi互联网连接的地方用手机收看视音频节目.针对这一现状,提出了一种基于嵌入式流媒体服务器的多功能视频点播系统.以ARM板和WiFi网络适配器作为流媒体服务器,设计一款Android手机播放器作为客户端,实现在智能手机上、多个客户端同时免流量接收服务器本地或外接设备推送的高清、超高清视频.该系统适用于公交、广场、电梯、商场、景区等场合,人们用手机观看视音频,实现不用耗费自己的流量,自由快速地选择自己喜欢的节目.     

Adaptive low-power address encoding techniques using self-organizing lists

Off-chip bus transitions are a major source of power dissipation for embedded systems. In this paper, new adaptive encoding schemes are proposed that significantly reduce transition activity on data and multiplexed address buses. These adaptive techniques are based on self-organizing lists to achieve reduction in transition activity by exploiting the spatial and temporal locality of the addresses. Also the proposed techniques do not require any extra bit lines and have minimal delay overhead. The techniques are evaluated for efficiency using a wide variety of application programs including SPEC 95 benchmark set. Unlike previous approaches that focus on instruction address buses, experiments demonstrate significant reduction in transition activity of up to 54% in data address buses and up to 59% in multiplexed address buses. The average reductions are twice those obtained using current schemes on a data address bus and more than twice those obtained on a multiplexed address bus.     

Narrow bus encoding for low-power DSP systems

High levels of integration in integrated circuits often lead to the problem of running out of pins. Narrow data buses can be used to alleviate this problem provided that the degraded performance due to wait cycles can be tolerated. We address bus coding methods for low-power core-based systems incorporating narrow buses. We show that transition signaling combined with bus-invert coding, which we call BITS coding, is particularly suitable for the data patterns of typical DSP applications on narrow data buses. The application of BITS coding to real circuit design is limited by the extra bus line introduced, which changes the pinout of the chip. We propose a new coding method, which does not require the extra bus line but retains the advantage of BITS     

基于LwIP协议栈的PCP协议的设计

网络通信技术的迅速发展,电子设备要求远程数据传输功能越来越普遍。现在对于智能仪表的通信,都是通过个工业总线、串口通信来完成的,以后网络通信就会完全替代这些成为唯一的通信方式。为了推动产品的网络化,本文在LwIP协议栈的基础上,提出PCP协议的应用。     

基于AT89C51型单片机的CAN总线智能节点设计

介绍CAN(控制器局域网)总线的特点,给出CAN总线系统智能节点电路原理及用C51语言编写的开发程序,方便使用者学习和掌握.     

Approximate performance analysis of real-time traffic over heavilyloaded networks with timed token protocols

This paper studies timed token protocols with respect to real-time packet traffic in local area networks (LANs), such as FDDI and token bus, employed in distributed control systems. Typically, in such systems, three classes of packet traffic are encountered. The first class consists of packets cyclically generated by data acquisition tasks. The second traffic class is represented by packets generated in a random manner by control tasks and sporadic events. Finally, the third traffic class represents nonreal-time packet streams such as, for example, file transfers. To evaluate protocol performance, three performance measures are taken into account with respect to randomly generated real-time traffic: the mean waiting time, the blocking probability, and the probability that accepted packets will wait for service no longer than a specified time limit. In order to determine the last performance measure, a two-moment approximation of the waiting time distribution is applied. All three performance measures are evaluated at the beginning of the heavy network load region. Two examples of numerical calculations compared with computer simulations done for FDDI-II and token bus networks are given     

基于软件无线电的嵌入式系统总线研究及应用

介绍了软件无线电传统的嵌入式系统并行总线传输方式,分析了高速串行总线相对于 并行总线的优势,比较了当前常用的几种高速串行总线的优劣,指出了RapidIO总线是当前 软件无线电嵌入式系统一种良好选择。同时,通过某项目应用,实现了RapidIO总线高速组 网以及系统开放、可扩展、可重构等性能。     

Fault model for on-chip communication and joint equalization and special spacing rules for on-chip bus design

Achieving high speed and reliability is a key challenge in on-chip bus design. To address the challenge, in this paper we propose a fault model for on-chip communication and further develop a new joint scheme which integrates an equalization technique and special spacing rules for improving the speed and communication reliability for on-chip buses. The proposed equalizer employs a variable threshold inverter whose switching threshold is adjusted as a function of the past output of the buses to achieve high-speed and high-reliability of the buses. Special spacing rules use the sufficient spacing between the adjacent wires to mitigate the crosstalk effect from the adjacent wires. The joint scheme equalization and special spacing rules exploits their respective advantages to further improve the speed and communication reliability of the buses. The simulation results show that the joint scheme equalization and increasing spacing of the uncoded bus can reduce 50% delay and save 42% power only with 52% area overhead compared with the minimum-spaced uncoded bus. The bit error rate of the bus can be improved from 10^?5 to 10^?24.     

PERFORMANCE ANALYSIS OF HETEROGENEOUS TRAFFIC ON AN INTEGRATED NETWORK LINK WITH FINITE WAITING ROOM AND ANTICIPATED-RELEASE RESERVATION POLICY

We consider a system where the superposition of two heterogeneous Poisson traffic streams is offered to an integrated network link in synchronous transfer mode, where one stream follows the blocked-and-cleared mode (‘loss’ mode) and the other can wait (finitely) if bandwidth is not available for connection at the time of arrival (‘hold’ mode). We assume that each stream has different bandwidth requirements per call. A reservation scheme, called anticipated-release policy, is introduced where an arrival is accepted into a waiting room only if the amount of time this customer is expected to wait is within acceptable limits. For such a loss/hold system, we provide analytical performance models for exponential service time distributions for both streams as well as for the non-exponential service time distribution case for the traffic stream in ‘hold’ mode. We also present a method on how to model the waiting time distribution of the traffic stream with ‘hold’ mode. From numerical studies, we observe that blocking can be reduced considerably for both services just by introducing a small waiting room for one traffic class compared to ‘loss’ mode for both traffic classes. Furthermore, this holds true for the case when a maximum tolerable time limit is imposed on the waiting. Finally, our results indicate that this loss/hold scenario with limited waiting room appears to be virtually insensitive to the service time distribution of the ‘hold’ mode traffic.     

基于CAN总线的汽车内部网络设计

研究了CAN总线在汽车电控系统中的应用,设计了汽车内部网络拓扑结构,采用高、低速CAN总线连接实时性要求不同的ECU,通过网关完成不同速率CAN网络间的通信,并给出了网关和基本CAN节点的软、硬件实现.与传统汽车ECU间点对点的通信方式相比,采用CAN总线节省了车内布线成本、提高了ECU间信息交互的可靠性.     

Multi-bend bus driven floorplanning

In this paper, the problem of bus-driven floorplanning is addressed. Given a set of blocks and bus specifications (the width of each bus and the blocks that the bus need to go through), we will generate a floorplan solution such that all the buses go through their blocks, with the area of the floorplan and the total area of the buses minimized. The approach proposed is based on a simulated annealing framework. Using the sequence pair representation, we derived and proved some necessary conditions for feasible buses, for which we allow 0-bend, one-bend, or two-bend. A checking will be performed to identify those buses that cannot be placed simultaneously. Finally, a solution will be generated giving the coordinates of the modules and the buses. Comparing with the results of the most updated work on this problem by Xiang et al. [Bus-driven floorplanning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 2003, pp. 66-73], our algorithm can handle buses going through many blocks and the dead space of the floorplan obtained is also reduced. For example, if the buses have to go through more than 10 blocks, the approach in Xiang et al. [Bus-driven floorplanning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 2003, pp. 66-73] is not able to generate any solution while our algorithm can still give solutions of good quality.     

PCI总线设备的开发过程及应用实例

PCI总线是一种标准的计算机总线,它具有即插即用、低功耗、数据传输率高等特点。PCI总线已经逐渐取代ISA和EISA总线的位置。PCI总线涉及的规范比较多,接口说明复杂,开发出高效、稳定的PCI总线设备具有一定难度。基于具体实践总结了PCI总线设备的开发过程,并结合PLX公司的9054接口芯片给出了一个应用实例。     

Adaptive Internet Integration of Field Bus Systems

Field buses are used to network sensors, actuators, and control devices inside automation systems. The Internet integration of field bus systems enables information from these devices to be exchanged across enterprises and businesses. An essential prerequisite to this aim is the interoperability of field bus systems with external systems and applications. Therefore, many efforts are made to establish a common information exchange standard which all field bus systems are supposed to support. However, the longer these efforts are ongoing the less it seems that they will ever yield the expected breakthrough. The present paper introduces an substantially different approach to interoperability. Field bus systems may keep their individual application interfaces and data exchange formats. All the same, external infrastructures do not have to be redesigned to match the specific needs of certain field bus systems. Rather, field bus systems become capable of adapting the information exchange flexibly according to the needs of the outside environment     

A dictionary-based en/decoding scheme for low-power data buses

As bus lengths on multihundred-million transistor systems-on-a-chip (SoC) grow, and as interwire capacitances of sub-0.10 /spl mu/m technologies advance, the resulting high-switching capacitances of buses (and interconnects in general) have a nonnegligible impact on the power consumption of a whole SoC. This trend has been recognized and recently addressed by various research groups. We address this problem by introducing our bus encoding technique, adaptive dictionary-encoding scheme "ADES" that minimizes the power consumption of data buses through a dictionary-based encoding technique. Based on exploration of data properties on buses, our technique saves on average more than 25% of bus energy compared to the nonencoded cases using a large set of real-world applications for both address and data buses. Furthermore, we compare our technique to the best-known data bus encoding techniques to date and we find that it exceeds all of them in terms of energy savings for the same set of applications.     

Waiting time analysis in a single buffer DQDB (802.6) network

The statistics of the request and countdown counters of a user in a network that operates with the DQDB (distributed queue dual bus) media access protocol are investigated. Assuming that a user can have at most one packet waiting for transmission, an expression is obtained for the steady-state generating function of the number of requests queued ahead of an arriving packet. Given this number, the waiting time of the packet can be easily obtained. The results provide an insight on how traffic, generated from the left and the right of a user in the network, affects the waiting time characteristics of packets generated by the user