Hybrid cascode feedforward compensation for nano-scale low-power ultra-area-efficient three-stage amplifiers

A modified frequency compensation technique is proposed for low-power area-efficient three-stage amplifiers driving medium to large capacitive loads. Coined hybrid cascode feedforward compensation (HCFC), the total compensation capacitor is divided and shared between two internal high-speed feedback loops instead of only one loop as is common in prior art. Detailed analysis of this technique shows significant improvement in terms of bandwidth and stability. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30% and 40% respectively, compared to the prevailing schemes.     

Hybrid cascode compensation with feedforward stage for high-speed area-efficient three-stage CMOS amplifiers

Hybrid cascode feedforward compensation (HCFC) is proposed for low-power area-efficient three stage amplifiers driving large capacitive loads. With no overhead in power or area, the total compensation capacitor is divided and shared between two internal high-speed loops instead of solely one loop as is common in prior art. Detailed analysis of HCFC shows significant improvement in terms of stability and bandwidth. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30 and 40 %, respectively, compared to the prevailing schemes.     

A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors

A multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced. The compensation scheme uses the positive phase shift of left-half-plane (LHP) zeroes caused by the feedforward path to cancel the negative phase shift of poles to achieve a good phase margin. A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster. The amplifier bandwidth is not compromised by the absence of the traditional pole-splitting effect of Miller compensation, resulting in a high-gain wideband amplifier. The capacitors of a capacitive amplifier using the proposed techniques can be varied more than a decade without significant settling time degradation. Experimental results for a prototype fabricated in an AMI 0.5-/spl mu/m CMOS process show DC gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is /spl plusmn/1.25 V.     

Transconductance with capacitances feedback compensation for multistage amplifiers

A new performance-boosting frequency compensation technique is presented, named Transconductance with Capacitances Feedback Compensation (TCFC). A transconductance stage and two capacitors introduce negative feedback to a three-stage amplifier, which significantly improves the performance such as gain-bandwidth product, slew rate, stability and sensitivity. An optimized TCFC amplifier has been implemented, and fabricated in a 0.35-/spl mu/m CMOS process. The TCFC amplifier driving a 150-pF load capacitor achieved 2.9-MHz gain-bandwidth product dissipating only 45-/spl mu/W power with a 1.5 V supply, which shows a significant improvement in MHz/spl middot/pF/mA performance.     

Single Miller capacitor frequency compensation technique for low-power multistage amplifiers

Due to the rising demand for low-power portable battery-operated electronic devices, there is an increasing need for low-voltage low-power low-drop-out (LDO) regulators. This provides motivation for research on high-gain wide-bandwidth amplifiers driving large capacitive loads. These amplifiers serve as error amplifiers in low-voltage LDO regulators. Two low-power efficient three-stage amplifier topologies suitable for large capacitive load applications are introduced here: single Miller capacitor compensation (SMC) and single Miller capacitor feedforward compensation (SMFFC). Using a single Miller compensation capacitor in three-stage amplifiers can significantly reduce the total capacitor value, and therefore, the overall area of the amplifiers without influencing their stability. Pole-splitting and feedforward techniques are effectively combined to achieve better small-signal and large-signal performances. The 0.5-/spl mu/m CMOS amplifiers, SMC, and SMFFC driving a 25-k/spl Omega///120-pF load achieve 4.6-MHz and 9-MHz gain-bandwidth product, respectively, each dissipates less than 0.42 mW of power with a /spl plusmn/1-V power supply, and each occupies less than 0.02 mm/sup 2/ of silicon area.     

Linearity improvement of cascode low-noise amplifiers using double DS method with a tuned inductor

We propose a highly linear low-noise amplifier (LNA) using the double derivative superposition method with a tuned inductor. This topology has an auxiliary common gate stage of the cascode amplifier to cancel each third-order intermodulation distortion (IMD3) component and can provide a high third-order input intercept point (IIP3) for the 5.25 GHz frequency band. From the simulation results using the TSMC 0.18 μm RF CMOS process, the IIP3 in the proposed cascode LNAs can be improved by 9 dB, compared with the conventional derivative superposition method. The proposed LNA achieves an IIP3 of + 15 dBm with a gain of 10.5 dB, a noise figure of 2.4 dB, and a power consumption of 6 mA at 1.5 V.     

Third-order nonlinearity vs. load impedance for CMOS low-noise amplifiers

The linearity of two 90 nm CMOS low-noise amplifiers has been measured and analyzed. The analysis is based on Taylor series expansion of simulated I-V characteristics. The two amplifiers are cascode amplifiers with transistors of the same size but with different loads. Even though the center frequencies of the amplifiers are as high as 15 and 20 GHz, respectively, the measured results correlate well with the low-frequency-based estimation of linearity. The analysis shows that for a low load impedance, the dominating source of nonlinearity is transconductance, while for a high load impedance the nonlinearity of the output conductance instead dominates.     

Evaluation of the pole expressions of nano-scale multistage amplifiers based on equivalent output impedance

Several frequency compensation schemes have been proposed to stabilize multistage amplifiers with negative feedback. The performance of these amplifiers can be analyzed by inspecting their input-output transfer function as representation of their frequency response. With many circuit elements affecting the output response, it is relatively difficult to obtain the real transfer function of multistage amplifiers based on only the original small-signal expressions. Instead, certain techniques such as Miller’s theorem are used to approximate important parameters such as DC gain and dominant pole. These methods are not generally helpful for approximating the nondominant poles which have a critical role on the loop stability of nano-scale amplifiers. With this issue in mind, this work proposes a systematic methodology to achieve the pole expressions of multistage amplifiers with frequency compensation. The key in the proposed technique is to model the equivalent impedance of the compensation loop at the output. The effectiveness of the proposed approach has been verified through comparison between the transfer functions obtained from theory and those transfer functions found in the literature.     

Tunable gain equalization using a Mach-Zehnder optical filter in multistage fiber amplifiers

Tunable signal gain equalization is demonstrated in three-stage Er/sup 3+/-doped fiber amplifiers using a waveguide type Mach-Zehnder (MZ) optical fiber. A 29-channel multiplexed system is examined where signal wavelengths are positioned from 1.548 to 1.555 mu m. By adjusting the MZ transmittance with the external control current, tunable gain equalization is achieved at the output of each amplifier.<>     

Design of InP DHBT power amplifiers at millimeter-wave frequencies using interstage matched cascode technique

In this paper, the design of InP DHBT based millimeter-wave(mm-wave) power amplifiers(PAs) using an interstage matched cascode technique is presented. The output power of a traditional cascode is limited by the early saturation of the common-base(CB) device. The interstage matched cascode can be employed to improve the power handling ability through optimizing the input impedance of the CB device. The minimized power mismatch between the CB and the common-emitter(CE) devices results in an improved saturated output power. To demonstrate the technique for power amplifier designs at mm-wave frequencies, a single-branch cascode based PA using single-finger devices and a two-way combined based PA using three-finger devices are fabricated. The single-branch design shows a measured power gain of 9.2 dB and a saturated output power of 12.3 dBm at 67.2 GHz and the two-way combined design shows a power gain of 9.5 dB with a saturated output power of 18.6 dBm at 72.6 GHz.     

S-band erbium-doped fiber amplifiers with a multistage configuration /sub e/sign, characterization, and gain tilt compensation

We report an S-band erbium-doped fiber amplifier (EDFA) with a multistage configuration in terms of its design, gain, and noise characteristics for various pump powers and input signal powers, the temperature dependence of the gain spectra, and gain tilt compensation for changes in input signal power and temperature change. We show that there is a tradeoff between low noise and efficiency in the S-band EDFA and describe the development of an S-band EDFA with a flattened gain of more than 21 dB and a noise figure of less than 6.7 dB. We also show that there is a change in the gain spectra with changes in the pump power and input signal power that is different from that observed in C- and L-band EDFAs, and that our EDFA has a temperature-insensitive wavelength. Furthermore, we develop a gain tilt compensated S-band EDFA that can cope with changes in input signal power and temperature.     

Nonlinear identification and optimal feedforward friction compensation for a motion platform

In this study, we present a method of nonlinear identification and optimal feedforward friction compensation for an industrial single degree of freedom motion platform. The platform has precise reference tracking requirements while suffering from nonlinear dynamic effects, such as friction and backlash in the driveline. To eliminate nonlinear dynamic effects and achieve precise reference tracking, we first identified the nonlinear dynamics of the platform using Higher Order Sinusoidal Input Describing Function (HOSIDF) based system identification. Next, we present optimal feedforward compensation design to improve reference tracking performance. We modeled the friction using the Stribeck model and identified its parameters through a procedure including a special reference signal and the Nelder–Mead algorithm. Our results show that the RMS trajectory tracking error decreased from 0.0431 deg/s to 0.0117 deg/s when the proposed nonlinear identification and friction compensation method is utilized.     

Ultrawideband biasing of MMIC distributed amplifiers using improved active load

An improved technique is presented for biasing FETs in ultrawideband circuits, such as the GaAs MMIC distributed amplifier. The technique uses an improved active load, which has a DC operating characteristic that is controlled by a resistor chain. The improved active load has been applied to a 0.5-13 GHz monolithic distributed active signal combiner. The circuit gives excellent bandwidth, and is insensitive to the DC bias voltages.<>     

Settling time optimisation for two-stage CMOS amplifiers with current-buffer Miller compensation

A new settling-time-oriented design strategy for two-stage operational amplifiers with current-buffer Miller compensation is presented. The proposed approach allows the systematic optimisation of the amplifier time response to be performed avoiding time-consuming trial-and- error design processes. A design example in 0.35 mum CMOS technology is also reported. Circuital and statistical simulations demonstrate the effectiveness of the proposed approach.     

脉冲形状对半导体激光放大器用于啁啾补偿的影响

光脉冲经过增益饱和的行波半导体激光放大器后,由于放大器的自相位调制,使放大脉冲附加上频率啁啾。合适的附加啁啾不但能抵销入射脉冲的初始啁啾,而且还有可能借助简单的群速度延迟线对脉冲进行压缩。本文计算了不同形状的入射脉冲经光放大器放大后的输出脉冲形状及其附加的频率啁啾,分析了它们对光放大器用于啁啾补偿的影响。     

Analysis and compensation of the bitline multiplexer in SRAMcurrent sense amplifiers

Current sensing in SRAMs is very promising to achieve high-speed operation in low-voltage applications. However, so far, a main limitation of the practical use of current sense amplifiers is the finite resistance of the bitline multiplexer (MUX). In this paper, the MUX itself and its influence on two types of current sense amplifiers is analyzed. It is shown that the MUX causes a significant performance degradation. A principle is presented to compensate for the bitline multiplexer by means of a current sense amplifier with improved feedback structure. The proposed solution is implemented in a 512×24 bit SRAM macro in 0.18-μm 1.8-V CMOS. It is shown by theory and measurements that, using the proposed circuit, it is possible to fully compensate for the MUX in terms of speed and signal amplitude with only little layout area penalty. A speed improvement due to the compensation of typically 0.5 ns is measured     

Analytical modeling methodology for ultrawideband low noise amplifiers with generalized filter-based impedance matching

In this paper, we present a modeling methodology for fully integrated inductively degenerated cascode ultrawideband low noise amplifiers (LNA) with generalized filter-based impedance matching networks. Our accurate analytical models capture the impact of device and passive component parasitics and transistor short channel effects to generate accurate designs. Utilizing our methodology, we are able to accurately generate an ultrawideband LNA in the 3.1–10.6 GHz frequency band using third and fifth order Chebyshev filters as input impedance matching networks. The speed and accuracy of the proposed analytical model will facilitate rapid design space exploration for ultrawideband LNAs.     

240-km CWDM transmission using cascaded SOA Raman hybrid amplifiers with 70-nm bandwidth

We demonstrate the cascading of broad-band semiconductor optical amplifier-Raman hybrid amplifiers which provide nearly flat gain over 70 nm. A coarse-wavelength-division-multiplexing transmission system consisting of three spans of 80 km shows uniform performance and <1-dB power penalty.     

Prediction of IMD in LDMOS transistor amplifiers using a new large-signal model

In this paper, the intermodulation distortion (IMD) behavior of LDMOS transistors is treated. First, an analysis is performed to explain measured IMD characteristics in different classes of operation. It is shown that the turn-on region plays an important role in explaining measured IMD behavior, which may also give a clue to the excellent linearity of LDMOS transistors. Thereafter, with this knowledge, a new empirical large-signal model with improved capability of predicting IMD in LDMOS amplifiers is presented. The model is verified against various measurements at low as well as high frequency in a class-AB power amplifier circuit.