I/SUP 2/L current gain design

A DC model useful for I/SUP 2/L upward current gain (/spl beta//SUB /spl mu//) design is described. An expression for /spl beta//SUB /spl mu// is obtained in terms of model parameters which are related to device morphology. Design parameters are identified for a standard bipolar technology and a minimum geometry cell.     

A verification of the physical reason for the current gain fall-off at high current levels

In this paper, starting from the theory of the base widening effect, it is demonstrated by a simple calculation that the critical current density of a collector followsT ^−1.3 law. And it is confirmed by experiment. We obtain from the temperature characteristics of the transistors. That the physical reason for the current gain fall-off at high current levels is the base widening effect.     

一种快速测量晶体管共射极直流放大倍数(HFE)的方法

晶体管是一种常用的半导体分立器件,共射极直流放大倍数(HFE)是其重要的一个参数,定义为指定集电极和发射极之间的电压(Uce)下、指定集电极电流(Ic)时和基极电流(Ib)的比值.晶体管是电流控制型器件,为达到指定Ic,在测量时通常采用扫描法:逐步增加Ib,测量Ic的值,当到达指定值时停止扫描,计算比值.这种方法效率很低,本文介绍了一种快速测试的方法,借助ATE上参数测量单元(PMU)的加流功能,一次就可以快速测量出放大倍数.     

A precise large current ratio integrated gain cell

A monolithic circuit technique is presented whereby large current ratios (≈100) are precisely obtained using only small ratios (<10) of resistances and bias currents. The same circuit functions as an analog multiplier/divider, and also generates useful square-law and square-root characteristics. In general, functions of the form z^y, where y > 0 and z > 0, can be realized.     

A code design criteria for not fully connected channel

There are parallel channels which are not fully connected in practice, such as Frequency Division Multiplex （FDM or Orthogonal FDM） systems. Conventional space-time codes can be used for such parallel channels but not the optimal. Based on the derivation of PEP expression for codes transmitted on parallel block fading channels, criteria of codes design for not fully connected channels are proposed and are compared with Tarokh＇s criteria for fully connected channel. New codes for such channels are provided by systematical and exhaustive search. Simulation results show that these codes offer better performance on parallel FDM channels than other known codes.     

A stability improvement of current gain in silicon planar transistors

Slow instability of current gain or the base current in silicon n-p-n planar transistors under large-current life tests in elevated temperatures is discussed. The instability is caused by the ion migration in the oxide bulk covering the intersection of emitter junction. Some results of experimental approach to make transistors insensitive to such a failure mode is also given.     

A power efficient gain enhancing technique for current mirror operational transconductance amplifiers

In this paper, a power efficient voltage gain enhancing technique is described. This technique is suitable for the amplifiers which use current starving method for gain enhancement (explained in the text). The proposed technique makes use of the current which conventionally goes to ground, through a parallel path. In this paper, the new technique is demonstrated for current mirror type of operational transconductance amplifier (OTA). Simulation results show that gain improves by a factor ~2, while consuming the same power as conventional OTA. The added advantage of this technique is that it does not affect the voltage swing while increasing the gain. Compared to the conventional current starving technique, the proposed technique also improves the noise performance and settling speed of the amplifier. The results are compared with the conventional technique, in terms of gain, settling and noise performance. A comparison of FoM (MHz.pF/mA), with other amplifiers, is given at the end as well.     

A contribution to the current gain temperature dependence of bipolar transistors

In this paper it is demonstrated by a simple calculation that the temperature dependence of current gain may be significantly influenced by both the different freeze-out rates of mobile carriers in emitter and base and the different temperature dependences of mobilities in these two regions. These effects can considerably reduce the decrease of current gain towards low temperatures, caused by the effective bandgap difference between the emitter and base region.     

Complementary CMOS current gain cell

A complementary CMOS gain cell is proposed that provides wideband linear amplification of bidirectional currents. The gain of the circuit is electronically variable and the cell has attractive cascading properties. An experimental circuit achieves a gain range of 1.1 to 11 with less than 1% THD and a gain-bandwidth product of 40 MHz.<>     

一种共面带状线高增益整流天线的设计

为了解决微小型机器人应用过程中能量供应的问题,介绍了一种应用于微小型机器人,由共面带状线组成的阶跃阻抗滤波器整流天线设计方法,这种整流天线具有结构简单、不需要集总元件即可滤波、能够对系统进行电磁场仿真、制作方便等优点。同时,在振子天线后面加上反射器,提高了天线增益。利用ADS2005A的Momentum对整流天线进行了仿真及实验验证,证明了设计的可行性。     

Factors limiting current gain in power transistors

The combined effect of sidewall injection, bandgap narrowing, and Shockley-Hall-Read and Auger recombination in determining emitter efficiency in n-p-n power transistor structures is demonstrated by utilizing a two-dimensional transistor model. The relative importance of each of these effects is calculated as a function of emitter junction depth, emitter surface doping, and injection level. It is shown that in a practical transistor design the reduction in emitter efficiency due to the increased injection of holes into the emitter, resulting from bandgap narrowing caused by heavy doping, is not dominated by the emitter sidewall. Auger recombination is seen to be especially important when bandgap narrowing is present. Enhanced Auger-type recombination is due both to increased minority carrier injection in the emitter as well as current crowding effects. The predictions of the model are compared with results of the measurement of current gain versus current level characteristics on existing devices.     

Cascadable CMOS current gain cell with gain insensitive phase shift

By using a complementary circuit topology, electronically variable gain in combination with a gain insensitive phase shift can be achieved. A cascadable CMOS current gain cell based on this concept is proposed, together with a linearisation technique for this circuit.<>     

A differential built-in current sensor design for high-speed IDDQtesting

A new built-in current sensor design for IDDQ testing is presented in this paper. Our design overcomes performance limitations encountered by previous sensors by using a novel differential architecture which allows early and accurate detection of abnormal quiescent current following the switching transient. This differential design also naturally compensates for inaccuracies due to any build up of leakage currents and subthreshold conduction effects when relatively large circuit partitions are tested. A test circuit utilizing the sensor in a built-in self-test environment has been fabricated. At clock speeds of up to 31.25 MHz the sensor accurately detects all six of the defects that were implanted in the test chip. SPICE3 simulations of the circuit indicate that with careful design, this sensor can accurately detect faults at operational speeds in a variety of situations     

The collapse of current gain in multi-finger heterojunction bipolartransistors: its substrate temperature dependence, instability criteria,and modeling

One undesirable phenomenon observed when AlGaAs/GaAs heterojunction bipolar transistors (HBT's) are operated under high power density is the collapse (of current gain). The collapse manifests itself by a distinct abrupt decrease of collector current in the transistor common-emitter current-voltage (I-V) characteristics. In this investigation, we study the substrate temperature dependence of the collapse. A unified equation is introduced to relate the collapse instability criterion with other thermal instability criteria proposed for silicon bipolar transistors. The effects of the thermal instability on the collapse behavior of 2-finger and 1-finger HBT's are examined. We also present a numerical model to adequately describe the collapse in multi-finger HBT's having arbitrary geometry. The I-V characteristics and regression plots of both ballasted and unballasted HBT's are compared     

Input filter design criteria for current-programmed regulators

The design of input filters for switched-mode regulators is discussed, and it is shown that the filter's effect on the power system depends on the control method used in the regulator's DC-DC converter. Design inequalities are reviewed for duty-ratio programmed converters, and specific expressions are presented for current-programmed converters. Examples of application to practical regulator circuits are given where current-programmed criteria, computer-driven measurement tools, and numerical evaluations of analytic expressions are used to design input filters     

Accurate design method for optimum gain pyramidal horns

The horn synthesis problem is formulated in terms of a fourth degree polynomial. Explicit analytical formulas are subsequently derived for the accurate design of standard gain pyramidal horn antennas. These formulas do not need the application of iterative techniques, unlike existing methods, are simpler to use, and are not restricted to high-gain horn design     

A current mode feed-forward gain control system for a 0.8 V CMOS hearing aid

A current mode feed-forward gain control（CMFGC）technique is presented,which is applied in the front-end system of a hearing aid chip.Compared with conventional automatic gain control（AGC）,CMFGC significantly improves the total harmonic distortion（THD）by digital gain control.To attain the digital gain control codes according to the extremely weak output signal from the microphone,a rectifier and a state controller implemented in current mode are proposed.A prototype chip has been designed based on a 0.13μm standard CMOS process.The measurement results show that the supply voltage can be as low as 0.6 V.And with the 0.8 V supply voltage,the THD is improved and below 0.06%（-64 dB）at the output level of 500 mV_p-p,yet the power consumption is limited to 40μW.In addition,the input referred noise is only 4μV_rmsand the maximum gain is maintained at 33 dB.     

一种适用于0.8VCMOS助听器的电流模前馈增益控制系统

摘要：本文介绍了一种适用于助听器前端系统的电流模前馈增益控制系统。和传统自动增益控制系统相比,电流模前馈增益控制通过数字增益控制码来实现前端系统总谐波失真的显著降低。为了从麦克风微弱的输出信号中得到数字控制码, 本文提出了用电流模实现的整流电路和电流模状态控制电路.该设计基于0.13微米CMOS工艺. 测试表明芯片可工作于0.6V的电源电压.在电源电压为0.8V下, 输出摆幅500mVp-p的信号总谐波失真在0.06% (-64dB)以下, 且功耗控制在40uW以内.另外,系统的等效输入噪声达到4uVrms,最大增益保持在33dB.     

Measurement of transistor high-frequency current gain

An approach commonly used in instruments to test the high-frequency current gain of transistors consists of driving the base with a calibrated current source and measuring the collector current with a very low resistance meter. The major shortcomings of such instruments are their insufficient accuracy and their limited range of quiescent test conditions. However, a thorough analysis of this method demonstrates the possibility of reducing the measurement error, in the most unfavorable case, to less than 4.5 per cent as well as the possibility of extending the test conditions to 10µv, 10µa. These improvements were obtained as a result of the development of such features as a source impedance of 50K Ω at 100 Mc, a collector load of 1 Ω and a very low capacitance socket.     

一种高精度电流检测电路的设计

针对常用电流模式的升压转换器结构,提出了一种高精度电流检测电路。该电路在保证响应速度的前提下,通过增加电路环路增益,降低误差源等方法,提高检测电路的电流检测精度。与其他结构电路相比,有结构简单,响应速度快,电流检测精度高的优点。基于Chartered的0.35μm的3.3V/13.5V CMOS工艺,使用Spectre仿真器,对该电路进行了仿真与验证。结果证明,在输入电压为2.5V～5.5V,电感电流为100mA～500mA,工作频率为1MHz的情况下,能够正常稳定工作,并且电流精度高达93%。