Small geometry depleted base bipolar transistors (BSIT)—VLSI devices?

An essential characteristic of devices which are viable candidates for VLSI circuits is that they must have electrical characteristics which can tolerate process variations. Conventional bipolar junction transistors (BJT) are well known to be limited by punchthrough when vertical basewidths axe decreased; these devices are, however, relatively tolerant of linewidth variations. The depleted base bipolar transistor represents a limiting case when the metallurgical basewidth is allowed to shrink to zero. Such devices, also called bipolar static induction transistors (BSIT), have been proposed as candidates for VLSI logic circuits. This paper describes the basic device physics of depleted base transistors and presents experimental verification of the theoretical modeling. The two essential conclusions that are drawn are that such devices can only achieve performance (in terms of transconductance) comparable to BJT's when an electrical p-type base exists (n-p-n device) and secondly, that BSIT's have characteristics which are extremely sensitive to process variations (linewidths, junction depths, and doping profiles). As a consequence, we conclude that while pure bipolar transistors may play an important role in VLSI circuits, depleted base structures such as the BSlT, are unlikely candidates for such applications.     

A fundamental limitation for bipolar transistor scaling

A microscopic model of minority-carrier diffusion in a heavily doped emitter is proposed. Monte Carlo simulation demonstrates that statistical fluctuation in the base current is one of the fundamental limitations in high-speed applications of scaled bipolar transistors. For the transistor presently investigated, with 5.0-μm² emitter area, 0.1-μm junction depth, 8.5-ps measurement time, and 0.75-V emitter/base bias, the base current deviation is 43%. This sets up the maximum operating frequency for the transistor. More lightly doped emitters (such as for heterojunction bipolar transistors) will relax this limitation, but at a cost of increased contact resistance, especially when poly-emitters are utilized. Increasing the emitter/base bias will also make the base current rate more deterministic, but the other limitations such as power dissipation and contact resistance will become more obvious     

One-dimensional modeling of TRIM

This paper describes the operation of a p-π-p structure with injecting contact in a mode similar to that of an equivalent p-n-p bipolar transistor. Minority carrier injection takes place from an adjacent n-type layer. Such structures occur in Tri-mask (TRIM) integrated circuits, for example. Because of the low doping in the π region, high injection level effects occur virtually at the onset of conduction (current densities > 10 mA/cm²). The π region is then divided into two regions, a low-field region and a high-field region. Overall behavior is similar to that of a normal bipolar transistor, the plasma behaving as an injected base layer, the high-field region behaving as the usual base-collector depletion region (output space). An appropriate closed-form solution is derived that gives physical insight into the operation of the structure. It gives gain (and base transit time) results identical in form to those for transistors at high-level injection. A more complete computer analysis of specific structures gave results consistent with the approximate model. The physical picture of TRIM transistors that results from this model indicates that for both gain and frequency response of these transistors, the collector voltage is an important parameter for a given collector current and width of π region. This study, motivated by TRIM structures, is more generally applicable as a one-dimensional analysis of any high-injection bipolar transistor operating in the active mode.     

Ring oscillator circuit simulation with physical model for GaAs/GaAlAs heterojunction bipolar transistors

Switching performance is simulated for GaAs/GaAlAs heterojunction bipolar transistors (HBT's) by combining a realistic physical device model that involves numerical solutions for carrier transport equations and Poisson's equation with our own circuit simulator that enables direct access to the device model embedded in arbitrary circuits. Based on simulated results for five-stage ring oscillators, discussion is given as to how the switching performance depends on the circuit configuration such as current mode logic (CML) without and with emitter follower, and direct-coupled transistor logic (DCTL), inclusion or exclusion of external base areas, and choice for single-or double-heterojunction transistors.     

On the profile design and optimization of epitaxial Si- andSiGe-base bipolar technology for 77 K applications. I. Transistor DCdesign considerations

The DC design considerations associated with optimizing epitaxial Si- and SiGe-base bipolar transistors for the 77-K environment are examined in detail. Transistors and circuits were fabricated using four different vertical profiles, three with a graded-bandgap SiGe base, and one with a Si base for comparison. All four epitaxial-base profiles yield transistors with DC properties suitable for high-speed logic applications in the 77-K environment. The differences between the low-temperature DC characteristics of Si and SiGe transistors are highlighted both theoretically and experimentally. A performance tradeoff associated with the use of an intrinsic spacer layer to reduce parasitic leakage at low temperatures and the consequent base resistance degradation due to enhanced carrier freeze-out is identified. Evidence that a collector-base heterojunction barrier effect severely degrades the current drive and transconductance of SiGe-base transistors operating at low temperatures is provided     

CMOS analog integrated circuits based on weak inversion operations

A simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications. This model includes only two parameters and is suitable for circuit design. It is verified experimentally for both p- and n-channel test transistors of a Si-gate low-voltage CMOS technology. Various circuit configurations taking advantage of weak inversion operation are described and analyzed: two different current references based on known bipolar circuits, an amplitude detector scheme which is then applied to a quartz oscillator with the result of a very low-power consumption (<0.1 /spl mu/W at 32 kHz), and a low-frequency bandpass amplifier. All these circuits are insensitive to threshold and mobility variations, and compatible with a CMOS technology dedicated to digital low-power circuits.     

Effect of reverse base current on bipolar and BiCMOS circuits

A detailed study on the effect of reverse base current (RBC) on the switching behavior of bipolar BiCMOS circuits utilizing advanced high-performance bipolar transistors is presented. It is shown that as the collector doping N_c is increased to overcome the Kirk effect (base stretching) during the switching transient, the avalanche-generated reverse base current in the collector-base junction may cause problems for bipolar output devices switching out of saturation. A basic bipolar inverter and various BiCMOS driver circuits were simulated based on measured avalanche multiplication factors from advanced bipolar transistors with various collector doping N _c. In the case of the basic bipolar inverter, the reverse base current may prevent the switching device from being shut off completely during the on-to-off transition and a self-sustained state may result which reduces the output voltage swing. For the common-emitter (CE) BiCMOS driver, a similar self-sustained state may also occur with the added adverse effect of excessive leakage in standby. Design and scaling considerations are discussed     

An improved Early voltage model for advanced bipolar transistors

An improved Early voltage model reflecting the effect of bias variation is developed. The bias dependencies of the Early voltage are more prominent as the base width of the bipolar transistor decreases. Thus, using the conventional constant Early voltage model can result in considerable errors in modeling the advanced bipolar transistors which possess very thin base region. Comparisons between the present model and the conventional model at different bias conditions support this assertion. SPICE simulations are performed to demonstrate the impact of this study on the small-signal performance of bipolar-transistor integrated circuits     

112-GHz collector-up Ge/GaAs heterojunction bipolar transistorswith low turn-on voltage

This paper reports small-sized collector-up Ge/Ga/As heterojunction bipolar transistors (HBT's) operating at low power and high frequency. A heavily B-doped Ge base-layer and a newly-developed self-aligned process reduce the base resistance and the parasitic elements. Intrinsic base resistance is 50 Ω/□; this is the lowest value reported for bipolar transistors. With limiting the active emitter area through B ion implantation, these collector-up HBT's with a collector size of 2×5 μm² exhibit a current gain of 60. They exhibit a maximum oscillation frequency f_max of 112 GHz with an associated current gain cutoff frequency f_T of 25 GHz. The large value of f_max, exceeding 100 GHz, is attributed to the extremely low base resistance caused by the heavily B-doped base-layer and the self-aligned process and to the low base-collector capacitance expected from the collector-up structure. The turn-on voltage of these HBT's is approximately 0.7 V smaller than that of AlGaAs/GaAs HBT's. These results show that these HBT's have excellent potential for low-power dissipation circuits     

Maximum operating frequency in Si bipolar master-slave toggleflip-flop circuit

This paper presents a propagation-delay equation which is expressed as the influence of the individual device and circuit parameters on the maximum operating frequency of Si bipolar master-slave toggle flip-flop (MS-TFF) circuit with double feedback emitter followers. This equation shows that optimizing the size of individual transistors can enhance the operating speed. Test results show a 10% increase in operating frequency by adopting this design technique. It is also shown that the time constants R_BC_jC, R_B C_D, T_F, R_LCj_C, and R _CCj_C of the upper-level current switch and T_F of the second feedback emitter follower greatly affect the operating speed of circuits using recently developed Si bipolar transistors. The results predicted by the equation are in good agreement with both the experimental ones and SPICE simulations     

Theory of electrothermal behavior of bipolar transistors: Part I -single-finger devices

A detailed theoretical and numerical analysis of the electrothermal behavior of single-finger bipolar transistors is proposed. Two models of different complexities are introduced to investigate self-heating effects in bipolar junction transistors (BJTs) and heterojunction bipolar transistors (HBTs) biased with a constant base-emitter voltage source or with a constant base current source. In the constant base-emitter voltage case, simple relations are derived for determining the onset of the flyback behavior in the output characteristics which defines the boundary of the safe operating region. The model indicates that the flyback behavior disappears at high V/sub BE/ values, and predicts a thermal hysteresis phenomenon at high currents. It is also shown that at high current levels the electrothermal behavior is dominated by ohmic base pushout. If a constant base current is applied, the model shows that both BJTs and HBTs are unconditionally thermally stable. The transient behavior is also considered, and the temperature evolution is investigated for different bias conditions. The model shows that, if the device is biased in the thermally unstable region, thermal breakdown occurs within a finite time instant in the limit case of a zero ballast resistance. Finally, the reduction in the safe operating area due to avalanche effects and to the temperature dependence of thermal conductivity is discussed, and a simplified model is proposed.     

Two-dimensional carrier flow in a transistor structure under nonisothermal conditions

A two-dimensional mathematical model is developed to predict the internal behavior of power transistors operating under steady-state conditions. This model includes the internal self-heating effects in power transistors and is applicable to predict the transistor behavior under high-current and high-voltage operating conditions. The complete set of partial differential equations governing the bipolar semiconductor device behavior under nonisothermal conditions is solved by numerical techniques without assuming internal junctions and other conventional approximations. Input parameters for this model are the dimension of the device, doping profile, mobility expressions, generation-recombination model, and the boundary conditions for external contacts. Computer results of the analysis of a typical power transistor design are presented for specified operating conditions. The current density, electrostatic potential, carrier charge density, and temperature distribution plots within the transistor structure illustrate the combined effect of the electrothermal interaction, base conductivity modulation, current crowding, base pushout, space charge layer widening, and current spreading phenomena in power transistors.     

Numerical Determination of Possible Multiple DC Solutions of Nonlinear Circuits

This paper proposes an approach to find possible multiple solutions of nonlinear resistive circuits. The approach does not guarantee to find all the solutions; its main features are efficiency, the ability to deal with circuits composed of elements described by the most common models employed in microelectronics, such as DIODEs, bipolar junction transistors, MOSFETs and the capability to simulate medium size circuits composed of, but not limited to, some thousand transistors. The proposed approach is based on the partitioning of the original circuit in subcircuits and on the construction of an oriented dependency graph that defines a suitable ordering in the solution of the subcircuits. The oriented dependency graph can have oriented loops and loops can be "sources" of multiple operating points. These loops can be opened by removing a minimal number of circuit nodes. In general these circuit nodes constitute a very small subset with respect to the nodes of the original circuit and as shown in the paper represent a peculiar aspect to search for multiple solutions of a nonlinear circuit.     

Noninterfering optical method of HBT circuit evaluation

The authors report a novel noninterfering and simple approach for evaluation of circuits implemented with AlGaAs/GaAs heterojunction bipolar transistors (HBTs). This method makes use of radiative recombination in the base region of current-carrying HBTs. The infrared radiation emitted is 'visible' to the closed-circuit TV (CCTV) cameras. Therefore, one can view the operation of the HBT circuit under test at normal biases with a TV monitor. This method can be used to determine logic states of gates, as well as collector current of individual HBTs within integrated circuits.<>     

The low-power-drain microelectronic VHF amplifier

Low-power-drain VHF amplifiers have some unique characteristics when they are miniaturized. And, if the design is special?requiring tight tolerances or intended for limited-quantity production?it is often desirable to make the RF micropower circuits from discrete components. Described in this article are the first-order device requirements and circuit considerations for such VHF amplifiers incorporating bipolar transistors operating at collector currents as low as 25 ?A. Two specific designs are offered, along with information pertinent to their construction.     

Second breakdown of vertical power MOSFET's

It is shown that a phenomenon of second breakdown similar to that in bipolar transistors can occur in vertical power MOSFET's. A model for the phenomenon of second breakdown involving the avalanche multiplication of the channel current, the parasitic bipolar transistor, and base resistance is proposed. After presenting the theory, this model is compared with experiments on four-terminal V-groove test devices in which the substrate can be accessed independently. Good agreement is achieved between calculated and measured boundaries of the safe operating area. The model should be applicable to DMOS devices as well.     

Effects of dislocations in silicon transistors with implanted bases

Silicon bipolar transistors have been made by substituting a shallow boron implantation for the standard base deposition used in the manufacture of integrated circuits. This was followed by a high-temperature oxidation drive-in, and the transistor structure completed with a standard phosphorus deposition and drive-in. The implantations were performed through oxides with thicknesses in the range 0.08–0.17 μm. For the 0.17 μm transistors, the electrical characteristics were comparable with standard diffused transistors, while for the 0.08 μm transistors low gains and high emitter/base and collector/base leakages were obtained. For the latter transistors, etching and TEM studies revealed a dislocation network in the emitter region with a small fraction (10^?3) of the dislocations looping down to intersect the emitter/base and collector/base junctions. The poor electrical characteristics are explained in terms of the looping dislocations, and a mechanism is suggested to describe how the dislocations form.     

Delay of Kirk effect due to collector current spreading inheterojunction bipolar transistors

In this work, we present experimental evidence and develop a simple theory for the delay of base push out (Kirk effect) due to collector current spreading in heterojunction bipolar transistors (HBTs). This effect is very pronounced in small area devices even with short collectors. A correction factor relating the observed emitter current density at which peak cut-off is observed to the classical Kirk effect current limit is derived. This theory has very good agreement with measured data for several different epitaxial structures and has important, implications for the design of both digital and microwave transistors and circuits     

Self consistent bipolar transistor models for computer simulation

Extended Ebers-Moll models of bipolar junction transistors have proven useful in computer-aided design packages for many years. The most recent refinement has been the incorporation of basewidth modulation or Early effect through a single model parameter called the Early voltage. This paper delineates the conditions under which a unique Early voltage can be defined and shows that a necessary condition is the base current must be independent of collector-base voltage. Further, a linearization of the large-signal model around a d.c. operating point leads to a small-signal hybrid-pi model in which the collector-base resistor r_u is necessarily absent. The absence of r_u has many implications in the design of high performance amplifier circuits.     

Surface passivation of lnP/ln0.53Ga0.47As heterojunction bipolar transistors for opto-electronic integration

We report for the first time, a surface passivation technique for InP/In_0.53Ga_0.47As heterojunction bipolar transistors that is suitable for optoelectronic integrated circuits. The combination of buffered hydrofluoric acid with high temperature annealing of the surface causes significant increase of the gain at low input currents. Using this technique, transistors were integrated with photodetectors and other optoelectronic devices and had current gains as high as 400 even at nanoampere base currents.