Defect generation statistics in thin gate oxides

We analyze data-retention experiments for flash memory arrays with thin tunnel oxide (t/sub ox/ = 5 nm). These samples show an additional conduction mechanism besides Fowler-Nordheim tunneling and stress-induced leakage current (SILC). The additional leakage contribution is analyzed with respect to the spatial distribution in the array and the shape of the current-voltage characteristics, and is interpreted as an anomalous SILC due to a two-trap leakage path. From the cycling dependence of the distribution tails related to one- and two-trap leakage, we provide evidence that the defect generation statistics is not Poissonian, but is instead correlated. Possible physical mechanisms responsible for correlated generation are also discussed.     

Statistical profiling of SILC spot in flash memories

A new experimental technique for evaluating the position of the oxide weak spot responsible for the stress-induced leakage current (SILC) in flash memories is presented. The oxide field along the channel is modified by drain biasing, and the gate current is then monitored. The position of the leakage spot can be determined by the shift in the gate current-voltage (I-V) characteristics. Experimental results on flash memory arrays reveal a strong localization of SILC in correspondence of the drain junction, due to the cooperation effects of program/erase (P/E) operations. The technique can be used to optimize the P/E conditions for maximum device reliability.     

Electrically and radiation induced leakage currents in thin oxides

Stress Induced Leakage Current (SILC) has been recognized as a topic of concern in flash memory reliability. It is a veritable failure mechanism, occurring long before oxide breakdown and, hence, limiting oxide lifetime. The physical origin and mechanisms of SILC have not yet been clearly understood and several open points to discussion remain. In this work the electrical characteristics of SILC have been studied and an empirical reliability model for ultra-thin gate oxide has been proposed. Moreover, ionizing radiation effects in leakage current generation have been analyzed and compared to electrical SILC.     

Equivalent cell approach for extraction of the SILC distribution inflash EEPROM cells

A new method for characterizing the distribution of the stress-induced leakage current (SILC) in flash memories is presented. The statistics of the leakage parameters are extracted directly from the time dependence of the threshold voltage distributions obtained in a single gate-stress experiment, without any need for tracking the behavior of the individual cells. The new technique can be used for fast evaluation and reliability projections, as well as providing a tool for statistical investigation on the oxide leakage mechanisms     

Explanation of SILC Probability Density Distributions With Nonuniform Generation of Traps in the Tunnel Oxide of Flash Memory Arrays

In this paper, we develop a detailed physical model to interpret the dependence of the stress induced leakage current (SILC) distributions on the nature and position of the generated defects, and we exploit it to reconsider in detail previously published experimental data on the statistical distribution of the SILC in Flash arrays. We found that a unique symmetrical spatial distribution of traps, which is rapidly decreasing from the Si-SiO₂ interfaces toward the center of the oxide, can explain the oxide-thickness and stress-level dependence of the measured SILC distributions. The generation of cooperating defects with increasing stress time is also analyzed and discussed.     

On the correlation between SILC and hole fluence throughout the oxide

Stress-induced leakage current (SILC) has been recognized as a topic of concern in flash memory reliability. It is a reliable failure mechanism, occurring long before oxide breakdown and, hence, limiting oxide lifetime[1]. The physical origin and mechanisms of SILC have not yet been clearly understood and several points open to discussion remain. In this work the role of oxide hole fluence in producing the SILC is discussed. An universal power law of SILC generation kinetics is proposed versus the hole fluence throughout the oxide. The experimental results are theoretically validated by modeling the measured quantum-yield by the contributions of both anode hole injection and electron valence band injection mechanisms.     

Overerase phenomena: an insight into flash memory reliability

The most important reliability issues related to the erasing operation in flash memories are, still today, caused by single bit failures. In particular, the overerase of tail and fast bits affects the threshold voltage distribution width, causing bit-line leakage that produces read/verify circuitry malfunctions, affects the programming efficiency due to voltage drop, and causes charge-pump circuitry failure. This brief overview explores the most important characteristics of these anomalous bits, their relation with the erratic erase phenomena and their impact on flash memory reliability. Identification techniques, experimental results, and physical models are also discussed.     

Applying the fWLR concept to Stress induced leakage current in non-volatile memory processes

A fast wafer level reliability structure and evaluation method has been developed for stress induced leakage current (SILC) in non-volatile memory processes. The structure is based on parallel floating gate cell arrays. The evaluation method is straightforward, and not time-consuming. The measurement consists of bi-directional FN tunneling stress (to degrade the tunnel oxide and to develop the SILC) and a negative voltage gate stress (to reveal the SILC). An empirical SILC parameter has been defined as the lowest cell V_t in the parallel NVM array. This method has been implemented as part of end-of-line measurements in Philips embedded Flash processes, and has been proven to be very effective and powerful in experimental split analysis, process reliability monitoring/control, and process transfers.     

Analytical percolation model for predicting anomalous charge loss in flash memories

Data retention in flash memories is limited by anomalous charge loss. In this work, this phenomenon is modeled with a percolation concept. An analytical model is constructed that relates the charge-loss distribution of moving bits in flash memories with the geometric distribution of oxide traps. The oxide is characterized by a single parameter, the trap density. Combined with a trap-to-trap direct tunneling model, the physical parameters of the electron traps involved in the leakage mechanism are determined. Flash memory failure rate predictions for different oxide qualities, thicknesses and tunnel-oxide voltages are calculated.     

Reliability of thin ZrO2 gate dielectric layers

In this work we examine the positive bias temperature instability (PBTI) and stress induced leakage current (SILC) reliability of nFET devices with thin (2.5 nm) ZrO₂ gate dielectric layers. nFET devices show anomalous PBTI behavior in the form of a negative threshold voltage (V_t) shift during positive bias stress with little temperature dependence and it is not ‘frozen out’ at lower temperatures, indicating a single non-diffusion based mechanism. Correlations between the PBTI and the stress induced leakage current (SILC) suggest that the PBTI effect originates from trapping into empty defects which are initially detected as SILC and located just below the silicon conduction band. These defects also appear to be linked to the time dependent dielectric breakdown behavior.     

Quick address detection of anomalous memory cells in a flash memorytest structure

A novel scheme for quick address detection of anomalous memory cells having the highest and lowest threshold voltages in a flash memory test structure is described. A test structure with a large memory cell array has been developed to evaluate reliability of flash memory cells before fabrication of a new generation of flash memory devices. In this test structure, each terminal branch of a tree-structured column selector is connected to each bitline of the array. And a simple threshold voltage distribution monitor circuit (VTDM) which we have already proposed is connected to the other end of the bitlines. A proposed Multi-Address Scanning Scheme (MASS) is performed by the tree-structured column selector with monitoring the output of VTDM. The detection time has been reduced to 1.12% in the case of 2048 columns. This novel scheme is suitable for performing reliability tests, such as program/erase endurance test and data retention test     

Modeling of SILC based on electron and hole tunneling. I. Transienteffects

A detailed investigation of the steady-state and transient leakage currents in thin oxides is proposed. The experimental data are compared with numerical results obtained from a model based on an inelastic trap-assisted tunneling process, which includes both electron and hole contributions. In order to accurately reproduce the transient discharge currents, a continuous distribution of oxide traps was adopted. The energies of these levels can be either in correspondence of the conduction or valence band edges of the adjacent silicon/polysilicon layers. Both electrons and holes contribute to the transient stress-induced leakage current (SILC), but the extracted trap densities cannot account for the steady-state SILC. A different mechanism, involving trap levels with energy aligned to the energy gap of the silicon layers is proposed and is developed in the following paper. The model can be applied to any type of device and bias conditions and may be used to correctly recognize the role of electron and hole SILC and the spatial and energy distribution of defect states     

Role of positive trapped charge in stress-induced leakage current for flash EEPROM devices

The transient behavior of hot hole (HH) stress-induced leakage current (SILC) in tunnel oxides is investigated. The dominant SILC mechanism is positive oxide charge-assisted tunneling (PCAT). The transient effect of SILC is attributed to positive oxide charge detrapping and thus the reduction of PCAT current. A correlation between SILC and stress-induced substrate current is observed. Our study shows that both SILC and stress-induced substrate current have power law time-dependence t/sup -n/ with the power factor n about 0.7 and 1, respectively. Numerical analysis for PCAT current incorporating a trapped charge caused Coulombic potential in the tunneling barrier is performed to evaluate the time- and field-dependence of SILC and the substrate current. Based on our model, the evolution of threshold voltage shift with read-disturb time in a flash EEPROM cell is derived. Finally, the dependence of SILC on oxide thickness is explored. As oxide thickness reduces from 100 /spl Aring/ to 53 /spl Aring/, the dominant SILC mechanism is found to change from PCAT to neutral trap-assisted tunneling (TAT).     

Detailed observation of small leak current in flash memories withthin tunnel oxides

This paper describes a method for measuring the small current through the oxides on the order of 10^-20 A or less using a floating gate MOSFET and the application results on flash memories with thin tunnel oxides. The method is based on an accurate measurement of the threshold voltage of a floating gate MOSFET with no charge in the floating gate. We applied this method to flash memories to investigate the leak current behavior through thin tunnel oxides with very small areas (<0.16 μm²), and found some anomalous phenomena which cannot be observed from SILC measurements if we use large capacitors. We also discuss possible mechanisms to explain the phenomena     

Impact of time dependent dielectric breakdown and stress-inducedleakage current on the reliability of high dielectric constant(Ba,Sr)TiO3 thin-film capacitors for Gbit-scale DRAMs

Time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) are investigated for the reliability of (Ba,Sr)TiO₃ (BST) thin films. Both time to breakdown (T_BD) versus electric field (E) and T_BD versus 1/E plots show universal straight lines, independent of the film thickness, and predict lifetimes longer than 10 y at +1 V for 50 nm BST films with an SiO₂ equivalent thickness of 0.70 nm. SILC is observed at +1 V after electrical stress of BST films; nevertheless, 10 y reliable operation for Gbit-scale DRAMs is predicted in spite of charge loss by SILC. Lower (Ba+Sr)/Ti ratio is found to be strongly beneficial for low leakage, low SILC, long TBD, and therefore greater long-term reliability. This suggests a worthwhile tradeoff against the dielectric constant, which peaks at a (Ba+Sr)/Ti ratio of 1.05     

Read-disturb and endurance of SSI-flash E2PROM devicesat high operating temperatures

The high-temperature (T) reliability behavior of merged-transistor source side injection (SSI) flash nonvolatile memory (NVM) devices is evaluated in terms of endurance and disturb effects related to stress induced leakage current (SILC) and correlated with the high-T behavior (generation, anneal) of oxide traps. As compared to room-T, program/erase (P/E) cycling at 150°C results in an improved endurance due to an enhanced charge emission. The impact of the operating temperature on SILC-related disturb effects, on the other hand, depends on two combined effects in memory cells where large local charge trap-up influences the threshold voltage, V_t: 1) the T-enhanced trap generation and 2) the T-enhanced emission of trapped charge which influences the disturb field. In the case of the HIMOS-cell-which is discussed here-long-term nonvolatility can still be guaranteed at 150°C. Finally, bake tests at higher temperatures (250-300°C) have been performed in order to evaluate the persistence of the generated damage. It is found that bulk oxide traps are not cured by the bake and, therefore, no long-term relief of SILC-related disturb effects is expected at 150°C     

Measurement of ultralow gate tunneling currents using floating-gate integrator technique

We report for the first time that a gate tunneling current measurement sensitivity better than 3/spl times/10/sup -22/ A has been achieved by using a floating-gate integrator technique. The technique involves monitoring the charge change in the floating-gate integrated with an on-chip op-amp and an on-chip feedback capacitor. We used this technique to study the stress-induced leakage current (SILC) and its cycling dependence of 70 /spl Aring/ oxides in the direct tunneling region at oxide voltage as low as 1.9 V. The technique has been validated through correlation to direct measurement on MOSFET arrays and theoretical calculations. The measured SILC current is modeled with an Inelastic trap-assisted tunneling model.     

低电场应力下闪速存储器的退化特性

基于负栅源边擦除的闪速存储器存储单元,研究了形成应力诱生漏电流的三种导电机制,同时采用新的实验方法对引起瞬态和稳态电流的电压漂移量进行了测量.并利用电容耦合效应模型对闪速存储器存储单元的可靠性进行了研究,结果表明,在低电场应力下,其可靠性问题主要由载流子在氧化层里充放电引起.     

Study of stress-induced leakage current (SILC) in HfO2/Dy2O3 high-κ gate stacks on germanium

In the present work we study reliability issues of Pt/HfO₂/Dy₂O₃/n-Ge MOS structures under various stress conditions. The electrical characteristics of the micro-capacitors are very good probably due to the presence of a rare earth oxide as interfacial layer. It is shown that the injected charge (Q_inj) at high constant voltage stress (CVS) conditions induces stress-induced leakage current (SILC) that obeys a power-law. We also observe a correlation between the trapped oxide charge and SILC, which is, at low stress field, charge build-up and no SILC, while at high stress field SILC but few trapped charges. Results show that the present bilayer oxides combination can lead to Ge based MOS devices that show acceptable degradation of electrical properties of MOS structures and improved reliability characteristics.     

The SILC study by PDO method

Stress induced leakage current (SILC) has been discussed for a long time by many researchers. The oxide traps are believed to be the cause of SILC, but characterization of these traps is still not clear. In this paper, we demonstrate that the SILC related oxide traps can be distinguished into two kinds with different characterization parameter by PDO method. Linear fitting also shows that double oxide trap model is better than single oxide trap model.