Process development of a novel wafer level packaging with TSV applied in high-frequency range transmission

The process development of a novel wafer level packaging with TSV applied in high-frequency range transmission is presented. A specially designed TSV structure (a core TSV and six shielding TSVs) is adopted to connect the components on different sides of the high-resistivity silicon wafer. And the microstrip line in the microwave monolithic integrated circuit is used to transmit high-frequency signal in packaging structure together with the low permittivity intermediate dielectric polymer, benzocyclobutene. The TSV fabrication process and the multi-layer interconnection is illustrated in details. The electrical measurement result of the microstrip lines connected by TSVs reveals the resistances within 0.719 Ω, a return loss better than 23.8 dB and an insertion loss better than 2.60 dB from 14 to 40 GHz.     

A low-cost through via interconnection for ISM WLP

Wafer level packaging (WLP) for image sensor device has the advantage of small size, high performance and low cost. In WLP technology, in order to form electrical interconnection from image sensor contact pad to the backside of the wafer, several structures have been developed, such as T-contact and through silicon via (TSV). In this paper, a wafer level package of image sensor with new type TSV electrical interconnection for image sensor pad is presented. The target of this development is to reduce process cost and difficulty, and increase yield of image sensor packaging. Key fabrication processes includes glass protecting wafer bonding, device wafer thinning, backside through via etching, via passivation layer deposition, pad oxide opening, via filling and backside re-routing layer formation, etc. Compared to large opening area of tapered via on the backside of CMOS image sensor wafer, only small opening area is need for making via interconnection with vertical sidewall presented in this paper. A fillet structure at bottom corner of via holes can help to reduce sequent process difficulty, so that low-cost and simplified unit processes are successfully adopted in the fabrication process for through via formation. The through via interconnection shows good electrical connection performance, and high-quality photo images are obtained by packaged image sensor device.     

MEMS packaging process by film transfer using an anti-adhesive layer

A low cost and low temperature thin film packaging process based on the transfer of an electroplated Nickel 3D cap is proposed. This process is based on adhesion control of a thick molded cap Ni film on the carrier wafer by using a plasma deposited fluorocarbon film, on mechanical debonding and on adhesive bonding of the microcaps on the host wafer with BCB sealing rings. Mechanical characterizations show that the transferred microcaps have a high stiffness, a low stress and a high adhesion. Because this process is simple and only involves a low temperature (250°C) heating of the host wafer, it is highly versatile and suitable for the encapsulation of micro and nano devices, circuits and systems elaborated on a large range of substrate materials.     

Packaging of a 3-axial piezoresistive force sensor with backside contacts

In this paper design aspects and challenging packaging solution of a monolithic 3D force sensor will be presented. The previously developed design and process flow (Vázsonyi et al. 123–124:620–626, 2005; Molnár et al. 90:40–43, 2012) were improved by an additional hybrid wafer bonding step of simultaneous anodic and metal bonding processes. This electrostatic force assisted metal bonding can ensure both the mechanical and the electrical integrity of the device. The applied novel process sequence can eliminate the need of a possible flip-chip bonding and chemical–mechanical polishing steps. The applied glass substrate improves the thermal isolation and thermo-mechanical stability of the integrated system considering the thermal expansion coefficients of the chosen glass material and the silicon (Si) only slightly differ minimizing the residual thermo-mechanical stress during the operation.     

Wafer level packaging compatible with millimeter-wave antenna

This paper presents a technological process compatible process compatible with an above integrated circuit (IC) to achieve a millimeter wave antenna structure that is well-suited for wafer level packaging technology. The radiating patch is introduced inside of the air cavity of packaging. This structure consists of two dielectric substrates and benzocyclobutene (BCB) sealing rings at the wafer level. The wafer level packaging that holds the radiating patch is made of Pyrex, a low permittivity substrate. The millimeter-wave antenna using the micromachining technology is excited by a coplanar waveguide fed aperture (CPWFA). This feeding mechanism is designed and realized on GaAs, a high permittivity substrate. The electromagnetic energy of the CPWFA to the radiating patch is made through a coupling slot. The fabricated antenna of 6 mm × 6 mm, including the ground plane, exhibits a 10 dB bandwidth of 3 GHz from 50.5 GHz to 53.5 GHz. The design has been driven by the interest of collective encapsulation of MEMS and MMICs devices.     

硅通孔键合硅片预对准边缘信息采集与处理

研究硅通孔即TSV(through-silicon vias)键合硅片的预对准边缘信息采集与处理方法。TSV硅片与标准硅片相比,有减薄、键合不同心、边缘毛刺多、存在崩边;缺口被填充、内有鼓胶、镀铜等工艺特点,使得传统基于线阵CCD一维图像采集与处理预对准方法失败。针对TSV硅片的特点,把线阵CCD配合扫描运动采集的一维原始图像集拼接获得二维图像,应用二维图像处理技术提取边缘信息,硅片整周边缘数据用最小二乘圆拟合算法识别出圆心位置,缺口边缘数据用Hough直线变换识别出缺口两条斜边,其交点定位为缺口位置,从而实现TSV硅片的自动预对准。实际测量表明,该方法预对准重复性定位精度<20um、预对准时间<40s,满足指标需求,为光刻机能够曝光TSV硅片提供有力支持。     

3D System-on-Chip technologies for More than Moore systems

3D integration is a key solution to the predicted performance problems of future ICs as well as it offers extreme miniaturization and cost-effective fabrication of More than Moore products. Through silicon via (TSV) technologies enable high interconnect performance compared to 3D packaging. At present TSVs are associated with a relatively high fabrication cost, but research world wide strive to bring the cost down to an acceptable level. An example of a 3D System-on-Chip (3D-SOC) technology is to introduce a post backend-of-line TSV process as an optimized technology for heterogeneous system integration. The introduced ICV-SLID process, that combines both TSVs and bonding, enables 3D integration of fabricated devices. Reliability issues related to thermo-mechanical stress caused by the TSV formation and the bonding are considered. 3D-SOC technology choices made to realize a heterogeneous ultra-small IC stack for a wireless tire pressure monitoring system (TPMS) as an automotive application are described.     

The implementation and performance evaluation of a silicon-based LED packaging module with lens configuration

This study develops a transfer molding with flexible master for a silicon-based light emitting diode packaging with an aspherical lens and a microlens array using microelectromechanical systems technology. By transferring the pattern from wafer to wafer, the precise alignment of the lens configuration and the reflector of the silicon substrate can be achieved; batch processing can be used to reduce the costs. The size of the packaging element can be further reduced to allow more applications. For evaluating the packaging performance, the transfer of the pattern of various lens profiles is accomplished successfully using silicone gel and electroplating nickel as the lens molds, and experiments to determine the mechanical reliability are conducted. The experimental results show that the lens profiles of the silicone gel and nickel masters are exactly transferred onto the surfaces of epoxy and silicone gel encapsulations, respectively, without any damage to the material surface. The brightness of the packaging elements with a single aspherical lens profile and high fill factor microlens array are increased by 26 and 16 %, respectively, as compared with optical encapsulation with a smooth curved surface. The light uniformity is greatly improved for a 100 % fill factor microlens array. The proposed packaging solution satisfies the requirements of pattern transfer in a wafer level and improves lighting performance.     

BCB contact printing for patterned adhesive full-wafer bonded 0-level packages

Adhesive wafer bonding with a patterned polymer layer is increasingly attracting attention as cheap and simple 0-level packaging technology for microstructures, because the patterned polymer both fulfills the bonding function and determines the volumes between the two wafers housing the devices to be packaged. To be able to pattern a polymer, it has to be cross-linked to a certain degree which makes the material rigid and less adhesive for the bonding afterward. In this paper, a simple method is presented which combines the advantages of a patterned adhesive layer with the advantages of a liquid polymer phase before the bonding. The pattern in the adhesive layer is "inked" with viscous polymer by pressing the substrate toward an auxiliary wafer with a thin liquid polymer layer. Then, the substrate with the inked pattern is finally bonded to the top wafer. Benzocyclobuene (BCB) was used both for the patterned structures and as the "ink". Tensile bond strength tests were carried out on patterned adhesive bonded samples fabricated with and without this contact printing method. The bonding yield is significantly improved with the contact printing method, the fabrication procedure is more robust and the test results show that the bond strength is at least 2 times higher. An investigation of the samples' failure mechanisms revealed that the bond strength even exceeds the adhesion forces of the BCB to the substrate. Furthermore, the BCB contact printing method was successfully applied for 0-level glass-lid packaging done by full-wafer bonding with a patterned adhesive layer. Here, the encapsulating lids are separated after the bonding by dicing the top wafer independently of the bottom wafer.     

Fabrication of an hermetically packaged silicon resonator on LTCC substrate

The design, fabrication and packaging process of silicon resonators capable of the integration of LSI (Large Scale Integration) have been developed on the basis of packaging technology using an LTCC (Low Temperature Co-fired Ceramic) substrate. The structures of silicon resonators are defined by deep reactive ion etching (DRIE) on a silicon on insulator (SOI) wafer and then transferred onto the LTCC substrate and hermetically sealed by anodic bonding technique. The measured resonant frequency of a micromechanical bulk acoustic mode silicon resonator after packaging at 0.02 Pa is 20.24 MHz with a quality factor of 50,600.     

考虑硅衬底效应的基于TSV的3D IC电源分配网络建模

基于硅通孔TSV的3D-IC在电源分配网络PDN中引入了新的结构--TSV，另外，3D堆叠使得硅衬底效应成为不可忽略的因素，因此为3D-IC建立PDN模型必须要考虑TSV以及硅衬底效应。为基于TSV的3D-IC建立了一个考虑硅衬底效应的3D PDN模型，该模型由P/G TSV对模型和片上PDN模型组成。P/G TSV对模型是在已有模型基础上，引入bump和接触孔的RLGC集总模型而建立的，该模型可以更好地体现P/G TSV对的电学特性；片上PDN模型则是基于Pak J S提出的模型，通过共形映射法将硅衬底效应引入单元模块模型而建立的，该模型可以有效地反映硅衬底对PDN电学特性的影响。经实验表明，建立的3D PDN模型可以有效、快速地估算3D-IC PDN阻抗。     

Direct bonding with on-wafer metal interconnections

A low temperature direct bonding process with encapsulated metal interconnections was proposed. The process can be realized between silicon wafers or silicon and glass wafers. To establish well-insulated electric connection, sputtered aluminum film was patterned between a bottom thermal SiO₂ and a top PE-SiO₂; the consequential uneven wafer surface was planarized through a chemical mechanical polishing (CMP) step. Benefit from this smooth surface finish, direct bonding is achieved at room temperature, and a general yielding rate of more than 95% is obtained. Test results confirmed the reliability of the bonding. The main advantages of this new technology are its electric connectivity, low thermal stress and hermeticity. This process can be utilized for the packaging of micro electro mechanical system (MEMS) devices or the production of SOI wafers with pre-fabricated electrodes and wires.     

InP dies transferred onto silicon substrate for optical interconnects application

We bonded quantum well InP dies on a photonic layer transferred on silicon CMOS processed wafer using direct molecular bonding. This approach is suitable for new applications, viz., photonics on silicon, 3D packaging and integrated sensors. The chips are diced from a bulk substrate and bonded directly onto a silicon substrate without any organic nor metallic adhesive layer. A thin silicon dioxide layer can be added on both assembled surfaces to enhance bonding quality. After bonding, the dies can mechanically be thinned down to 20 μm and chemically etched. The InAsP quantum well stack of the InP dies keeps its optoelectronics features and performances after being transferred onto a silicon substrate.     

Microrivets for MEMS packaging: concept, fabrication, and strengthtesting

Microriveting is introduced as a novel and alternative joining technique to package MEMS devices. In contrast to the existing methods, mostly surface bonding, the reported technique joins two wafer pieces together by riveting, a mechanical joining means. Advantages include wafer joining at room temperature and low voltage, and relaxed requirements for surface preparation. The microrivets, which hold a cap-base wafer pair together, are formed by filling rivet holes through electroplating. The cap wafer has a recess to house the MEMS devices and also has through-holes to serve as rivet molds. The seed layer on the base wafer becomes the base of the rivet. The process requires only simple mechanical clamping of the wafer pair during riveting, compared with the more involved procedures needed for wafer bonding. Directionality of electroplating in an electric field is what makes this process simple and robust. Strength testing is carried out to evaluate the joining with microrivets. Different modes of rivet failure under different loading conditions are identified and investigated. Effective strength between 7 and 11 MPa was measured under normal loading with nickel microrivets. Joining strengths comparable to conventional wafer bonding processes, ease of fabrication with repeatability, and compatibility with batch fabrication show that microriveting is a feasible technique to join wafers for MEMS packaging, especially when hermetic sealing is not essential     

Through-silicon via technologies for interconnects in RF MEMS

In this paper, we describe the application of through-silicon via (TSV) interconnects in Radio Frequency Micro-electro-mechanical systems (RF MEMS). Using TSV technologies as grounding connections, a Ku band miniature bandpass filter is designed and fabricated. Measured results show an insertion loss of 1.9 dB and a bandwidth of 20%. The chip size is 9.6 × 4 × 0.4 mm³. Using TSV as interconnections for 3 dimensional millimeter-wave integrated circuits, a silicon micromachined vertical transition with three layers is presented. TSV, alignment, bonding and wafer thinning technologies are used to fabricate the sample. This transition has an insertion loss of less than 6.7 dB from 26 to 34 GHz and its amplitude variation is less than 2 dB. The total size of the chip is 6.3 × 3.2 mm².     

三维芯片中TSV链式冗余修复电路的设计与实现

由于具有高集成度、高性能及低功耗等优点,三维芯片结构逐渐成为超大规模集成电路技术中的热门研究方向之一。TSV是三维芯片进行垂直互连的关键技术,然而在TSV的制作或晶圆的减薄和绑定过程中都可能产生TSV故障,这将导致与TSV互联的模块失效,甚至整个三维芯片失效。提出了一种基于TSV链式结构的单冗余/双冗余修复电路,利用芯片测试后产生的信号来控制该修复电路,将通过故障TSV的信号转移到相邻无故障的TSV中进行传输,以达到修复失效TSV的目的。实验结果表明,该电路结构功能正确,在面积开销较低的情况下,三维芯片的整体修复率可达91.97%以上。     

Evaluation of Si liquid cooling structure with microchannel and TSV for 3D application

The development of 3D integration has caused a major technology paradigm shift to all integrated circuit (IC) devices, interconnects, and packages. Despite the benefits of 3D integration, this process faces the key challenge of thermal management, especially for high power and high density IC devices. Due to the limitations of conventional thermal solutions, liquid cooling technology has become a field of great interest for IC thermal management. In this study, an on-chip liquid cooling module with three different through Si vias (TSVs) and a fixed microchannel structure has been fabricated on an Si wafer using deep reactive ion etching and anodic bonding, followed by a grinding and dicing process. Pressure drop, coolant flow, and temperature difference before and after liquid flow were experimentally measured. TSV depth and diameter have been shown to have little effect on the change of pressure drop; however, shallower TSV depth and larger TSV diameter led to improved liquid cooling performance. The trapezoidal TSV showed slightly more effective cooling than did the scalloped TSV or the straight TSV.

     

Development of Wafer Warehouse Management System for Semiconductor Manufacturing Foundry Supply Chain

Efficiency of supply chains management mostly depends on the process coordination and information integration between the supply chain companies.The well-known integrated circuit design houses,the wafer fabrication industries, and the integrated circuit packaging/testing business has together formed a contiguous supply chain from materials to system in Taiwan during the past decades.Logistic management of the wafer hence becomes the key linkage in the semiconductor foundry supply chain.The objective of this paper is to develop the wafer warehouse management system for global wafer logistics.Current operations for wafer logistics management are firstly reviewed. The system requirements are analyzed by the model-driven business transformation approach.The business operation model and the platform-independent solution architecture for the wafer logistics management are constructed.A prototype information system is also developed for validation.Results of this research can improve the effectiveness and efficiency in wafer logistics management for the semiconductor foundry supply chain.     

Temperature characterization of flip-chip packaged piezoresistive barometric pressure sensors

In order to miniaturize piezoresistive barometric pressure sensors, a new flip-chip packaging technology has been developed. The thermal expansions of chip and package are different. So in a standard flip-chip package the strong mechanical coupling by the solder bumps would lead to stress in the sensor chip, which is unacceptable for piezoresistive pressure sensors. To solve this problem, in the new packaging technology the chip is flip-chip bonded on compliant springs to decouple chip and package. As the first step of the packaging process an under bump metallization (UBM) is patterned on the sensor wafer. Then solder bumps are printed. After wafer-dicing the chips are flip-chip bonded on copper springs within a ceramic cavity housing. Due to the compliance of the springs, packaging stress is induced into the sensor chip. As sources of residual stress the UBM and the solder bumps on the sensor chip were identified. Different coefficients of thermal expansion of the silicon chip, the UBM and the solder lead to plastic straining of the aluminum metallization between UBM and chip. As a consequence the measurement accuracy is limited by a temperature hysteresis. The influence of the chip geometry, e.g., the thickness of the chip or the depth of the cavity, on the hysteresis was investigated by simulation and measurements. As a result of this investigation a sensor chip was designed with very low residual stress and a temperature hysteresis which is only slightly larger than the noise of the sensor.     

A silicon test chip for the thermomechanical analysis of MEMS packagings

This paper reports on a method for the investigation of mechanical stress on MEMS sensor and actuator structures due to packaging processes. A silicon test chip is developed and manufactured to validate the simulation results. Finite element analysis (FEA) is used to optimize the geometric parameters and to find a stress sensitive sensor geometry. A diaphragm structure is used as mechanical amplifier for bulk induced stresses during the packaging process. Piezo resistive solid state resistors are doped into the surface of the chip to measure the stress in the diaphragms and at the contact pads being most significant locations for analysis. A high precision ohmmeter was used to measure the resistance prior and past the packaging process. The captured data allows for computation of the resulting stress loads in magnitude. Therefore, a stress evaluation of different packaging technologies is conducted and the impact of the packaging process on reliability can be estimated immediately.