Decoupled optimal design for power electronic circuits with adaptive migration in coevolutionary environment

This paper presents a genetic based decoupled optimal design method for power electronics circuit design using an adaptive collaboration approach in a cooperative coevolutionary environment. The circuit parameters of the power conversion stage and the feedback network of a buck regulator are optimized through two parallel coadaptive genetic based optimization processes. The best candidate of the tunable parameters in one evolutionary process for the design of the power conversion stage is merged to the other evolutionary process for the design of the feedback network as untunable factors through a collaboration controller in which the collaboration strategy is adaptively controlled by a first-order projection of the maximum and minimum bounds of the fitness value of the genes representing the circuit design parameters in each generation. The proposed design methodology is suitable for parallel computation resulting in considerable improvement in searching efficiency. Simulated results of the design of a buck regulator with the proposed approach were verified with experimental results from the actual hardware implementation. It showed that the design with the proposed scheme was compatible with the design specification.     

基于演化算法的电路自动设计方法

在电路设计中引入演化计算,在可编程逻辑器件上通过对基本电路元器件进行演化而自动生成人工不可能设计出的电路结构,称为演化硬件设计。文中介绍了演化硬件实现的物质基础、演化计算在硬件自动设计方法的实现过程以及该方法要解决的问题,并对演化数字电路、模拟电路的设计进行了分析,说明演化算法在电路自动设计中是切实有效的。     

A three-step decomposition method for the evolutionary design of sequential logic circuits

Evolvable hardware (EHW) refers to an automatic circuit design approach, which employs evolutionary algorithms (EAs) to generate the configurations of the programmable devices. The scalability is one of the main obstacles preventing EHW from being applied to real-world applications. Several techniques have been proposed to overcome the scalability problem. One of them is to decompose the whole circuit into several small evolvable sub-circuits. However, current techniques for scalability are mainly used to evolve combinational logic circuits. In this paper, in order to decompose a sequential logic circuit, the state decomposition, output decomposition and input decomposition are united as a three-step decomposition method (3SD). A novel extrinsic EHW system, namely 3SD–ES, which combines the 3SD method with the (μ, λ) ES (evolution strategy), is proposed, and is used for the evolutionary designing of larger sequential logic circuits. The proposed extrinsic EHW system is tested extensively on sequential logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library. The results demonstrate that 3SD–ES has much better performance in terms of scalability. It enables the evolutionary designing of larger sequential circuits than have ever been evolved before.     

Generalized disjunction decomposition for evolvable hardware.

Evolvable hardware (EHW) refers to self-reconfiguration hardware design, where the configuration is under the control of an evolutionary algorithm (EA). One of the main difficulties in using EHW to solve real-world problems is scalability, which limits the size of the circuit that may be evolved. This paper outlines a new type of decomposition strategy for EHW, the "generalized disjunction decomposition" (GDD), which allows the evolution of large circuits. The proposed method has been extensively tested, not only with multipliers and parity bit problems traditionally used in the EHW community, but also with logic circuits taken from the Microelectronics Center of North Carolina (MCNC) benchmark library and randomly generated circuits. In order to achieve statistically relevant results, each analyzed logic circuit has been evolved 100 times, and the average of these results is presented and compared with other EHW techniques. This approach is necessary because of the probabilistic nature of EA; the same logic circuit may not be solved in the same way if tested several times. The proposed method has been examined in an extrinsic EHW system using the (1 + lambda) evolution strategy. The results obtained demonstrate that GDD significantly improves the evolution of logic circuits in terms of the number of generations, reduces computational time as it is able to reduce the required time for a single iteration of the EA, and enables the evolution of larger circuits never before evolved. In addition to the proposed method, a short overview of EHW systems together with the most recent applications in electrical circuit design is provided.     

仿生硬件在线进化技术研究

仿生硬件是一门新兴的研究领域,它提供了一种基于进化的电路设计新方法.目前,国内的研究主要以离线进化为主.介绍了仿生硬件的在线进化,给出了电路进化系统的硬件结构和软件流程.实例证明基于进化算法、JBits API和RC1000板卡实现硬件在线进化是可行的.     

Graph-based evolutionary design of arithmetic circuits

We present an efficient graph-based evolutionary optimization technique, called evolutionary graph generation (EGG), and the proposed approach is applied to the design of combinational and sequential arithmetic circuits based on parallel counter-tree architecture. The fundamental idea of EGG is to employ general circuit graphs as individuals and manipulate the circuit graphs directly using new evolutionary graph operations without encoding the graphs into other indirect representations, such as the bit strings used in genetic algorithm (GA) proposed by Holland (1992) and trees used in genetic programming (GP) proposed by Koza et al. (1997). In this paper, the EGG system is applied to the design of constant-coefficient multipliers and the design of bit-serial data-parallel adders. The results demonstrate the potential capability of EGG to solve the practical design problems for arithmetic circuits with limited knowledge of computer arithmetic algorithms. The proposed EGG system can help to simplify and speed up the process of designing arithmetic circuits and can produce better solutions to the given problem     

基于HOL4的形式化方法

针对计算机系统设计的正确性问题,研究了一种在测试空间上完备的形式化方法,探讨了硬件系统在定理证明器HOL4中进行形式化验证的一般方法,其中包括如何采用高阶逻辑形式化描述系统的实现与规范,以及在HOL4中证明目标的一般过程.同时,以乘法器为实例,提出一种功能分解法对需要分析的电路进行形式化建模,并对模型的性质在HOL4中进行推理与验证,从而证明了乘法器电路设计的模型满足所提取的性质.     

基于演化算法的全加器优化设计

演化硬件研究工作中的一个重要研究内容就是电路优化设计,电路优化设计有望实现复杂电路的自动设计并获得新颖、优化的设计结果,因而成为国际性的研究热点。将演化算法引入全加器电路的优化设计中,引入了新的个体评估机制并提出了适用于全加器演化的演化算法。通过仿真实验验证了算法的有效性。     

基于修复技术的组合电路进化设计算法研究

提出基于修复技术的组合逻辑电路快速进化设计算法。该算法利用候选电路在进化的初始阶段适应度增加很快的现象,先进化出一个功能大致正确的电路;然后转入修复过程并对不正确的输出进行修正,最终设计出功能正确的电路。为了能对进化出的有错误的电路进行修复,专门设计出简单而规整的修复电路的构造方法。附加的修复电路与进化生成的对大部分输入都能输出正确结果的电路结合在一起,形成最终的功能完全正确的电路。该方法极大地减少进化所需的时间。     

基于DSP的车型检测器设计及其算法的研究

车型分类是高速公路自动收费和交通流量统计的重要依据,它是智能交通(ITS)的一个重要组成部分。本文针对车型检测器硬件结构和处理算法两方面提出一些具有创新性的设计方案,介绍了由LC振荡电路和TMS320F2812处理芯片构成的车型检测器的硬件结构,为克服LC振荡电路频率不稳定的固有缺陷提出了基频更新算法。并提出了利用一维数学形态滤波方法过滤实际应用中的噪声信号的方法,最后简单介绍了基于粗糙集BP神经网络车型分类算法。     

TPC码译码器硬件仿真的优化设计

介绍一种TPC码迭代译码器的硬件设计方案,基于软判决译码规则,采用完全并行规整的译码结构,使用VHDL硬件描述语言,实现了码率为1/2的(8,4)二维乘积码迭代译码器,并特别通过硬件测试激励来实时测量所设计迭代译码器的误码率情况,提出了优化设计方案,和传统的硬件仿真方法相比大大提高了仿真效率。仿真结果证明该译码器有很大的实用性和灵活性。     

CMOS analogue amplifier circuits optimisation using hybrid backtracking search algorithm with differential evolution

This paper proposes a novel hybrid optimisation algorithm which combines the recently proposed evolutionary algorithm Backtracking Search Algorithm (BSA) with another widely accepted evolutionary algorithm, namely, Differential Evolution (DE). The proposed algorithm called BSA-DE is employed for the optimal designs of two commonly used analogue circuits, namely Complementary Metal Oxide Semiconductor (CMOS) differential amplifier circuit with current mirror load and CMOS two-stage operational amplifier (op-amp) circuit. BSA has a simple structure that is effective, fast and capable of solving multimodal problems. DE is a stochastic, population-based heuristic approach, having the capability to solve global optimisation problems. In this paper, the transistors’ sizes are optimised using the proposed BSA-DE to minimise the areas occupied by the circuits and to improve the performances of the circuits. The simulation results justify the superiority of BSA-DE in global convergence properties and fine tuning ability, and prove it to be a promising candidate for the optimal design of the analogue CMOS amplifier circuits. The simulation results obtained for both the amplifier circuits prove the effectiveness of the proposed BSA-DE-based approach over DE, harmony search (HS), artificial bee colony (ABC) and PSO in terms of convergence speed, design specifications and design parameters of the optimal design of the analogue CMOS amplifier circuits. It is shown that BSA-DE-based design technique for each amplifier circuit yields the least MOS transistor area, and each designed circuit is shown to have the best performance parameters such as gain, power dissipation, etc., as compared with those of other recently reported literature.     

基于精英池演化算法的数字电路在片演化方法

20世纪末演化硬件技术的提出为实现硬件系统的自适应与智能化等特征提供了一种可行的新技术,现阶段电路进化是演化硬件研究的热点之一.该文引入人工经验与规则,提出一种扩展矩阵编码法,保护具有较优结构的电路个体不易被淘汰;其次,基于多目标和局部寻优技术,结合子电路杂交与单元重要性的自适应变异策略,提出了一种设计数字电路的精英池演化算法,并在可编程逻辑器件上实现电路的自主动态重构与评价等演化过程.     

演化硬件技术及其应用发展

在硬件电路设计中引入演化计算,在可编程逻辑器件上通过对基本电路元器件进行演化而自动生成人工不可能设计出的电路结构,称为演化硬件设计。本文就演化硬件的原理和其国内外的发展现状进行说明和阐述,并对此技术的具体实现过程做了一个简单的实验。通过实验,说明演化硬件技术确实在电路自动设计方面有着极大的前景。最后介绍了演化硬件技术发展,及其应用到深空探测领域的现实意义。     

采用定点数的数字DC-DC控制器设计

提出了一种应用于数字DC-DC变换器的高精度定点数字控制器的设计方法;在数字控制器的控制率运算中,将浮点数格式的控制参数转化为定点数格式,从而达到简化硬件电路的目的;该设计方法应用于降压型数字DC-DC变换器的设计中,并完成了基于FPGA的测试和验证;在500kHz的开关频率下,输出电压纹波为14mV,对于±0.5A的负载电流跳变,控制器响应时间约为330μs。测试结果表明,该设计方法在保持控制精度的前提下,可简化硬件电路的设计复杂度,并改善系统的瞬态性能。     

Parameter optimization of an on-chip voltage reference circuitusing evolutionary programming

This paper presents an application of evolutionary programming to parameter optimization in the design of a voltage reference circuit. Designing circuits consists of two steps: topological design and parameter determination. After designing a topology suitable for the circuit, the designer selects an appropriate value for each circuit element from a circuit analysis and his experience. This step is difficult and time consuming because the designer must consider many factors simultaneously. As more precise circuits are required, parameter optimization becomes more complex. The voltage reference circuit, which requires a precise reference voltage independent of power fluctuation and temperature change, is such an example. In this paper, evolutionary programming is used as an effective method of finding good parameter values for the elements of the voltage reference circuit. Simulation results show that this method provides good performance and can be used as an effective method for circuit design     

基于调制宽带转换器的低频射电天文信号采集电路设计及实现

针对射电天文信号观测中传统的信号采集电路存储数据需较大的存储空间的问题,提出一种基于调制宽带转换器（MWC）的低频射电天文信号采集的硬件电路设计方法。首先,将观测信号与4路伪随机周期信号相乘后分为4路,并将这4路信号分别进行二阶巴特沃兹低通滤波器滤波;然后,对4路滤波后的信号进行采样,数据传输至现场可编程门阵列（FPGA）中进行存储;最后,用正交匹配追踪（OMP）算法进行信号重构。理论分析和实验测试结果表明,重构信号与观测信号的均方误差为1.27×10^-2,数据存储空间压缩率为20%,该硬件电路设计方法降低了电路设计成本,也释放了存储空间。     

Explorations in design space: unconventional electronics designthrough artificial evolution

Three hypotheses are formulated. First, in the “design space” of possible electronic circuits, conventional design methods work within constrained regions, never considering most of the whole. Second, evolutionary algorithms can explore some of the regions beyond the scope of contentional methods, raising the possibility that better designs can be found. Third, evolutionary algorithms can in practice produce designs that are beyond the scope of conventional methods, and that are in some sense better. A reconfigurable hardware controller for a robot is evolved, using a conventional architecture with and without orthodox design constraints. In the unconstrained case, evolution exploited the enhanced capabilities of the hardware. A tone discriminator circuit is evolved on an FPGA without constraints, resulting in a structure and dynamics that are foreign to conventional design and analysis. The first two hypotheses are true. Evolution can explore the forms and processes that are natural to the electronic medium, and nonbehavioral requirements can be integrated into this design process, such as fault tolerance. A strategy to evolve circuit robustness tailored to the task, the circuit, and the medium, is presented. Hardware and software tools enabling research progress are discussed. The third hypothesis is a good working one: practically useful but radically unconventional evolved circuits are in sight     

基于改进连续时间动态系统的模拟SAT求解器

针对布尔可满足性问题的高效求解进行了研究。首先,通过对k-SAT问题和基于耦合常微分方程形式的确定性连续时间动态系统的分析,提出了一种基于时延信息形式的改进连续时间动态系统方程,以保持集中搜索特性;然后,提出了实现该系统方程的三个主要组件即信号动态电路、辅助变量电路和数字验证电路的模拟设计。在信号动态电路的设计中,设计了一种获得更高性能、更小面积和更低功耗的模拟硬件形式;在提出的辅助变量电路和数字验证电路的模拟硬件设计中,实现了避免梯度下降搜索陷入无解和确定给定问题的解是否已经找到的目标;同时提出了降低面积和功耗的可替代辅助变量电路的两种设计方案。仿真实验结果表明,提出的新的模拟SAT求解器不仅是有效的,而且相比于单一软件算法实现的SAT求解器和其他硬件类SAT求解器具有更高的加速性能和更低的功耗。     

A hardware/software partitioning algorithm based on artificial immune principles

Hardware/software codesign is the main approach to designing the embedded systems. One of the primary steps of the hardware/software codesign is the hardware/software partitioning. A good partitioning scheme is a tradeoff of some constraints, such as power, size, performance, and so on. Inspired by both negative selection model and evolutionary mechanism of the biological immune system, an evolutionary negative selection algorithm for hardware/software partitioning, namely ENSA-HSP, is proposed in this paper. This ENSA-HSP algorithm is proved to be convergent, and its ability to escape from the local optimum is also analyzed. The experimental results demonstrate that ENSA-HSP is more efficient than traditional evolutionary algorithm.