A 2-dB noise figure 900-MHz differential CMOS LNA

This paper proposes a new circuit topology for RF CMOS low noise amplifier (LNA). Since pMOS devices are approaching the performances of nMOS devices in scaled technologies, the idea is to realize the input stage shunting an inductively degenerated nMOS stage with a pMOS one. In this way, due to the inherent current reuse, the performances can be improved using the same power consumption. Since the devices of an inductively degenerated input stage are working in moderate inversion (at least at moderate power dissipation), prior to the stage optimization an appropriate moderate inversion model is introduced. A fully differential 900-MHz 0.35-μm CMOS LNA (plus output buffer) prototype achieves the following performances: 2-dB noise figure (NF), 17.5-dB power gain, -6-dBm IIP3 with 8-mA current consumption from a 2.7-V voltage supply. To the author's knowledge, this is the lowest reported NF for a fully differential CMOS LNA operating at this power consumption level. As an additional feature, this LNA has a programmable gain     

A 2.7-V 900-MHz CMOS LNA and mixer

A CMOS low-noise amplifier (LNA) and a mixer for RF front-end applications are described. A current reuse technique is described that increases amplifier transconductance for the LNA and mixer without increasing power dissipation, compared to standard topologies. At 900 MHz, the LNA minimum noise figure (NF) is 1.9 dB, input third-order intercept point (IIP3) is -3.2 dBm and forward gain is 15.6 dB. With a 1-GHz local oscillator (LO) and a 900-MHz RF input, the mixer minimum double sideband noise figure (DSB NF) is 5.8 dB, IIP3 is -4.1 dBm, and power conversion gain is 8.8 dB. The LNA and mixer, respectively, consume 20 mW and 7 mW from a 2.7 V power supply. The active areas of the LNA and mixer are 0.7 mm×0.4 mm and 0.7 mm×0.2 mm, respectively. The prototypes were fabricated in a 0.5-μm CMOS process     

一种低于1dB噪声系数的单片集成GNSS低噪声放大器

A monolithic integrated low noise amplifier(LNA) based on a SiGe HBT process for a global navigation satellite system(GNSS) is presented. An optimizing strategy of taking parasitic capacities at the input node into consideration is adopted and a method and design equations of monolithically designing the LC load and the output impedance matching circuit are introduced. The LNA simultaneously reaches excellent noise and input/output impedance matching. The measurement results show that the LNA gives an ultra-low noise figure of 0.97 dB, a power gain of 18.6 dB and a three-order input intermodulation point of..6 dBm at the frequency of 1.575 GHz. The chip consumes 5.4 mW from a 1.8 V source and occupies 600×650 μm2 die area.     

A 900-MHz 1-V CMOS frequency synthesizer

A 900-MHz 1-V frequency synthesizer has been fabricated in a standard 0.35-μm CMOS technology. The frequency synthesizer consists of a divide-by-128/129 and 64/65 dual-modulus prescaler, phase-frequency detector, charge pump, and voltage-doubler circuit with an external voltage-controlled oscillator (VCO) and passive loop filter. The on-chip voltage-doubler circuit converts the 1-V supply voltage to the higher voltage which supplies the prescaler internally. In this way, the 900-MHz 1-V frequency synthesizer with an external VCO can be achieved. The measured phase noise is -112.7 dBc/Hz at a 100-kHz offset from the carrier, and the synthesizer dissipates 3.56 mW (not including VCOs) from a single 1-V supply when the switching frequency of the on-chip voltage doubler is 200 kHz and the power efficiency of the voltage doubler is 77.8%. The total chip area occupies 0.73 mm²     

A fully integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

A monolithic 900-MHz CMOS wireless receiver with on-chip RF and IF filters and a fully integrated fractional-N synthesizer is presented. Implemented in a standard 0.5-/spl mu/m CMOS process and without any off-chip component, the complete receiver has a measured image rejection of 79 dB, a sensitivity of -90 dBm, an IIP3 of -24 dBm, and a noise figure of 22 dB with a power of 227 mW and a chip area of 5.7 mm/sup 2/. The synthesizer achieves a phase noise of -118 dBc/Hz at 600 kHz offset and a settling time of less than 150 /spl mu/s.     

A low-noise, 900-MHz VCO in 0.6-μm CMOS

This paper describes a low-noise, 900-MHz, voltage-controlled oscillator (VCO) fabricated in a 0.6-μm CMOS technology. The VCO consists of four-stage fully differential delay cells performing full switching. It utilizes dual-delay path techniques to achieve high oscillation frequency and obtain a wide tuning range. The VCO operates at 750 MHz to 1.2 GHz, and the tuning range is as large as 50%. The measured results of the phase noise are -101 dBc/Hz at 100-kHz offset and -117 dBc/Hz at 600-kHz offset from the carrier frequency. This value is comparable to that of LC-based integrated oscillators. The oscillator consumes 10 mA from a 3.0-V power supply. A prototype frequency synthesizer with the VCO is also implemented in the same technology, and the measured phase noise of the synthesizer is -113 dSc/Hz at 100-kHz offset     

A variable gain amplifier with 50-dB control range for 900-MHz applications

A variable gain amplifier for 900-MHz applications has been designed and fabricated in a BiCMOS process with f/sub T/ = 24 GHz. The amplifier has linear-in-dB gain control with a 50-dB control range. The maximum gain is 28 dB and the third-order output intercept point (OIP3) is 13.7 dBm. The gain is achieved in one gain stage with a cascoded output. The amplifier bias network and the gain-control circuitry are temperature compensated for temperature-independent gain at any gain setting. The bias network also uses a feedback loop to cancel out undesired low frequencies present at the radio-frequency input. The maximum output power is +10 dBm and the output 1-dB compression point is +8.7 dBm. Active chip area is 0.1 mm/sup 2/. The amplifier is packaged in a SOT-363 and consumes 30 mA from a 2.8-V supply.     

A 4.5-mW 900-MHz CMOS receiver for wireless paging

An ultralow-power 900-MHz receiver implemented on a single CMOS chip is intended for use in FLEX wireless paging. The receiver uses an indirect conversion to zero intermediate frequency (IF) to suppress the flicker noise corner in the second mixer to less than 1 kHz. Various techniques for low-power design, most of them unique to CMOS, are presented, with theoretical support and experimental verifications. The receiver, fabricated in a 0.25-μm standard CMOS process, achieves 7.4-dS noise figure at 1.6 kHz with -25-dBm IIP3 on a 1.5 V supply. The voltage-controlled oscillator (VCO) has a phase noise of -98 dBc/Hz at 25 kHz offset. The nominal receiver bias current of 3 mA is higher than the expected 2 mA because of unanticipated losses in coupling capacitors     

A 900-MHz dual-conversion low-IF GSM receiver in 0.35-μm CMOS

A low-power fully integrated GSM receiver is developed in 0.35-μm CMOS. This receiver uses dual conversion with a low IF of 140 kHz. This arrangement lessens the impact of the flicker noise. The first IF of 190 MHz best tolerates blocking signals. The receiver includes all of the circuits for analog channel selection, image rejection, and more than 100-dB controllable gain. The receiver alone consumes 22 mA from a 2.5-V supply, to give a noise figure of 5 dB, and input IP3 of -16 dBm. A single frequency synthesizer generates both LO frequencies. The integrated VCO with on-chip resonator and buffers consume another 8 mA, and meets GSM phase-noise specifications     

A low-phase-noise 900-MHz CMOS ring oscillator with quadrature output

A 900-MHz two-stage CMOS voltage controlled ring oscillator (VCRO) with quadrature output is presented. The circuit is designed in a 0.18-um CMOS technology and operated on a 1.8-V supply voltage. The VCRO have a tuning range of 730 MHz to 1.43 GHz and good tuning linearity. Between 0 V and 1.1 V of control voltage, the gain of VCRO is around −620 MHz/V. At 900 MHz, the phase noise of the VCRO is −106.1 dBc/Hz at 600-KHz frequency offset with power consumption of 65.5 mW.     

A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chipautomatic tuning

A maximally flat 10.7-MHz fourth-order bandpass filter with an on-chip automatic tuning system is presented. The signal-to-in-band integrated noise ratio (SNR) of the automatically tuned filter is around 68 dB. The third intermodulation distortion (IM3) is lower than -40 dB for a two-tone input signal of 3.2 V peak to peak (V_p-p). The complete system operates with supply voltages of ±2.5 V. The power consumption of the system is 220 mW. All this has been achieved due to the use of a low-distortion transconductor, the development of a high-frequency CMOS resistor, and the realization of an advanced on-chip automatic tuning system for both frequency and bandwidth control. The chip has been fabricated in a standard 1.5-μm n-well CMOS process     

Design of a Sub-mW 960-MHz UWB CMOS LNA

This paper presents a sub-mW ultra-wideband (UWB) fully differential CMOS low-noise amplifier (LNA) operating below 960 MHz for sensor network applications. By utilizing both nMOS and pMOS transistors to boost the transconductance, coupling the input signals to the back-gates of the transistors, and combining the common-gate and shunt-feedback topologies, the LNA achieves 13 dB of power gain, a 3.6 dB minimum noise figure, and -10 dBm of IIP3 with only 0.72 mW of power consumption from a 1.2 V supply     

A 3.3-V CMOS 10.7-MHz sixth-order bandpass ΣΔ modulatorwith 74-dB dynamic range

A 3.3-V bandpass ΣΔ modulator for IF sampling at 10.7 MHz in digital radio applications has been developed. The modulator presents a sixth-order single-loop architecture and features a 74-dB dynamic range in a 2OO-kHz signal bandwidth (FM signal), while for a 9-kHz signal bandwidth (AM signal) the dynamic range is 88 dB. The modulator has been integrated in a standard 0.35-μm CMOS technology using switched-capacitor technique and consumes 76 mW from a single 3.3V supply     

A 900-MHz/1.8-GHz CMOS transmitter for dual-band applications

The design of a radio-frequency transmitter that can operate in two bands while employing a minimal number of external components entails many challenges at both the architecture and the circuit levels. This paper describes the design of a 900-MHz/1.8-GHz transmitter implemented in CMOS technology for dual-band applications. Configured as a two-step architecture, the circuit generates the first upconverted signal in quadrature form and subsequently performs single-sideband modulation to produce the output in two bands. Fabricated in a 0.6-μm digital CMOS technology, the transmitter exhibits unwanted spurs 40 dB below the carrier while drawing 75 mW from a 3-V supply     

A 60-dB 246-MHz CMOS variable gain amplifier for subsampling GSM receivers

A variable gain amplifier (VGA) is designed for a GSM subsampling receiver. The VGA is implemented in a 0.35-/spl mu/m CMOS process and approximately occupies 0.64 mm/sup 2/. It operates at an IF frequency of 246 MHz. The VGA provides a 60-dB digitally controlled gain range in 2-dB steps. The overall gain accuracy is less than 0.3 dB. The current is 9 mA at 3 V supply. The noise figure at maximum gain is 8.7 dB. The IIP3 is -4 dBm at minimum gain, while the OIP3 is -1 dBm at maximum gain. The group delay is 1.5 ns across 5-MHz bandwidth.     

A 110-MHz 84-dB CMOS programmable gain amplifier with integrated RSSI function

This paper describes a CMOS programmable gain amplifier (PGA) that maintains a 3-dB bandwidth greater than 110 MHz and can provide an 84-dB gain control range with 1-dB step resolution. The PGA can also be operated in a low-power mode with 3-dB bandwidth greater than 71 MHz. Integrated with this PGA is a CMOS successive logarithmic detecting amplifier with a /spl plusmn/0.7-dB logarithmic accuracy over an 80-dB dynamic range. It achieves -83-dBm sensitivity and consumes 13 mA from a single 3-V supply in the normal power mode. The chip area, including pads, occupies 1.5/spl times/1.5 mm/sup 2/.     

A single-chip 900-MHz spread-spectrum wireless transceiver in1-μm CMOS. II. Receiver design

For pt. I see ibid., vol. 33, no. 4, April 1998. A 900-MHz direct-conversion receiver to detect a frequency-hopped carrier with frequency shift keying (FSK) modulation at 160 kb/s is integrated on the same chip as the transmitter. The receiver combines a low-noise amplifier with downconversion mixers and low-pass channel-select filters in quadrature channels. A digital correlating detector makes the data decisions. The received signal is dehopped when it is down-converted. The cascade noise figure is 8.6 dB, and the cascade IIP3 is -8.3 dBm. In active mode, the receiver takes 120 mA from 3 V     

A 30-MHz Fifth-Order Elliptic Low-Pass CMOS Filter With 65-dB Spurious-Free Dynamic Range

A fifth-order 30-MHz integrated low-pass filter with 65-dB spurious-free dynamic range is presented. The topology is based on an operational transconductance amplifier (OTA)-C ladder configuration implementing an elliptic transfer function. High linearity and low noise are achieved by using polysilicon resistors and efficient highly linear transconductors based on a proposed nonlinear source degeneration technique. The linearity of a typical source degenerated structure is improved by more than 10 dB while the small-signal transconductance is reduced by less than 1 dB; the additional power needed by the auxiliary circuitry is less than 10% that of the OTA's power, and the noise level increases by no more than 1 dB. Experimental results of a prototype fabricated in a standard 0.35-mum CMOS technology are presented and compared with previously reported solutions. The overall filter's power consumption is 85 mW with a 3.3-V power supply     

A 0.5-μm CMOS T/R switch for 900-MHz wireless applications

A single-pole double-throw transmit/receive switch for 3.0-V applications has been fabricated in a 0.5-μm CMOS process. An analysis shows that substrate resistances and source/drain-to-body capacitances must be lowered to decrease insertion loss. The switch exhibits a 0.7-dB insertion loss, a 17-dBm power 1-dB compression point (P_{1 dB}), and a 42-dB isolation at 928 MHz. The low insertion loss is achieved by optimizing the transistor widths and bias voltages, by minimizing the substrate resistances, and by dc biasing the transmit and receive nodes, which decreases the capacitances while increasing the power 1-dB compression point. The switch has adequate insertion loss, isolation, P_{1 dB}, and IP₃ for a number of 900-MHz ISM band applications requiring a moderate peak transmitter power level (~15 dBm)     

A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR

This paper proposes a high-speed CMOS transconductor with its linearity enhanced by current–voltage negative feedback. This voltage-to-current converter is mainly composed of two parts: an operational transconductance amplifier and a pair of feedback resistors. The measured spurious-free dynamic range of the transconductor achieves 72.6 dB when the input frequency is 100 MHz. To compensate for common-mode deviation due to process and temperature variation, digital calibration circuits are added. With the proposed calibration scheme, the common-mode voltage deviation is eliminated within 24 clock cycles. Fabricated in TSMC 0.13-$muhbox{m}$ CMOS process, the transconductor occupies 220 $,times,$160 $muhbox{m}^{2}$ active area and consumes 6 mW from a 1.2-V supply where the calibration circuits only consume 16% of the overall power consumption.