Design of a W-band Stepped-frequency Synthesizer with Fast Frequency Switching

In this paper, a W-band coherent stepped-frequency synthesizer is proposed, which provides transmitter and local oscillator signals to a high range resolution radar system. This synthesizer is realized by combining the technique of direct digital synthesizer, phase lock loop, up-conversion and multiplier chain, etc. In order to shorten the lock time of the phase lock loop, a new method is introduced in the design of this synthesizer. Measurement results show that the transmitting signal is around 94 GHz, the bandwidth is 504 MHz, the phase noise is about −90 dBc/Hz at 10 kHz offset, and the spurious signals are less than −55 dBc. Especially, the frequency switching time of this synthesizer is about 1 μs. With the W-band stepped-frequency synthesizer, the range resolution of the high range resolution radar system is better than 0.6 m.     

A monolithic sigma-delta fractional-N frequency synthesizer with implicit dual-path filter and phase switching multi-modulus frequency divider

A fully integrated Sigma-delta fractional-N frequency synthesizer is realized in TSMC 0.18 μm MM/RF 1P6M Salicide 1.8V/3.3V technology. The proposed implicit dual-path loop filter with enhanced trans-conductor can eliminate the charge pump mismatch of the conventional dual-path loop filter and suppress the effect of parasitic poles and zero as well as reduce the area of the loop filter. A simple frequency divider based on phase switching technique is employed to reduce the area and power dissipation. The frequency synthesizer consumes 21 MW power from 1.8 V power supply voltage with area 1.80  ×  2.0 mm². The achieved phase noise is −82 dBc/Hz at 10 kHz offset, −108 dBc/Hz at 100 kHz offset and −128 dBc/Hz at 1 MHz offset respectively with frequency switching time 95 μs.     

Wideband Frequency Synthesizer at X/Ku Band by Mixing and Phase Locking of Half Frequency Output of VCO

A wideband low phase noise frequency synthesizer at X/Ku band has been developed by using phase locking and mixing technique at half frequency of voltage controlled oscillator (VCO). The half frequency output signal of the VCO is down converted by a balanced mixer at C band to obtain an intermediate frequency (IF) signal used for phase locking of the VCO. An ultra low phase noise local signal source at 6 GHz is developed with a frequency multiplying chain driven by a 100 MHz oven controlled crystal oscillator (OCXO). Coupling circuit outside the VCO chip to the mixer does not need to be specially designed, which is beneficial to simplify the circuit scheme and improve the phase noise performance. Measurement results show that the phase noise of the output signal at 10.6 GHz to 11.8 GHz and 12.3 GHz to 13.0 GHz is better than −102 dBc/Hz at 10 kHz away form the carrier center. This frequency synthesizer can be used as local signal source or driving source for the development of wideband millimeter-wave frequency synthesizer systems.     

GHz band frequency hopping PLL-based frequency synthesizers

In this paper we describe a full-integrated circuit containing all building blocks of a completed PLL-based synthesizer except for low pass filter（LPF）. The frequency synthesizer is designed for a frequency hopping （FH） transceiver operating up to 1.5 GHz as a local oscillator. The architecture of Voltage Controlled Oscillator （VCO） is optimized to get better performance, and a phase noise of -111.85-dBc/Hz @ 1 MHz and a tuning range of 250 MHz are gained at a centre frequency of 1.35 GHz. A novel Dual-Modulus Prescaler（DMP） is designed to achieve a very low jitter and a lower power. The settling time of PLL is 80 μs while the reference frequency is 400 KHz. This monolithic frequency synthesizer is to integrate all main building blocks of PLL except for the low pass filter, with a maximum VCO output frequency of 1.5 GHz, and is fabricated with a 0.18 μm mixed signal CMOS process. Low power dissipation, low phase noise, large tuning range and fast settling time are gained in this design.     

A fast-locking agile frequency synthesizer for MIMO dual-mode WiFi/WiMAX applications

In this paper, a wide-range and fast-locking phase-locked loop (PLL) frequency synthesizer using the band selection technique for the agile voltage-controlled oscillator (VCO) is proposed. The minimum time for band selection, discretely tuned by a time-to-voltage converter, can reach four times of the reference period. In addition, a current-enhanced circuit applied to the PLL can make settling behavior faster. The synthesizer is implemented in a 0.13-μm CMOS process, which provides the range from 4.6 GHz to 5.4 GHz with the phase noise of −106 dBc/Hz at 1-MHz offset. Combining the fast-locking techniques, the lock time of the synthesizer can be less than 13.2 μs and consume 39 mW from a 1.2-V power supply.     

Single-VCO multi-band DTV frequency synthesizer with a divide-by-3 frequency divider for quadrature signal generation

A multi-band frequency synthesizer for In-phase and Quadrature (I/Q) LO signal generation in Digital TV tuners is presented. Using divisor numbers other than powers of 2 (2 ⁿ ) for quadrature generation, reduces the required frequency range of the VCO, hence the number of VCO circuits, in multi-band frequency synthesizers. In the proposed synthesizer, VHF, UHF and L-band frequencies are covered with only one VCO. This is achieved by using a novel divide-by-3 circuit which produces precise I/Q LO signals. The VCO tuning range in this design is 2,400–3,632 MHz which is covered by a 6-bit switched-capacitor bank. A fast adaptive frequency calibration block selects the closest VCO frequency to the target frequency by setting the coarse-tuning code prior to the start of phase lock. A programmable charge pump is used to reduce variations in PLL characteristics over the frequency range. The synthesizer has been fabricated in a 0.18 μm CMOS technology and the die area is 1.7 × 1.6 mm². It consumes 27 mA from a 1.8 V power supply. Measurement results show operation of the proposed divide-by-3 circuit over the entire VCO frequency range. The synthesizer quadrature output phase noise for UHF and VHF bands is <−131dBc/Hz at 1.45 MHz offset.     

A CMOS broadband frequency synthesizer for DVB-C receiver

A 70∼900 MHz broadband PLL frequency synthesizer is developed for the single conversion DVB-C receiver in a standard 0.25 μm CMOS technology. The true 3-band VCO with a novel AAC (Auto-Amplitude Control) circuit provides a wideband amplitude stable output and a reliable startup without degrading the phase noise performance. A 16/17 dual-modulus prescaler with a new logic structure has increased the speed. The charge pump current is programmable for wide loop stabilization and phase noise optimization. The measured results show that the locked range of the frequency synthesizer is 70∼900 MHz. The worst phase noise at 1 k/10 k/100 k/1 MHz offset frequency is ordinal −65/−85/−112/−128 dBc/Hz and the spur at reference frequency is lower than −90 dBc.The frequency synthesizer chip dissipates only 16.2 mA from a 3.3 V supply.     

A low-power phase-locked loop for UWB applications

This paper describes a low-power phase-locked loop (PLL) design for WiMedia UWB synthesizer implemented in a 0.13-μm CMOS process. Three parallel PLLs and a multiplexer (MUX) constitute a frequency synthesizer which is used to generate carrier frequencies to UWB band groups 1 and 3. The implemented PLL consumes only 10 mW from a 1.2-V supply. Moreover, it achieves a close-in spurious tone level of −54 dBc and in-band phase noise of −78 dBc/Hz.     

A low phase noise and low power 3–5 GHz frequency synthesizer in 0.18 µm CMOS technology

A low power frequency synthesizer for WLAN applications is proposed in this paper. The NMOS transistor-feedback voltage controlled oscillator (VCO) is designed for the purpose of decreasing phase noise. TSPC frequency divider is designed for widening the frequency range with keeping low the power consumption. The phase frequency detector (PFD) with XOR delay cell is designed to have the low blind and dead zone, also for neutralizing the charge pump (CP) output currents; the high gain operational amplifier and miller capacitors are applied to the circuit. The frequency synthesizer is simulated in 0.18 µm CMOS technology while it works at 1.8 V supply voltage. The VCO has a phase noise of −136 dBc/Hz at 1 MHz offset. It has 10.2% tuning range. With existence of a frequency divider in the frequency synthesizer loop the output frequency of the VCO can be divided into the maximum ratio of 18. It is considered that the power consumption of the frequency synthesizer is 4 mW and the chip area is 10,400 µm².     

CMOS implementation of a 1.6 GHz low voltage low phase noise quadrature output frequency synthesizer with automatic amplitude control

This article presents the design of a 1.2 V CMOS low phase noise quadrature output frequency synthesizer (FS) to be used for a GPS tuner application. Special reference is made to the design of a wide tuning range quadrature output voltage-controlled oscillator which is equipped with an automatic amplitude controller. It exhibits a phase noise response of less than −115 dBc/Hz at an offset of 1 MHz from the carrier and has a tuning range of over 36%. The effect of the automatic amplitude control is shown to improve phase noise at high oscillation frequencies and its noise has a negligible effect on the phase noise response even at low offset frequencies from the carrier. Preliminary analysis is presented showing the negligible effect of a DC–DC converter on the spurious level of the FS, included to permit the use of low sensitivity varactors. Design guidelines for reducing both the loop noise and the AM-to-PM conversion factors of the oscillator are also given. The design was made using the STMicroelectronics 0.13 μm HCMOS9-RF technology design kit.     

A SiGe BiCMOS 24-GHz receiver front-end for automotive short-range radar

This paper presents a fully integrated SiGe BiCMOS 24-GHz receiver front-end implemented for a ultra-wideband automotive short-range radar sensor. The circuit consists of a homodyne I/Q down-converter and a 24-GHz synthesizer. The receiver front-end is able to achieve a power conversion gain as high as 30 dB and a 6-dB noise figure, while preserving high linearity performance thanks to a 1-bit gain control. The frequency synthesizer, which also includes an on-chip loop filter, guarantees a phase noise of −104 dBc/Hz at 1-MHz offset from the 24.125-GHz carrier and a 4.7-GHz tuning range from 20.4 to 25.1 GHz.     

A single-PLL dual-PPF synthesizer for Mode-1 MB-OFDM UWB communication

A frequency synthesizer incorporating a single-PLL and single-sideband (SSB) mixers for Multi-Band OFDM Mode-1 UWB application is presented in this paper. The proposed synthesizer employs RC poly phase filter to suppress unwanted tones and correct phase and amplitude errors between quadrature paths. Fabricated in a 0.18-μm CMOS technology, this circuit achieves a sideband rejection of −32.27 dB, integrated phase noise of 2.138°, and a switching time of less than 2.05 ns while consuming 66 mW from a 1.8-V supply.     

A crystal-tolerant fully integrated CMOS low-IF dual-band GPS receiver

This paper presents the design of a dual-band L1/L2 GPS receiver, that can be easily integrated in portable devices (mainly GSM mobile phones). For the ease of integration with GSM wireless systems the receiver can tolerate most of the common GSM crystals, besides the GPS crystals, this will eliminate the need to use another crystal on board. A new frequency plan is presented to satisfy this requirement. A low-IF receiver architecture is used for dual-band operation with analog on-chip image rejection. The receiver is composed of a narrow-band LNA for each band, dual down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and a fully integrated frequency synthesizer including an on-chip VCO and loop filter. The complex filter can accept IF frequency variation of 10% around 4.092 MHz which allows the use of the commonly used 10/13/26 MHz GSM crystals and all the GPS crystals. The synthesizer generates the LO signals for both L1/L2 bands with an average phase noise of −95 dBc/Hz. The receiver exhibits maximum gain of 112 and 115 dB, noise figures of 4 and 3.6 dB, and input compression points of −76 and −79 dBm for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection greater than 25 dB and gain control range over 80 dB. The receiver is designed in 0.13 μm CMOS technology and consumes 18 mW from a 1.2-V supply.     

A 1.41–1.72 GHz sigma-delta fractional-N frequency synthesizer with a PVT insensitive VCO and a new prescaler

A 1.41–1.72 GHz fractional-N phase-locked loop (PLL) frequency synthesizer with a PVT insensitive voltage-controlled oscillator (VCO) is presented. In this PLL, a VCO with process, voltage, and temperature (PVT) insensitive bias circuit, and a divided-by-7/8 prescaler with improved multi-phase frequency divider are adopted. A novel multi-stage noise shaping (MASH) sigma-delta modulator (SDM) is adopted here. A new combination of low-current-mismatch charge pump (CP) and a phase/frequency detector (PFD) is proposed in this paper. Using Hejian Technology CMOS 0.18 μm analog and digital mixed-mode process, a fractional-N PLL prototype circuit is designed, the VCO in the prototype circuit can operate at a central frequency of 1.55 GHz, and its phase noise is −121 dBc/Hz at 1.0 MHz, the variety of phase noise is depressed by about 1.4 dB with the help of PVT insensitive bias. Under a 1.8-V supply voltage, the phase noise of the PLL is −113 dBc/Hz at 1.0 MHz.     

Architecture of a dual-mode cascaded-loop frequency synthesizer

A new architecture for a frequency synthesizer with adjustable output frequency range and channel spacing is introduced. It is intended for the generation of closely spaced frequency channels in the GHz range while producing minimal spurious phase noise components. The architecture employs two independent phase-locked loops that are driven in cascade by a single reference oscillator. This approach provides fine resolution and wide bandwidth as well as low phase noises. The synthesizer can be operated in either of two different modes: nonfractional and mini-denominator fractional modes. The architecture produces no fractional spurs in the first mode and relatively small phase spurs in the second mode. It is simulated that, in an application to a P-GSM 900 system tuning from 890 to 915 MHz with a channel spacing of 200 kHz, the worst case phase spurs are of −100 dBc at an offset frequency of 833 kHz and the linear frequency-switching settling time (to 0.01% of frequency increments) is of 128 μs.     

C波段低相噪频率合成器设计

低相噪频率合成是通信电路设计中的关键技术,在射频和微波领域应用广泛。基于混频锁相原理,介绍了一种低相噪频率合成方法。通过建立噪声模型,对影响相位噪声的主要因素进行了详细论述。结合实际应用提出了一个C波段低相噪频率合成设计方案,并对关键指标的实现和试验结果进行了分析和讨论。     

An ultra-low power ISM-band integer-N frequency synthesizer dedicated to implantable medical microsystems

In this article, the architectural choices and design of a fully integrated integer-N frequency synthesizer operating in the 902–928 MHz Industrial, Scientific and Medical (ISM) band is presented. This frequency synthesizer, optimized for ultra-low power operation, is being integrated in the transceiver of an implantable wireless sensing microsystem (IWSM), which is dedicated to in vivo monitoring of biological parameters such as temperature, pressure, pH, oxygen, and nitric oxide concentrations. This phase-locked loop-based synthesizer includes a 1.830 GHz LC voltage-controlled oscillator (VCO) using a 10 nH on chip inductor. Varactors are implemented using P+ in N-well diodes for their linearity and high quality factor. The transistors of the VCO are operated in moderate inversion, and their bias point was chosen using the g _m/I _d design methodology. The output of the VCO, operating at twice the ISM frequency band, is divided by 2 to generate differential, quadrature versions of the carrier. Power minimization of the programmable divider was achieved by designing the latches and flip-flops using appropriate circuit techniques such as True Single Phase Clocking (TSPC) and first-type Dynamic Single Transistor Clocking (DSTC1) depending on their operating frequency. The power consumption of the proposed synthesizer is 580 μW under 1 V; almost an order of magnitude lower compared to that of recent synthesizer designs having a similar architecture.     

具有自校准压控振荡器和精确自动频率校准算法的低噪声频率合成器

A low noise phase locked loop （PLL） frequency synthesizer implemented in 65 nm CMOS technology is introduced. A VCO noise reduction method suited for short channel design is proposed to minimize PLL output phase noise. A self-calibrated voltage controlled oscillator is proposed in cooperation with the automatic frequency calibration circuit, whose accurate binary search algorithm helps reduce the VCO tuning curve coverage, which reduces the VCO noise contribution at PLL output phase noise. A low noise, charge pump is also introduced to extend the tuning voltage range of the proposed VCO, which further reduces its phase noise contribution. The frequency synthesizer generates 9.75-11.5 GHz high frequency wide band local oscillator （LO） carriers. Tested 11.5 GHz LO bears a phase noise of-104 dBc/Hz at 1 MHz frequency offset. The total power dissipation of the proposed frequency synthesizer is 48 mW. The area of the proposed frequency synthesizer is 0.3 mm^2, including bias circuits and buffers.     

Parametric Analysis to Reduce Phase Noise of Frequency Synthesizers for Wireless Communication System

The aim of this paper is analysis and presenting a technique to reduce phase noise of frequency synthesizer for pure signal synthesis. To reduce phase noise of synthesizer, first, we present a mathematical and accurate model of phase noise in phase locked loop based frequency synthesizer with take into account noise of its component. Then we predict output phase noise in term of its parameters. Finally, we describe as effective technique for phase noise in frequency synthesizer. The simulation results show the performance of the frequency synthesizer for the High Speed communication system.