Enhanced phase noise modeling of fractional-N frequency synthesizers

Mathematical models for the behavior of fractional-N phase-locked-loop frequency synthesizers (Frac-N) are presented. The models are intended for calculating rms phase error and determining spurs in the output of Frac-N. The models describe noise contributions due to the charge pump (CP), the phase frequency detector (PFD), the loop filter, the voltage control oscillator, and the delta-sigma modulator. Models are presented for the effects of static CP gain mismatch, CP dynamic mismatch and PFD reset delay mismatch. A simple analytic expression shows the level of /spl Delta//spl Sigma/ sequence noise caused by static CP current mismatch. We further show that un-equal rise time and fall time constants of the CP result in dynamic mismatch noise. Reset delay mismatch in PFD is shown to also contribute significantly to close-in phase noise. The model takes into account the reduction in CP thermal and flicker noise due to the changing duty cycle of Frac-N CP. Our model is therefore useful in characterizing the noise performance of Frac-N at the system-level, simplifying the design of fractional-N synthesizers and transmitters. Analytical and simulated results are compared and show good agreement with prior published data on Frac-N realizations.     

锁相频率合成器相位噪声的精确估计与仿真

实现对相位噪声的精确估计必须考虑环路中电阻噪声的影响.从建立并分析电阻噪声模型出发,设计了两种都能满足基本技术指标的环路滤波器.用仿真手段对这两种不同的环路滤波器进行了仿真,清楚地表明了电阻对相位噪声的影响.最后的实验结果证明了这种估计方法的精确性.     

A stabilization technique for phase-locked frequency synthesizers

A stabilization technique is presented that relaxes the tradeoff between the settling speed and the magnitude of output sidebands in phase-locked frequency synthesizers. The method introduces a zero in the open-loop transfer function through the use of a discrete-time delay cell, obviating the need for resistors in the loop filter. A 2.4-GHz CMOS frequency synthesizer employing the technique settles in approximately 60 /spl mu/s with 1-MHz channel spacing while exhibiting a sideband magnitude of -58.7 dBc. Designed for Bluetooth applications and fabricated in a 0.25-/spl mu/m digital CMOS technology, the synthesizer achieves a phase noise of -112 dBc/Hz at 1-MHz offset and consumes 20 mW from a 2.5-V supply.     

Prediction of the impact of substrate coupled switching noise on frequency synthesizers

This paper proposes a methodology to accurately predict the phase noise effects in frequency synthesizers as a consequence of switching noise coupled through the substrate. The method proposed is based on a phase model of a frequency synthesizer where each circuit block is characterized by complex noise sensitivity functions. Considering the phase information of the different contributors allows to evaluate the noise without overestimation, as well as identifying the main noise contributors. This information can then be used by designers to decide where to put the effort to mitigate the noise effects. The methodology is applied to a typical N-Integer frequency synthesizer based on a LC-VCO. Measurements on this frequency synthesizer implemented in a 0.35 μm CMOS technology have provided information of the relative importance of the noise aggressors, the effect of the loop on the phase noise, as well as comparison to the predictions obtained with the proposed methodology.     

A high-frequency CMOS multi-modulus divider for PLL frequency synthesizers

A high-frequency divide-by-256–271 programmable divider is presented with the improved timing of the multi-modulus divider structure and the high-speed embedded flip-flops. The D flip-flop and logic flip-flop are proposed by using a fast pipeline technique, which contains single-phase, edge-triggered, ratioed, and high-speed technologies. The circuits achieve high-speed by reducing the capacitive load and sharing the delay between the combination logic blocks and the storage elements. By the way, it is suitable for realizing high-speed synchronous counters. The programmable divider using proposed flip-flops is measured in 0.25-μm CMOS technology with the operating clock frequency reaching as high as 4.7 GHz under the supply voltage of 3V.     

An overview of frequency synthesizers for radars

The authors present an overview of frequency synthesizer techniques suitable for radar systems. Various synthesizer architectures and key synthesizer components are considered along with a discussion of advantages and disadvantages. Some architectures are hardware intensive and, because of their physical size, are more suitable for stationary or shipboard radars. Architectures requiring smaller volume are more suitable for airborne applications. Direct, phase-locked, and frequency-locked architectures are covered, including key building blocks and performance limitations. The direct digital synthesizer (DDS) architecture is considered briefly, as it is not yet widely used in radar systems. Finally, projections are made of advances in components that have a direct effect on frequency synthesis     

A modeling approach for /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers allowing straightforward noise analysis

A general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations. The proposed model allows straightforward noise and dynamic analyses of /spl Sigma/-/spl Delta/ fractional-N frequency synthesizers and other PLL applications in which the divide value is varied in time. Based on the derived model, a general parameterization is presented that further simplifies noise calculations. The framework is used to analyze the noise performance of a custom /spl Sigma/-/spl Delta/ synthesizer implemented in a 0.6 /spl mu/m CMOS process, and accurately predicts the measured phase noise to within 3 dB over the entire frequency offset range spanning 25 kHz to 10 MHz.     

一种X波段低相噪跳频源的设计

基于小数分频锁相环HMC704LP4设计了一种X波段跳频源,具有相位噪声低、杂散低、体积小的特点。针对指标要求拟定设计方案,简述设计过程,给出设计参数,对关键指标进行分析仿真,并给出测试曲线。     

Analysis and minimization of substrate spurs in fractional-N frequency synthesizers

This paper analyses substrate-related spurious tones in fractional-N phase-locked loops with integrated VCOs. Spur positions are calculated and experimentally verified as a function of the divider ratios of prescaler and programmable divider. For an integrated wideband PLL in SiGe BiCMOS technology the spur power levels are measured and compared with theoretical expectations. The power in these spurs is minimized by layout techniques shielding the reference input buffer. Spur minimization by using a variable reference frequency is experimentally demonstrated. Based on this observation, a programmable integer-N PLL for driving the fractional-N synthesizer is suggested to reduce the worst-case spur level significantly.     

A solid-state instrument for the measurement of frequency and phase angle in power systems

This paper describes the development of an instrument, using electronic switching circuits for the measurement of frequency and phase angles in power systems. The phase angle and frequency are indicated on a meter with linear scale. The instrument responds to changes in system frequency and the phase-angle measurement is inherently lead-lag sensitive.     

数字频率合成器的原理与实现

现代高速信息处理系统需要具备稳定精确的定时基准。系统设计人员长期以来依赖的是晶体振荡器的精度和稳定性。但是,由于系统频率的提晨以及市场竞争的压力,促使设计人员充分利用集成数字频率合成器的诸多优点,以缩短产品的开发周期。本文回顾了集成频率合成器的基本工作方式,使用MicrosoftExcel解释和举例说明了与它们的使用相关的频率计算方法。晶体振荡器晶体振荡器的最大好处在于通过对振荡器“心脏”石英晶体元件进行微调就能达到良好的频率精度。遗憾的是,由于这种微调是一种机械过程,晶体生产厂家为了实现标准的批量生产,已…     

Optimized reduction of spur tones in fractional frequency synthesizers

In this article the contribution of the digital \Upsigma\Updelta\Upsigma\Updelta modulator in fractional frequency synthesizers is explored. Due to the circuit’s non linear behavior, the spur tones generated by the digital \Upsigma\Updelta\Upsigma\Updelta modulation degrade the synthesizer’s phase noise even in regions where the charge pump noise is dominant. A new method to dither digital MASH \Upsigma\Updelta\Upsigma\Updelta modulators for fractional frequency synthesizers is proposed. The method barely increases the circuit complexity and has the same performance as more cumbersome architectures. Also, a new design consideration to linearize the voltage control oscillator is proposed. Experimental results are obtained in an on-chip fractional synthesizer manufactured in CMOS technology.     

Complementary BAW oscillator for ultra-low power consumption and low phase noise

A complementary cross coupled BAW parallel resonance oscillator offering ultra-low power consumption and a good phase noise performance is presented. The power consumption in this structure is 50?% less than the classical NMOS based structure without any penalty in the phase noise performance. Rather, this structure serves to reduce the noise contribution of the biasing transistors at the output leading to a marginal improvement in thermal noise performance as compared to the NMOS based structure. Furthermore, the flicker noise upconversion of this complementary structure can be minimized by proper design considerations. The power consumption in case of such a complementary structure based oscillator (designed in 180nm CMOS process) employing a 2.497?GHz BAW resonator is around 675???W for an amplitude of 300?mV with a phase noise of ?140?dBc/Hz at 1?MHz offset.     

Probability density function for the phase and frequency noise in a semiconductor laser

A physical definition for the phase and frequency noise of a semiconductor laser is given, which can be applied in determining the performance of coherent optical communication systems. The definition allows a filtered Poisson model to be developed for the probability density function (pdf) of the laser output phase or frequency noise, based on evaluating the cumulants of the noise processes. A condition is derived to quantify under what laser and system conditions a Gaussian pdf is a good approximation. It is shown that the phase and frequency noise can increase significantly for bit rates approaching the relaxation oscillation frequency of the laser diode.     

New 800-MHz frequency synthesizers for cellular land mobile telephone equipment

800-MHz frequency synthesizers, constructed by the 800- MHz directly divided method, are presented. High spectral purity and fast channel switching time are obtained. These synthesizers contribute to the simplification of the local oscillator vehicular equipment.     

Optical power requirements for detecting OOK and FSK signalscorrupted by phase noise

The decision of on-off keying (OOK) and frequency-shift keying (FSK) is considered for coherent lightwave communications in which the optical pulses are corrupted by the phase noise associated with nonzero laser linewidths. Heterodyne lightwave detection is assumed, followed by intermediate frequency filtering, envelope detection, and postdetection low-pass filtering. Using analytical results published previously, theoretical minimum values of the required average power are obtained in photons/bit, for achieving a bit error rate of 10^-9. Numerical results are given as functions of laser linewidth-to-bit-rate ratio for OOK, binary FSK (or 2-FSK), and 8-FSK. It is shown that heterodyne detection for lightwave signals of this kind can be made highly robust to phase noise, in contrast to the case of binary phase-shift keying     

全相位滤波白噪声产生有色噪声及其功率谱估计

本文提出用全相位数字滤波器这种新型滤波器滤波白噪声产生有色噪声的方法,这种方法比用传统FIR滤波器产生的有色噪声频谱泄漏少,阻带衰减功率大等优点.并且分别用Welch法和全相位法对在有色噪声中混入的双频小信号余弦波进行谱估计,实验证明全相位谱估计性能优于经典谱估计.     

Phase/frequency detector phase noise contribution in PLL frequencysynthesiser

A straightforward mathematical analysis of the noise contribution of a phase/frequency detector in a PLL frequency synthesiser is presented. A figure of merit is derived which allows comparison of different phase/frequency detectors and an accurate estimate of their performance in given configurations. Experimental results show excellent agreement with theory     

直接数字频率合成技术杂散信号频谱性能分析

本文介绍了直接数字频率合成技术DDS(Direct Digital Frequency Synthesizers)工作原理,分析了其理想频谱;采用信号分析的方法深入研究了DDS存在相位截断和幅度量化时引入的杂散信号频谱分布的规律和性能;定性讨论了DAC非理想性对DDS输出杂散谱的影响。最后进行计算机仿真分析并验证了结论。所得规律性结论为DDS设计和工程应用开发中的参数选取、杂散评估和杂散抑制提供重要的理论依据和经验参考。