Turbo码交织方式探讨

交织器是Turbo码中一个比较重要的部分。通过适当的交织器,可以在不改变Turbo码输入序列码重的情况下增加输出序列的自由距。这也正是Turbo码具有良好性能的来源。本文重点对块交织算法进行了一些探讨。并在两种不同块交织方式、短分组序列的情况下,用计算机Turbo码译码性能进行了仿真,模拟出信噪比-误比特率曲线。     

一种适合于并行译码的Turbo交织器的设计

高数据率的通信系统要求有高吞吐量的译码器,而并行译码是高吞吐量的译码器的一种有效实现方法。对于采用并行译码的Turbo码,交织器的设计是决定其性能和译码器吞吐量的关键因素。本文在A.Giuliett提出的没有读写冲突的并行交织器的设计原则基础上,给出了一种新型的交织器设计方法。该方法在保证Turbo优越性能的前提下,使得高并行度的译码成为可能。译码性能的仿真结果验证了设计方案的良好译码性能,通过FPGA的硬件实现验证了译码器吞吐量的极大提高。该设计方案可用于Beyond3G系统。     

一种低存储容量Turbo码译码器结构设计及FPGA实现

为满足高性能低功耗无线通信的要求,基于反向重算和线性估算的Turbo码译码器结构,通过改变其前向状态度量的存储方式,提出了一种低存储容量的低功耗译码器结构设计方案,并给出了FPGA实现结构。结果表明,与已有的Turbo码译码器结构相比,本设计的译码器结构使存储容量降低了65%,译码性能与Log-MAP算法接近;并且在25 MHz、50 MHz、75 MHz、100 MHz、125 MHz频率下,较传统的译码器结构相比,动态的存储容量功耗均下降50%左右,而总功耗分别降低了4. 97%、 8. 78%、 11. 93%、 14. 18%、 14. 65%。     

Turbo码快速交织算法的性能仿真及其FPGA实现

针对目前交织器存在的时延大的缺陷,设计了一种基于短时延伪随机序列的Turbo码快速交织算法,给出了基于FPGA的硬件实现方案,在时延和性能之间取得较好的折衷。仿真结果表明,该交织算法在不增加Turbo码编译码复杂度的情况下,一次迭代过程交织模块即能减少20%的时间延迟。     

利用CMOS模拟电路设计实现的新型概率译码器

利用CMOS模拟电路设计了模拟概率计算模块,并以此为基础,通过晶体管级的模拟电路设计,构造了(5,2,3)网格码完整的新型模拟概率译码器,给出了模拟译码器的译码性能.当信噪比大于4.8 dB时,对于950 kHz的输入信号,输出没有错误.当输入信号为6 MHz时,误码率约为10-4.在5 V工作条件下,译码器功耗为2.957mw.测试结果表明,在速度一定的条件下,与采用数字电路实现的译码器相比,该模拟译码器的功耗和芯片面积至少减少了一个数量级.该设计方法适用于实现网格码、Turbo码以及LDPC码等的模拟译码器.     

高性能QC-LDPC码译码器的VLSI实现

基于改进的最小和（Min-Sum）译码算法,提出一种高速半并行准循环低密度奇偶校验（QC-LDPC）码译码器结构．设计了对数桶型移位器来传递数据,以降低译码器内部连线的复杂度;引入微指令控制技术,使译码器的硬件结构独立于具体的码率和码的规则性,可以在不改变硬件的情况下支持任意码率;采用动态功耗管理技术,译码器可以随信道好坏自动控制功耗．基于该结构实现了一个适合中国数字电视地面传输标准（GB20600-2006）系统的LDPC码译码器,在SMIC0．18μm标准CMOS工艺下综合,总面积仅为62万等效门,频率最高可达100MHz．     

基于C语言的Turbo码的DSP实现

介绍了Turbo码的编译码基本原理,在详细研究Log-MAP算法的基础上,用V05．0编写了状态转移表生成子程序,Turbo交织表生成子程序和Turbo码译码程序等几个对Turbo码进行仿真最重要的函数,并在DSP上实现了通用的Turbo码编译码器。     

吉比特里所码和卷积码级联译码器设计

针对60-GHz无线个域网,提出了一种吉比特里所码和卷积码级联译码器架构。在推荐级联架构中,里所码和卷积码分别作为外码和内码,通过交织器级联。采用基于Viterbi算法的8路并行卷积译码结构和基于RiBM算法的里所码译码结构,实现了超高速级联译码器。在TSMC 0.13μm CMOS工艺下,该译码器以0.135 nJ/bit和5.19 mm2的能耗资源开销实现了高达2 Gb/s的吞吐率。     

Turbo简化译码算法的FPGA设计与实现

在深入分析Turbo译码算法的基础上,采用MAX-LOG-MAP算法进行了Turbo码译码器的FPGA设计与实现,并给出相应实现参数和结构。对FPGA的实现与MATLAB浮点算法做了仿真比较。     

基于FPGA的改进型分组交织器的设计与实现

本文分析了交织器在Turbo码中的重要作用,以及分组交织器存在的缺陷,提出了一种改近型分组交织器的设计与实现方法.该交织器具有算法简单、易于实现、可适应不同数据帧长度传输要求的优点.设计采用Ahera公司生产的Cyclone系列器件,利用其片内RAM实现,并基于Quartus II软件平台进行了仿真验证.     

Design and implementation of motion compensator in memory reduced HDTV decoder with embedded compression engine

In this paper, a low-cost compatible motion compensator is implemented and integrated into a macroblock-level three-stage-pipelined HDTV decoder, in which an embedded compression (EC) engine is realized as well. The decoder with EC engine is designed to reduce the power consumption and memory bandwidth requirement since memory accesses are reduced. In the motion compensator, a boundary judgment scheme for reference pixel fetching is proposed to provide seamless integration in HDTV video decoder for the block-based EC engines. Furthermore, a buffer sharing mechanism is adopted to reduce extra memory requirement involved by EC. The reference pixel fetching unit costs only 17.3 K logic gates when the working frequency is set to 166.7 MHz. On average, when decoding HD1080 video sequence, 30% memory access reduction and 24% memory power consumption saving are achieved when a near lossless EC algorithm is integrated in the video decoder. In other words, the proposed motion compensator makes the EC engine an integral part of a memory reduced decoder without extra cost. Additionally, since the work in this paper is based on EC schemes, the EC design criterion are discussed, and several useful rules on the selection of EC algorithm are addressed for the video decoder of corresponding VLSI architecture.     

基于TDMP优化算法的QC-LDPC译码器VLSI实现

在对TDMP算法优化的基础上,提出了一种LDPC译码器VLSI架构和实现方法.与目前已经存在的LDPC译码器相比,这种实现方法的优势主要有:1)能够实现快速收敛,将译码迭代次数降低为经典方法的50%以下,进而降低功耗;2)用于存储中间置信信息的存储器使用量比传统方法减少50%以上,大大减少芯片面积;3)校验节点置信度更新采用归一化Min-Sum算法(NMS),降低计算复杂度,选取的校正因子保证了译码器的BER性能;4)充分利用校验矩阵的准循环特点,实现规整的芯片内部互连线,减小布线难度.用这种架构实现了符合中国数字电视地面传输标准(DTMB)的LDPC译码器:融合3种码率;芯片规模为58万门;时钟频率为100 MHz,数据吞吐率为107 Mbps.     

数据不规则问题全相关Block递归方程组多维流水线并行技术研究

主要讨论数据不规则问题全相关Block递归方程组多维流水线并行的实现.首先给出全相关Block递归方程组的模型方程,并从图论的角度给出了流水关系有向图的定义以及流水线并行条件的判别准则,分析了影响流水线并行效率的主要因素.在此基础上,提出一种基于流水关系有向图的流水线并行实现算法并应用于数据不规则问题.实验结果表明该方法在复杂区域情况下也可以取得较高的效率.     

采用并行分层译码的LDPC译码器设计研究

基于并行分层译码算法的LDPC译码器可以使用较小的芯片面积实现较高的译码速率。提出一种基于该算法的译码器硬件设计方法。该设计方法通过使用移位寄存器链,来进一步降低基于并行分层译码算法的译码器芯片面积。该硬件设计使用TSMC 65 nm工艺实现,并在实现中使用IEEE 802.16e中的1/2码率LDPC码。该译码器设计在迭代次数设置为10次时可实现1.2 Gb/s的译码速率,芯片面积1.1 mm2。译码器设计通过打孔产生1/2至1之间的连续码率。     

Faster optimal parallel prefix circuits: New algorithmic construction

Parallel prefix circuits are parallel prefix algorithms on the combinational circuit model. A prefix circuit with n inputs is depth-size optimal if its depth plus size equals 2n-2. Smaller depth implies faster computation, while smaller size implies less power consumption, less VLSI area, and less cost. To be of practical use, the depth and fan-out of a depth-size optimal prefix circuit should be small. A circuit with a smaller fan-out is in general faster and occupies less VLSI area. In this paper, we present a new algorithm to design parallel prefix circuits, and construct a class of depth-size optimal parallel prefix circuits, named SU4, with fan-out 4. When n30, SU4 has the smallest depth among all known depth-size optimal prefix circuits with fan-out 4.     

Recursive identification of Hammerstein systems with application to electrically stimulated muscle

Modeling of electrically stimulated muscle is considered in this paper where a Hammerstein structure is selected to represent the isometric response. Motivated by the slowly time-varying properties of the muscle system, recursive identification of Hammerstein structures is investigated. A recursive algorithm is then developed to address limitations in the approaches currently available. The linear and nonlinear parameters are separated and estimated recursively in a parallel manner, with each updating algorithm using the most up-to-date estimation produced by the other algorithm at each time instant. Hence the procedure is termed the alternately recursive least square (ARLS) algorithm. When compared with the leading approach in this application area, ARLS exhibits superior performance in both numerical simulations and experimental tests with electrically stimulated muscle.     

RA码交织器的研究与设计

重复累积码(Repeat Accumulate Code,简称RA码)综合了Turbo码和LDPC码的优点,可以进行线性时间的编码及译码,成为了近年来信道编码技术研究的热点。为了改善重复累积码的性能,对其交织器进行优化设计。在几种常见的交织器的基础上提出了奇偶分组交织器的设计方法,并在AWGN信道下基于BP译码算法完成性能分析。仿真结果表明,奇偶分组交织器优于分组交织器,大大降低了信息序列之间的相关性,同时避免了校验矩阵中两类四环的产生,可以提高信息在信道中传输的可靠性。     

A hardware oriented fuzzification algorithm and its VLSI implementation

An efficient fuzzification algorithm named as Dynamic Precision Fuzzification (DPF) is introduced in this paper which is mainly developed for hardware implementation. The DPF which might be generally used with any piecewise linear membership function, exploits an inherent capacity of the normal fuzzification algorithm to improve its efficiency when realized in a finite-precision implementation bed such as digital VLSI. The accuracy simulation results of the DPF and normal fuzzification method are presented and compared to show the superiority of the DPF. As the word-length is the most important parameter in a finite-precision implementation environment which determines the system cost-precision trade-off, the simulation results show that DPF provides suitable precision improvements with respect to traditional fuzzification without increasing the system word-length. The VLSI synthesis results of both methods are also presented to show that this considerable accuracy improvement is achieved by an acceptable increase in its VLSI implementation costs in terms of area, delay, and power consumption with respect to traditional methods.