1.5V BiCMOS dynamic multiplier using Wallace tree reduction architecture

A 1.5V BiCMOS dynamic multiplier is presented which is free from race and charge sharing problems, using Wallace tree reduction architecture and a 1.5V full-swing BiCMOS dynamic logic circuit. Based on a 1 mu m BiCMOS technology, a designed 1.5V 8*8 multiplier shows a *2.3 improvement in speed as compared to the CMOS static multiplier.<>     

Design of a 1.5 V full-swing bootstrapped BiCMOS logic circuit

A low voltage full-swing BiCMOS bootstrapping technique that allows the design of BiCMOS logic circuits at supply voltages down to 1.5 V is presented. This is the first 1.5-V design technique that does not require complementary bipolar devices. The technique is shown to have significant advantages over existing low voltage BiCMOS logic designs in sub-3 V operation. Inverter gates fabricated using a 0.8-μm technology were operated at 150 MHz with a supply voltage of 1.5 V. Implementation of this technique on dynamic logic is also demonstrated and experimental results match closely with simulation     

A 100-MHz 4-mW four-quadrant BiCMOS analog multiplier

A four-quadrant analog multiplier based on a simple, very linear, and fast BiCMOS transconductor using MOS transistors operating in the triode region and NPN bipolar devices is presented. The four quadrant operation is obtained by crosscoupling-in a Gilbert-cell fashion-two transconductors with a third stage used to modulate the transconductances of the former two. A chip prototype of the multiplier has been integrated in a 1.2-μm BiCMOS process to validate the idea. It has been designed to achieve high linearity on both inputs: measured results show a total harmonic distortion (THD) of less than -40 dB with a 3-V peak-to-peak input signal at 5 MHz from a 5-V supply and an output -3 dB bandwidth of 100 MHz while dissipating 4 mW from a 3-V supply. The integrated chip prototype active area is 1 mm²     

Low-voltage BiCMOS dynamic minimum circuit using a parallelcomparison algorithm for fuzzy controllers

The authors present a low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for VLSI implementation of fuzzy controllers. Using low-voltage BiCMOS dynamic circuits and a parallel comparison algorithm, a four-4-bit-input minimum circuit designed, based on a 1μm BiCMOS technology, shows a 9.5ns comparison time, which is a ×2.5 improvement in speed as compared to that based on CMOS technology     

A 1.5 V full-swing BiCMOS dynamic logic gate circuit suitable forVLSI using low-voltage BiCMOS technology

This paper presents a 1.5 V full-swing BiCMOS dynamic logic gate circuit, based on a dynamic pull-down BiPMOS configuration, suitable for VLSI using low-voltage BiCMOS technology. With an output load of 0.2 pf, the 1.5 V full-swing BiCMOS dynamic logic gate circuit shows a more than 1.8 times improvement in speed as compared to the CMOS static one     

A 1.5-V full-swing BiCMOS logic circuit

A BiCMOS logic circuit applicable to sub-2-V digital circuits has been developed. A transiently saturated full-swing BiCMOS (TS-FS-BiCMOS) logic circuit operates twice as fast as CMOS at 1.5-V supply. A newly developed transient-saturation technique, with which bipolar transistors saturate only during switching periods, is the key to sub-2-V operation because a high-speed full-swing operation is achieved to remove the voltage loss due to the base-emitter turn-on voltage. Both small load dependence and small fan-in dependence of gate delay time are attained with this technique. A two-input gate fabricated with 0.3-μm BiCMOS technology verifies the performance advantage of TS-FS-BiCMOS over other BiCMOS circuits and CMOS at sub 2-V supply     

An analytical transient model for a 1.5 V BiCMOS dynamic logiccircuit for low-voltage deep submicrometer BiCMOS VLSI

This paper presents an analytical transient model for the 1.5 V BiCMOS dynamic logic circuit using Gummel-Poon charge control model for deep submicrometer BiCMOS VLSI. Based on the analysis, the switching time of the 1.5 V BiCMOS dynamic circuit is sensitive to the forward transit time with a large load capacitance. With a small load capacitance, its switching time is related to the threshold voltage     

A 200-MHz 15-mW BiCMOS sample-and-hold amplifier with 3 V supply

A sample-and-hold amplifier designed for the front end of high-speed low-power analog-to-digital converters employs a BiCMOS sampling switch and a low-voltage amplifier to achieve a sampling rate of 200 MHz while allowing input/output voltage swings of 1.5 V with a 3-V supply. The circuit also incorporates a cancellation technique to relax the trade-off between the hold-mode feedthrough and the sampling speed. Fabricated in a 20-GHz 1-μm BiCMOS technology, an experimental prototype exhibits a harmonic distortion of -65 dB with a 10-MHz analog input and occupies an area of 220×150 μm². The measured feedthrough is -52 dB for a 50-MHz analog input and the droop rate is 40 μV/ns     

Low-voltage dynamic BiCMOS CLA circuit with carry skip using novelfull-swing logic

This paper presents novel low-voltage dynamic BiCMOS logic gates and an improved carry look-ahead (CLA) circuit with carry skip using these new dynamic BiCMOS topologies. The well-known “MOS clock feedthrough effect” is used to achieve full swing with substantially reduced low-to-high evaluation delay in the logic gates, thus, resulting in reduced carry propagation/bypass delay in the cascaded CLA array. Simulations at clocking frequency of 100 MHz, using 2-μm BiCMOS process parameters and supply voltage in the range of 2-4 V displays lower gate delay and lower power dissipation compared to other recent dynamic BiCMOS logic topologies. The circuit has no dc power dissipation, race, or charge redistribution problems. An 8-b CLA with 5-b carry skip was achieved in 2.917 ns. This speed is significantly higher than other recent dynamic BiCMOS CLA designs. In addition, the new CLA circuit is more compact compared to previous dynamic BiCMOS CLA designs. A tiny chip was fabricated using the MOSIS Orbit Analog 2-μm V-well CMOS process for the experimental verification of the new low-voltage dynamic BiCMOS topologies     

A high performance 0.35-μm 3.3-V BiCMOS technology optimized forproduct porting from a 0.6-μm 3.3-V BiCMOS technology

A 0.35-μm logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5-V version offers lower power and higher performance. A 3.3-V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6-μm 3.3-V BiCMOS process. A two-step design process for converting an existing production worthy 0.6-μm 3.3-V BiCMOS design to a 0.35-μm design is described. The silicon results are described     

Level-shifted 0.5-μm BiCMOS circuits

A circuit concept, level shifting, is presented for scaled BiCMOS circuits. A full-swing, ground-level-shifted (FS-GLS) BiCMOS circuit has shown approximately 1.6× speed improvement over a conventional partial-swing BiCMOS circuit, and a 4× better driving capability over a CMOS circuit at 3.3 V. With a high-performance p-n-p device, simulations show that the level-shifted complementary BiCMOS can provide further speed leverage over the BiCMOS circuit with n-p-n only     

Low-Voltage BiCMOS Four-Quadrant Multiplier and Squarer

A new low-voltage low-power BiCMOS four-quadrant multiplier using cascode NPN and NMOS pairs is presented. This circuit has been fabricated in a 1 m BiCMOS process. Experimental results show that for a power supply of ±1.5 V, the linear range is over ±0.8 V with the linearity error less than 2%. The total harmonic distortion is less than 2% with input range up to ±0.8 V. The measured –3 dB bandwidth of the proposed multiplier is about 10 MHz. Its static power dissipation is about 50 W. The squarer modified from the proposed multiplier has the input range up to ±1 V. This circuit is expected to be useful in low-voltage analog signal processing applications.     

Monolithic magnetic Hall sensor using dynamic quadrature offsetcancellation

The offset voltage and its temperature drift and production spread, which generally degrades the zero-level stability and reproducibility of magnetic Hall sensors, can be reduced using a single Hall plate and switching means for periodic permutation of the supply and output contact pairs. The present work describes a chopper-based 5-V monolithic linear Hall sensor with a ±0.1 T full scale where this dynamic plate offset cancellation technique has been employed together with a cost-effective signal conditioner. The device was integrated using a 2-μm conventional BiCMOS process and the final chip, measuring 15×1.5 mm², shows, after packaging in a 3-pin plastic package, a residual offset with a production spread and a temperature-induced drift five to ten times smaller than in currently used multiplate dc quadrature cancellation approaches. The device does not require external components and provides an output free of HF residues     

A new true-single-phase-clocking BiCMOS dynamic pipelined logicfamily for high-speed, low-voltage pipelined system applications

New true-single-phase-clocking (TSPC) BiCMOS/BiNMOS/BiPMOS dynamic logic circuits and BiCMOS/BiNMOS dynamic latch logic circuits for high-speed dynamic pipelined system applications are proposed and analyzed. In the proposed circuits, the bootstrapping technique is utilized to achieve fast near-full-swing operation. The circuit performance of the proposed new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications are simulated by using HSPICE with 1 μm BiCMOS technology. Simulation results have shown that the new dynamic logic circuits and dynamic latch logic circuits in both domino and pipelined applications have better speed performance than that of CMOS and other BiCMOS dynamic logic circuits as the supply voltage is scaled down to 2 V. The operating frequency and power dissipation/MHz of the pipelined system, which is constructed by the new clock-high-evaluate-BiCMOS dynamic latch logic circuit and clock-low-evaluate-BiCMOS (BiNMOS) dynamic latch logic circuit, and the logic units with two stacked MOS transistors, are about 2.36 (2.2) times and 1.15 (1.1) times those of the CMOS TSPC dynamic logic under 1.5-pF output loading at 2 V, respectively. Moreover, the chip area of these two BiCMOS pipelined systems is about 1.9 times and 1.7 times as compared with that of the CMOS TSPC pipelined system. A two-input dynamic AND gate fabricated with 1 μm BiCMOS technology verifies the speed advantage of the new BiNMOS dynamic logic circuit. Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed new dynamic logic circuits and dynamic latch logic circuits are feasible for high-speed, low-voltage dynamic pipelined system applications     

Merged BiCMOS logic to extend the CMOS/BiCMOS performance crossoverbelow 2.5-V supply

The authors discuss the merged BiCMOS (MBiCMOS) gate, a unique circuit configuration to improve BiCMOS gate performance at low supply voltages. MBiCMOS maintains a measured delay and power-delay advantage over CMOS into the 2-V supply range, in a simple four-device gate that does not require any change in the standard BiCMOS processing sequence. In a 2-μm technology, MBiCMOS outperforms CMOS down to a 2.6-V supply. Gates designed for fabrication in a 0.5-μm technology and simulated using measured device parameters indicate that MBiCMOS can be used to extend the performance crossover voltage to below 2 V in the submicrometer regime. A full-swing version of the MBiCMOS gate (FS-MBiCMOS) is introduced. Simulations of 2-μm gates show FS-MBiCMOS/CMOS performance crossover voltages of 2.2 V     

New full-voltage-swing BiCMOS buffers

Circuit techniques are presented for increasing the voltage swing of BiCMOS buffers through active charging and discharging using complementary bipolar drivers. These BiCMOS circuits offer near rail-to-rail output voltage swing, higher noise margins, and higher speed of operation at scaled-down power supply voltages. The circuits are simulated and compared to BiCMOS and CMOS buffers. The comparison shows that the conventional BiCMOS and the complementary BiCMOS buffers are efficient for power supply voltages greater than 3V and that if the power supply voltage is scaled down (<3 V) and the load capacitance is large (>1 pF), the complementary BiCMOS buffers would be the most suitable choice. They provide high speed and low delay to load sensitivity and high noise margins. The first implementation is favorable near a 2.5-V power supply for its smaller area     

A BiCMOS continuous-time filter for video signal processingapplications

A fully integrated BiCMOS continuous-time filter for video signal processing applications is presented. It incorporates an input clamping circuit, a third-order equalizer, a fifth-order elliptic filter with sinx/x correction, and a 75-Ω driver. The architectures of the input and output amplifiers as well as the filter and the equalizer are chosen based on the extensive study of circuit structures and Monte Carlo simulation to meet the linearity requirement for the broadcast-quality video system. The complete chip achieves a low-pass filter response with a 5.5-MHz cutoff frequency (f_cc), 0.3-dB passband ripple, 20-ns group delay variation up to 0.9 f_c, and 43-dB attenuation at 1.45 f_c. With a nominal 2-Vpp signal at the output, measured results show 0.2% differential gain, 0.38° differential phase, and 1.7-mV rms noise demonstrating 10-bit linearity in a 1.5-μm 4-GHz BiCMOS process technology. The filter active area is 8 mm² and it dissipates 350 mW in a single 5-V power supply     

A single-power-supply 10-b video BiCMOS sample-and-hold IC

A +5-V single-power-supply 10-b video BiCMOS sample-and-hold IC is described. Video speed, low power, and 10-b accuracy sample-and-hold operation have been achieved using a complementary connected buffer format sample switch. A high-speed p-n-p transistor used in the sample switch is formed by a combination of n-p-n and PMOS transistors. The sample-and-hold operation is accomplished by feeding back the hold capacitor voltage to the sample switch inputs, so that the inputs transfer symmetrically for the hold capacitor voltage at any input level. The sample-and-hold IC has been implemented in 1.2-μm BiCMOS technology and evaluated. The following results have been obtained: 185-MHz 3-dB bandwidth at 22-pF hold capacitor, 63-dB signal-to-noise ratio at 8-MHz full-scale input, 20-ns acquisition time at 1-V step input, 15-ns switch setting time, and 0.1% linearity error. Power dissipation is 150 mW     

A 10-bit video BiCMOS track-and-hold amplifier

A 1.2-μm VLSI BiCMOS technology has been used to implement a monolithic video track-and-hold amplifier that settles to an accuracy of 10 b in 15 ns. This level of performance is competitive with hybrid track-and-hold circuits and surpasses previously reported monolithic implementations by nearly two orders of magnitude. The amplifier's design is based on a closed-loop topology incorporating two BiCMOS folded-cascode gain stages, an NMOS sampling switch, and a BiCMOS switch driver with 1-ns transitions between ±4 V. The circuit operates from ±5-V power supplies and is capable of driving a 50-Ω load with ±1-V swings. For a fully differential implementation, the power dissipation is 1.2 W. The amplifier can be integrated either as a stand-alone track-and-hold circuit or as the front end of an analog-to-digital conversion system for video and high-speed instrumentation applications     

一种低压BiCMOS四象限模拟乘法器的设计

提出了一种结构简单的采用 Bi CMOS线性区跨导和输入预处理电路的低压 Bi CMOS四象限模拟乘法器 ,详细分析了电路的结构和设计原理。设计采用典型的 1.2 μm Bi CMOS工艺 ,并给出了电路的 SPICE模拟结果。模拟结果表明 ,当电源电压为± 3V时 ,功耗小于 2 .5m W,线性输入电压范围大约± 2 V。当输入电压范围限于± 1.6 V时 ,总谐波失真和非线性误差均小于0 .8% ,- 3d B带宽大于 110 MHz。