A high performance 0.35-μm 3.3-V BiCMOS technology optimized forproduct porting from a 0.6-μm 3.3-V BiCMOS technology

A 0.35-μm logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5-V version offers lower power and higher performance. A 3.3-V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6-μm 3.3-V BiCMOS process. A two-step design process for converting an existing production worthy 0.6-μm 3.3-V BiCMOS design to a 0.35-μm design is described. The silicon results are described     

A 10 K-gate 950 MHz CML demonstrator circuit made with a 1-μmtrench-isolated bipolar silicon technology

A quad 512-b static shift register consuming 1.8 mW/stage designed to demonstrate the capabilities of an advanced bipolar silicon technology is discussed. The process uses 1-μm lithography, trench isolation, polyemitter transistors, polysilicon resistors, and polycide layer for local interconnections. This VLSI circuit (over 35 K transistors, 86-mm² chip) has been implemented on a sea-of-cells structure. An appropriate scheme has been used for the clock distribution. The experimental results show operation at a clock frequency up to 950 MHz     

A 2-μm BiCMOS process utilizing selective epitaxy

A 2-μm BiCMOS process designed for 10-V analog/digital applications is described. This process utilizes selective epitaxial growth to integrate a vertical n-p-n bipolar structure with an estimated cutoff frequency of 5 GHz and nonoptimized vertical p-n-p structure into a 2-μm CMOS process with a poly-to-n⁺ capacitors. The insertion of the bipolar structures is accomplished with only two added masking steps and with no change to the critical process parameters which determine the performance of the MOS transistors     

Breakdown voltage enhancement for devices on thin siliconlayer/silicon dioxide film

Studies of high-voltage lateral device structures on a thin silicon layer over silicon dioxide have been carried out. It was found both theoretically and experimentally that over 600-V devices can be realized using a structure consisting of an n diffusion layer over a 15-μm-thick high-resistivity n^- silicon layer over 3-μm silicon dioxide (SOI). A method is presented to enhance breakdown voltage by applying a large share of the voltage to the bottom oxide     

A BiCMOS process utilizing selective epitaxy for analog/digitalapplications

A 2-μm BiCMOS process that has been designed for 10-V analog/digital applications is described. This process utilizes selective epitaxial growth to integrate a vertical n-p-n bipolar with an f_T of 3.0 GHz, and a nonoptimized vertical p-n-p structure into a 2-μm CMOS process with poly-to-n⁺ capacitors. The insertion of the bipolar structures is accomplished with only two added masking steps, and with no changes to the critical process parameters that determine the performance of the MOS transistors. The circuit worthiness of the process is demonstrated by fabricating CMOS, vertical n-p-n RTL, and vertical p-n-p RTL ring oscillators, and demonstrating high yields for these circuits     

A low-power 15-GHz frequency divider in a 0.8-μm silicon bipolartechnology

In this paper, we present a low-power static frequency divider with a divide ratio of eight. It operates up to 15 GHz, consuming only 22 mA from a 3.6-V supply. The chip is manufactured in a 0.8-μm silicon bipolar production technology with a cutoff frequency of 25 GHz. The circuit has a single-ended input and output and is mounted in a six-pin SOT363 plastic package     

A comparison of GaAs HJBT and silicon bipolar technologies forhigh-speed analog-to-digital converters

The potential using the emerging GaAlAs/GaAs heterojunction bipolar transistor (HJBT) technology is all-parallel analog-to-digital (A/D) converters is studied. To put into perspective the HJBT predictions made, a comparison of the ultimate performance levels achievable with contemporary silicon bipolar processes is given. Optimized latched compensators were developed for each technology and simulations on SPICE were carried out to determine the maximum sample rate and large-signal analog bandwidths that would be achieved. As both technologies are produced in-house, models were available for processors in the latter stages of development, namely the standard 1-μm silicon bipolar process, and the 4-μm HJBT process, as well as processes at an earlier stage of development, the enhanced 1-μm silicon bipolar processes and the 2.5-μm HJBT process. This enabled the trend of performance improvements with time to be compared     

A 1.5-V full-swing BiCMOS logic circuit

A BiCMOS logic circuit applicable to sub-2-V digital circuits has been developed. A transiently saturated full-swing BiCMOS (TS-FS-BiCMOS) logic circuit operates twice as fast as CMOS at 1.5-V supply. A newly developed transient-saturation technique, with which bipolar transistors saturate only during switching periods, is the key to sub-2-V operation because a high-speed full-swing operation is achieved to remove the voltage loss due to the base-emitter turn-on voltage. Both small load dependence and small fan-in dependence of gate delay time are attained with this technique. A two-input gate fabricated with 0.3-μm BiCMOS technology verifies the performance advantage of TS-FS-BiCMOS over other BiCMOS circuits and CMOS at sub 2-V supply     

A high-speed complementary silicon bipolar technology with 12-fJpower-delay product

A complementary silicon bipolar technology offering a substantial improvement in power-delay performance over conventional n-p-n-only bipolar technology is demonstrated. High-speed n-p-n and p-n-p double-polysilicon, self-aligned transistors were fabricated in a 20-mask-count integrated process using an experimental test site designed specifically for complementary bipolar applications. N-p-n and p-n-p transistors with 0.50-μm emitter widths have cutoff frequencies of 50 GHz and 13 GHz, respectively. Two novel complementary bipolar circuits-AC-coupled complementary push-pull ECL, and NTL with complementary emitter-follower-display a significant advantage in power dissipation as well as gate delay when compared to conventional n-p-n-only ECL circuits. Record power-delay products of 34 fJ (23.2 ps at 1.48 mW) and 12 fJ (19.0 ps at 0.65 mW) were achieved for these unloaded complementary circuits, respectively. These results demonstrate the feasibility and resultant performance leverage of high-speed complementary bipolar technologies     

High-performance thin-film silicon-on-insulator CMOS transistors inporous anodized silicon

Ultrathin-film silicon-on-insulator (SOI) CMOS transistors, produced in silicon islands 100 nm thick, formed by oxidation of porous anodized silicon, are described. Both n-channel and p-channel mobilities are similar to equivalent bulk values. Subthreshold slopes are less than 80 mV/decade and junction leakages are approximately 0.1 pA/μm. No kink is seen in the output characteristics of the n-channel transistors as the silicon film is fully depleted. A ring-oscillator gate delay of 161 ps has been achieved, at a power dissipation of 270 μW/stage, for 1.5-μm gate length     

A 100-MHz 4-mW four-quadrant BiCMOS analog multiplier

A four-quadrant analog multiplier based on a simple, very linear, and fast BiCMOS transconductor using MOS transistors operating in the triode region and NPN bipolar devices is presented. The four quadrant operation is obtained by crosscoupling-in a Gilbert-cell fashion-two transconductors with a third stage used to modulate the transconductances of the former two. A chip prototype of the multiplier has been integrated in a 1.2-μm BiCMOS process to validate the idea. It has been designed to achieve high linearity on both inputs: measured results show a total harmonic distortion (THD) of less than -40 dB with a 3-V peak-to-peak input signal at 5 MHz from a 5-V supply and an output -3 dB bandwidth of 100 MHz while dissipating 4 mW from a 3-V supply. The integrated chip prototype active area is 1 mm²     

A fundamental limitation for bipolar transistor scaling

A microscopic model of minority-carrier diffusion in a heavily doped emitter is proposed. Monte Carlo simulation demonstrates that statistical fluctuation in the base current is one of the fundamental limitations in high-speed applications of scaled bipolar transistors. For the transistor presently investigated, with 5.0-μm² emitter area, 0.1-μm junction depth, 8.5-ps measurement time, and 0.75-V emitter/base bias, the base current deviation is 43%. This sets up the maximum operating frequency for the transistor. More lightly doped emitters (such as for heterojunction bipolar transistors) will relax this limitation, but at a cost of increased contact resistance, especially when poly-emitters are utilized. Increasing the emitter/base bias will also make the base current rate more deterministic, but the other limitations such as power dissipation and contact resistance will become more obvious     

A 0.25-μm, 600-MHz, 1.5-V, fully depleted SOI CMOS 64-bitmicroprocessor

A 0.25-μm, four-layer-metal, 1.5-V, 600-MHz, fully depleted (FD) silicon-on-insulator (SOI) CMOS 64-bit ALPHA1 microprocessor integrating 9.66 million transistors on a 209-mm² silicon die has been developed leveraging the existing bulk design. FD-SOI technology is used because it has better immunity for dynamic leakage current than partially depleted SOI in high speed dynamic circuits without body contact. C-V characteristics of metal-oxide-silicon-oxide-silicon with and without source-drain junctions are described to explain the behavior of FD-SOI transistor. Race, speed, and dynamic stability have been simulated to reassure the circuit operation. Key process features are shallow trench isolation, 4-nm gate oxide, 30-nm co-silicide, 46-nm silicon film, and 200-nm buried oxide. The FD-SOI microprocessor runs 30% faster than that of bulk, and it passes the reliability and system test     

A sub-1 mA 1.5-GHz silicon bipolar dual modulus prescaler

This paper describes a 2.7-V dual modulus (÷64/65, ÷128/129) prescaler that operates up to 1.5 GHz with a power consumption of 1.97 mW (Vcc=2.3 V, Icc=860 μA). The prescaler also incorporates a stand-by mode feature, which reduces its power dissipation to 0.12 mW when enabled. This performance has been achieved on a 0.8-μm advanced bipolar technology     

Investigation on low-voltage low-power silicon bipolar designtopology for high-speed digital circuits

This paper investigates a bipolar design topology which is suitable to operate from a voltage supply well below 1.5 V, while maintaining the ability of high frequency operation. The topology has been applied in the design of different divide-by-4 circuits, utilizing a 20-GHz 0.6-μm Si bipolar technology. The different versions featured slight modifications in the architecture of the logic cells and the influence on the frequency and supply voltage range of operation has been investigated. Measurements have shown operation from 1.0-V supply voltage and up to 4.2-GHz input frequency to 1.5 V and up to 6 GHz. The power consumption is approximately 0.3 mW/latch and 1.2 mW/latch, respectively     

A 130-mm2, 256-Mbit NAND flash with shallow trenchisolation technology

A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 μm is achieved with 0.25-μm STI. The memory cell is shrunk to 0.29 μm², which realizes a 130-mm² , 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-μs first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 μs. That realizes 4.4-Mbyte/s programming throughput     

Amorphous silicon thin-film transistors on compliant polyimide foilsubstrates

Much of the mechanical strain in semiconductor devices can be relieved when they are made on compliant substrates. We demonstrate this strain relief with amorphous silicon thin-film transistors made on 25-μm thick polyimide foil, which can be bent to radii of curvature R down to 0.5 mm without substantial change in electrical characteristics     

Large suspended inductors on silicon and their use in a 2-μmCMOS RF amplifier

Large spiral inductors encased in oxide over silicon are shown to operate beyond the UHF band when the capacitance and loss resistance are greatly reduced by selective removal of the underlying substrate. Using a 100-nH inductor whose self-resonance lies at 3 GHz, a balanced tuned amplifier with a gain of 14 dB centered at 770 MHz has been implemented in a standard digital 2-μm CMOS IC process. The core amplifier noise figure is 6 dB, and the power dissipation is 7 mW for a 3-V supply     

A low cost and low power silicon npn bipolar process with NMOS transistors (ADRF) for RF and microwave applications

A silicon bipolar process for RF and microwave applications, which features 25-GHz double-polysilicon self-aligned npn bipolar transistors with 5.5-V BV/sub CEO/, optional 0.7-/spl mu/m (L/sub eff/) NMOS transistors with p/sup +/ polysilicon gates for switch applications, lateral pnp transistors, high and low valued resistors, p/sup +/ polysilicon-to-n/sup +/ plug capacitors, and inductors is described. The npn transistors utilize nitride-oxide composite spacers formed using sacrificial TEOS spacers, a process which is simpler than the previously reported composite spacer processes. Use of the composite spacer structure virtually eliminates problems relating to the extrinsic-intrinsic base link-up and reduces plasma induced damage associated with the conventional spacer process. Microwave and RF capabilities of the process up to several GHz are demonstrated by fabricating and characterizing RF amplifiers, low noise amplifiers, and RF switches.<>     

Performance limitations of silicon bipolar transistors

The author considers some performance limitations of silicon bipolar transistors, assuming our ability to fabricate small geometric devices, by device analysis using an accurate two-dimensional numerical solution of classic semiconductor transport equations. The applicability of mathematical equations used to represent carrier transport in small geometric bipolar transistors and silicon-material parameters, such as bandgap narrowing with doping, ionization coefficients, and lifetime, used in the model has also been considered. The terminal characteristics, the internal behaviour, and performance limitations due to voltage and current operating levels of bipolar transistors with emitter depths and basewidths ranging from 0.4 /spl mu/m to 30 nm have been analyzed.