分级的混合模式布局算法

针对混合模式的布局问题提出一种分级的自动布局算法.所谓混合模式就是标准单元和宏模块相结合的布局模式.该算法在模块级和单元级两个层次上完成布局.在模块级上,首先将所有随机单元划分成若干软模块,然后采用基于序列对(sequence pair,简称SP)的方法完成模块布局;在单元级上,首先对每个软模块内部采用二次规划的布局算法进行布局,然后在全芯片范围内对布局进行改善,最后采用一种基于最小割(min-cut)和枚举相结合的快速详细布局算法完成最终布局.在一组标准单元数和宏模块数不同的电路上对该算法进行了验证,效果是令人满意的.     

Research in Design Automation for VLSI Layout

Since Japanese R&D efforts began in the late 1960s, advances in LSI circuit design automation have made possible the design of custom logic VLSI circuits with up to 10,000 gates. Automatic placement and routing programs have become essential DA tools in both master-slice LSI circuit design, and the custom design of VLSI circuits with up to 100,000 gates. Algorithms for VLSI DA systems include automatic floor planning, automatic cell placement, and automatic routing. Hierarchical design is an efficient approach to the layour of huge numbers of transistors; a VLSI circuit with 74,000 transistors and 17,000 gates was designed using such an approach. The layout design effort required less than 10 man-months, and the chip was fabricated with no error on the first design.     

Corner block list representation and its application with boundary constraints

Floorplanning is a critical phase in physical design of VLSI circuits. The stochastic optimization method is widely used to handle this NP-hard problem. The key to the floorplanning algorithm based on stochastic optimization is to encode the floorplan structure properly. In this paper, corner block list (CBL)-a new efficient topological representation for non-slicing floorplan-is proposed with applications to VLSI floorplan. Given a corner block list, it takes only linear time to construct the floorplan. In floorplanning of typical VLSI design, some blocks are required to satisfy some constraints in the final packing. Boundary constraint is one kind of those constraints to pack some blocks along the pre-specified boundaries of the final chip so that the blocks are easier to be connected to certain I/O pads. We implement the boundary constraint algorithm for general floorplan by extending CBL. Our contribution is to find the necessary and sufficient characterization of the blocks along the boundary repre     

A methodology for custom VLSI layout

In this paper, we present a new methodology for custom VLSI layout which aims at a low turnaround time and a high quality of design. VLSI circuits are highly complex, and to speed up the design process we exploit the hierarchical structure of a design, splitting the problem domain into several levels. The process of layout at each level is divided into steps such as placement of rectangular blocks, determining block dimensions, determining interconnection paths, etc. In order to obtain high quailty, designs, we have systematically analyzed the relationship among the parameters being computed at various steps and have accordingly organized the flow of data and control through these steps. There are two novel features in our scheme. First, we do not follow the usual pure top-down or pure bottom-up approach, so as to take into account the influence of design decisions at the higher levels on design decisions made at the lower levels, as well as vice versa. For example, we determine the geometry, of a block taking into consideration the context in which it is placed, as well as the geometries of the lower level blocks it encloses. Second, we perform a look-ahead operation when the values of some parameters are needed before they are actually deterministically computable by the process. For example, at the time of placement, the area required for routing is estimated statistically (before doing the actual routing) so that a more routable placement can be obtained, thereby avoiding some unnecessary iterations.     

SoC芯片设计方法及标准化

随着集成电路技术的迅速发展，集成电路已进入系统级芯片（SoC)设计时代，SoC芯片的集成度越来越高，单芯片上的集成度和操作频率越来越高，投放市场的时间要求越来越短，为了实现这样的SoC芯片，设计越来越依赖IP模块的重用，SoC复杂性的提高和IP模块的多样化，SoC芯片中多个厂商不同IP模块的使用，导致了IP模块可重用的许多问题，IP模块和片上总线，以及EDA工具接口的标准化，是解决IP模块标准化的很好途径，另一方面，SoC芯片设计的复杂性和嵌入软件所占比重的增加，要求更高层次的系统抽象和软硬件的协同设计，使用更流地的设计进行系统的硬件设计和更有效的系统设计方法，描述了SoC芯片设计中的IP模块可重用技术以及所存在的问题，介绍了SoC IP模块和片上总线结构的标准化，讨论了基于C／C＋＋扩展类库的系统级描述语言和基于平台的SoC设计方法。     

求解带有预放置矩形块的布局问题的启发式算法*

在超大规模集成电路设计中,一些特别重要的部件,如RAM、ROM、CPU等经常被优先放置,而其他元件则被两两互不重叠地放置在芯片的剩余区域.这类问题能被形式化为带有预放置矩形块的布局问题.基于占角和最大穴度优先的放置策略,为该问题的快速求解提供了一种高效的启发式算法.算法的高效性通过应用于标准电路MCNC得到了验证.     

Deterministic VLSI block placement algorithm using Less Flexibility First principle

In this paper,a simple while effective deterministic algorithm for solving the VLSI block placement problem is proposed considering the packing area and interconnect wiring simultaneously.The algorithm is based on a principle inspired by observations of ancient professionals in solving their similar problems.Using the so-called Less Flexibility First principle,it is tried to pack blocks with the least packing flexibility on its shape and interconnect requirement to the empty space with the least packing flexibility in a greedy manner.Experimental results demonstrate that the algorithm,though simple,is quite effective in solving the problem.The same philosophy could also be used in designing efficient heuristics for other hard problems,such as placement with preplaced modules,placement with L/T shape modules,etc.     

用Tabu Search解决基于结群的电路划分问题

电路划分是VLSI物理设计中最重要的步骤之一。本文提出了一种自底向上的结群策略，首先将具有高互连关系的电路模块进行结群，然后再将结群后的宏模块进行划分，用Tabu Search启发式算法进行求解，测试电路选择标准MCNC benchmarks，实验结果表明在解的质量相当情况下，运算时间较少。     

Efficient implementations of construction heuristics for the rectilinear block packing problem

The rectilinear block packing problem is a problem of packing a set of rectilinear blocks into a larger rectangular container, where a rectilinear block is a polygonal block whose interior angle is either 90° or 270°. There exist many applications of this problem, such as VLSI design, timber/glass cutting, and newspaper layout. In this paper, we design efficient implementations of two construction heuristics for rectilinear block packing. The proposed algorithms are tested on a series of instances, which are generated from nine benchmark instances. The computational results show that the proposed algorithms are especially efficient for large instances with repeated shapes.     

FUZZY LOGIC FOR STANDARD CELL PLACEMENT

Improved manufacturing processes and techniques have increased the level of integration and complexity of the ubiquitous silicon chip. But as design complexity grows, physical design automation becomes indispensable. At present a variety of tools are available to assist the designer in the various phases of circuit design. Tools for automatic placement of VLSI cells, in particular, have received much attention, because good placement is a key factor in achieving the demanded performance levels. In this paper, we present a new technique based on fuzzy logic for the placement of double-entry standard cells. Fuzzy logic offers a better alternative for handling uncertainty, and it models the human operator rather than the operation. Simulation results for the placement of nine test circuits are presented and compared with those of two other techniques.     

An efficient heuristic algorithm for arbitrary shaped rectilinear block packing problem

Arbitrary shaped rectilinear block packing problem is a problem of packing a series of rectilinear blocks into a larger rectangular container, where arbitrary shaped rectilinear block is a polygonal block whose interior angle is either 90° or 270°. This problem involves many industrial applications, such as VLSI design, timber cutting, textile industry and layout of newspaper. Many algorithms based on different strategies have been presented to solve it. In this paper, we proposed an efficient heuristic algorithm which is based on principles of corner-occupying action and caving degree describing the quality of packing action. The proposed algorithm is tested on six instances from literatures and the results are rather satisfying. The computational results demonstrate that the proposed algorithm is rather efficient for solving the arbitrary shaped rectilinear block packing problem.     

Fifth generation computers

Fifth generation computers are analogous to LEGO building blocks, with each block corresponding to a microcomputer and a group of blocks working together as a computer system. These computers will represent a unification of currently separate areas of research into parallel processing and into VLSI processors. Parallel processing based on data driven and demand driven computer organisations are under investigation in well over thirty laboratories in the United States, Japan and Europe. Basically, in data driven (e.g. data flow) computers the availability of operands triggers the execution of the operation to be performed on them; whereas in demand driven (e.g. reduction) computers the requirement for a result triggers the operation that will generate the value. VLSI processors exploit very large scale integration and the new simplified chip design methodology pioneered in US universities by Mead and Conway, allowing users to design their own chips. These novel VLSI processors are implementable by simple replicated cells and use extensive pipelining and multiprocessing to achieve a high performance. Examples range from a powerful image processing device configured from identical special-purpose chips, to a large parallel computer built from replicated general-purpose microcomputers. This paper outlines these topics contributing to fifth generation computers, and speculates on their effect on computing.     

一种快速准确控制复杂路径延时的方法

在深亚微米超大规模集成电路的物理设计中,为达到时序收敛经常遇到复杂路径延时的准确控制问题,提出了一种新的准确控制复杂路径延时方法,并使用布局布线工具Synopsys Astro实现。实验结果表明,该方法比传统的ECO（Engineer Change Order）精度高,收敛速度快,可广泛应用于超大规模集成电路物理设计。     

SOC设计中的浮动压焊块电源/地线网络设计和优化

随着VLSI工艺技术的发展和芯片规模的不断增加，尤其是在SOC设计中，原有的那种供电压焊块只能位于芯片边缘的确定益的模式已经不能够满足整个电路性能的需要。在很多情况下，依靠在电源线的拓扑结构确定后的线宽优化，还是无法保证在有限的布线资源下为电路提供可靠的高性能的供电需求。由此，出现了在芯片边缘上浮动放置压焊块及在芯片的顶部放置供电压焊块阵列的方法。文中提出了一种用于SOC设计中新的基于树型结构的浮动压焊块的电源／地线网络优化算法，经过MCNC电路实例测试后得到明显的优化结果。     

一种改进的VLSI电路有效布局算法

采用重心矩形约束[1]进行VLSI布局会出现以下问题：(1)布局边界的浪费,出现不可利用的小区域;(2)放置模块时可能会出现模块放置在实际有效区域内却因为重心约束成为非法放置。为了解决该问题,本文提出了一种改进文献[1]的VLSI布局启发式算法：通过设计模块的优先顺序进行合理布局,并辅助于边界矩形来解决重心矩形约束出现的问题;对模块布局放置的多个可能位置进行比较,并将其放置在优先度最高的适当区域。用Banchmark（ami33,ami49）和文献[1]的数据进行测试,结果表明新算法：（1）算法简洁高效,运行时间短;（2）布局结果明显好于文献[1]。     

基于标准单元的低功耗FIR数字滤波器VLSI实现

功耗与硅面积一样已成为芯片设计中的关键问题，尤其是在数字信号处理集成电路设计中。基于标准单元的VLSI设计是实现数字信号处理模块芯片或模块的重要方法。该文提出了一种基于标准单元的低功耗FIR滤波器多层次设计方案，其中体系结构层次采用多层流水线策略，逻辑层次将加法集成到部分积压缩中，在电路层次采用最小器件，从而在最大限度减少面积的同时降低了FIR的功耗。根据实际需求，该设计方案易于扩展和变换，可灵活应用到其它类似的滤波器设计中。实现结果表明在TSMC0.25标准单元库下FIR的功耗最多可降低20％以上。     

Solving optimization problems by parallel recombinative simulatedannealing on a parallel computer-an application to standard cellplacement in VLSI design

In this paper, parallel recombinative simulated annealing (PRSA), a hybrid method with features of simulated annealing and genetic algorithms, is examined. PRSA inherits the global convergence property from simulated annealing and the parallelism property from genetic algorithms. PRSA was implemented on a monoprocessor system as well as on a transputer. The algorithm, its parallel implementation, and its application to an NP-hard problem, namely standard cell placement in very large scale integration (VLSI) chip design, are described. PRSA was run for a large range of test cases. Since its performance depends on many parameters, the effects of parameter variations are studied in detail. Some important parameters are migration of individuals to other transputer nodes and selection strategies for constructing new populations. In comparison with simulated annealing and genetic algorithms, PRSA was found to produce better solutions.     

求解方格packing问题的启发式算法

沿着拟物与拟人的途径，本文为一类具有ＮＰ难度的方格ｐａｃｋｉｎｇ问题得到了实用的近似求解算法。以此算法为基础可以发展出一种为大规模集成电路芯片裁切工作做计算机辅助设计的高效的软件系统。     

Optimal approach on net routing for VLSI physical design based on Tabu-ant colonies modeling

To get a more efficient program for net routing design in VLSI physical design, a new mixed algorithm is presented by combining ant colonies algorithm and Tabu search algorithm for improving net routing design scheme in VLSI physical design. The models by considering different structure property such as two-terminal, multiple-terminal, multi-layers and gridless net routing are developed with introducing the proper parameters matching which can be obtained by computer experiments. The results show that the new algorithm can avoid the low convergence rate in the initial stage of basic ant colonies system. The efficiency of the Tabu-ant colonies is improved about 16.667%; meantime, the Tabu-ant colonies system can also avoid the local optimal solution effectively. It builds a basis for future work in solving multiple-terminal, multiple-layers and gridless net routing problems with high efficiency.     

Effective Memetic Algorithms for VLSI design = Genetic Algorithms + local search + multi-level clustering

Combining global and local search is a strategy used by many successful hybrid optimization approaches. Memetic Algorithms (MAs) are Evolutionary Algorithms (EAs) that apply some sort of local search to further improve the fitness of individuals in the population. Memetic Algorithms have been shown to be very effective in solving many hard combinatorial optimization problems. This paper provides a forum for identifying and exploring the key issues that affect the design and application of Memetic Algorithms. The approach combines a hierarchical design technique, Genetic Algorithms, constructive techniques and advanced local search to solve VLSI circuit layout in the form of circuit partitioning and placement. Results obtained indicate that Memetic Algorithms based on local search, clustering and good initial solutions improve solution quality on average by 35% for the VLSI circuit partitioning problem and 54% for the VLSI standard cell placement problem.