A flexible architecture for multi-view 3DTV based on uncalibrated cameras

This paper presents a novel flexible architecture for 3DTV based on multiple uncalibrated cameras. The proposed signal representation improves the interactivity of dense point-based methods, making them appropriate for modeling the scene semantics and free-viewpoint 3DTV applications. The main concern is to address the shortcomings of depth image-based 3D video systems for free-viewpoint visualization, and to provide an efficient implementation of the rendering part which is computationally intensive as well potentially determine the view quality. Novel rendering algorithms are added that specifically aim at solving the rendering artifacts, and sampling issues encountered in wide baseline extensions and arbitrary camera movements. To optimize the process, a “selective” warping technique is proposed that takes the advantage of temporal coherence to reduce the computational overhead. Performance is illustrated on challenging videos to prove the suitability and flexibility of the architecture for advanced 3DTV systems.     

View-spatial–temporal post-refinement for view synthesis in 3D video systems

Depth image based rendering is one of key techniques to realize view synthesis for three-dimensional television and free-viewpoint television, which provide high quality and immersive experiences to end viewers. However, artifacts of rendered images, including holes caused by occlusion/disclosure and boundary artifacts, may degrade the subjective and objective image quality. To handle these problems and improve the quality of rendered images, we present a novel view-spatial–temporal post-refinement method for view synthesis, in which new hole-filling and boundary artifact removal techniques are proposed. In addition, we propose an optimal reference frame selection algorithm for a better trade-off between the computational complexity and rendered image quality. Experimental results show that the proposed method can achieve a peak signal-to-noise ratio gain of 0.94 dB on average for multiview video test sequences when compared with the benchmark view synthesis reference software. In addition, the subjective quality of the rendered image is also improved.     

Design of unpunctured turbo trellis-coded modulation

In this paper, the design of newly introduced turbo encoding scheme called ‘Unpunctured Turbo Trellis-Coded Modulation’ (UTTCM) is exposed. The performance improvement of this encoding scheme is obtained by setting a design criterion for each of its components namely: the search rules of best constituent encoders’ generator polynomials, the constellation and the associated mapping. Simulation results show that the optimized UTTCM outperforms TTCM and PCTCM for all considered spectral efficiencies, and presents competitive error floors. As examples, for a spectral efficiency of 3 bits/symbol (bps), UTTCM with 8 decoding iterations outperforms TTCM by 0.05 dB at BER = 10^?4; and for a spectral efficiency of 4 bps and 6 decoding iterations, UTTCM outperforms Fragouli's PCTCM by 0.07 dB at BER = 10^?5.     

Overview of the MVC + D 3D video coding standard

3D video services are emerging in various application domains including cinema, TV broadcasting, Blu-ray discs, streaming and smartphones. A majority of the 3D video content in market is still based on stereo video, which is typically coded with the multiview video coding (MVC) extension of the Advanced Video Coding (H.264/AVC) standard or as frame-compatible stereoscopic video. However, the 3D video technologies face challenges as well as opportunities to support more demanding application scenarios, such as immersive 3D telepresence with numerous views and 3D perception adaptation for heterogeneous 3D devices and/or user preferences. The Multiview Video plus Depth (MVD) format enables depth-image-based rendering (DIBR) of additional viewpoints in the decoding side and hence helps in such advanced application scenarios. This paper reviews the MVC + D standard, which specifies an MVC-compatible MVD coding format.     

Depth and depth–color coding using shape-adaptive wavelets

We present a novel depth and depth–color codec aimed at free-viewpoint 3D-TV. The proposed codec uses a shape-adaptive wavelet transform and an explicit encoding of the locations of major depth edges. Unlike the standard wavelet transform, the shape-adaptive transform generates small wavelet coefficients along depth edges, which greatly reduces the bits required to represent the data. The wavelet transform is implemented by shape-adaptive lifting, which enables fast computations and perfect reconstruction. We derive a simple extension of typical boundary extrapolation methods for lifting schemes to obtain as many vanishing moments near boundaries as away from them. We also develop a novel rate-constrained edge detection algorithm, which integrates the idea of significance bitplanes into the Canny edge detector. Together with a simple chain code, it provides an efficient way to extract and encode edges. Experimental results on synthetic and real data confirm the effectiveness of the proposed codec, with PSNR gains of more than 5 dB for depth images and significantly better visual quality for synthesized novel view images.     

A tunable CMOS Wilkinson power divider using active inductors

This paper presents the design and implementation of a tunable CMOS Wilkinson power divider using active inductors. Compared to a conventional active inductor topology, the proposed active inductor features higher inductance tuning range, higher self-resonant frequency, and lower power consumption by introducing two additional transistors. Benefitting from the superior inductor, the low-loss Wilkinson power divider is practical while maintaining a wide tuning range. The design consuming 10.2 mW demonstrates an insertion loss of 0.67 dB, a return loss of 27 dB, and an isolation of 22.6 dB at 8 GHz. Moreover, the tuning range of the circuit is between 5.8 GHz and 10.4 GHz, rendering a 4.6 GHz bandwidth. The active chip size of the lumped design is merely 0.25 mm × 0.15 mm.     

Nano-graphoepitaxy of semiconductors for 3D integration

The advantages of integrating semiconductor devices at more than one level (‘3D integration’) are now recognized. Key to achieving monolithic 3DICs is the ability to form single crystal semiconductor islands at the upper level without unduly heating the lower level structures. In prior work a surface relief grating of 3.8 μm pitch in the substrate was used to mediate single crystal formation while continuous wave (CW) heating a thin film of amorphous silicon; the term ‘graphoepitaxy’ was coined. CW heating is not possible in our case because it would overheat the lower layers. Moreover the area of the crystallites need only be about 100 nm to accommodate today’s transistors. Thus we have chosen a substrate grating pitch of 190 nm (hence the term ‘nano-graphoepitaxy’) and a modulated CW laser to reduce the heating time to several μs. Preliminary results indicate the substrate grating lines can indeed determine the position of the crystallite boundaries when the film thickness is 100 nm; the effect is much less pronounced in 500 nm thick films.     

Reconstruction of lost depth data in multiview video-plus-depth communications using geometric transforms

This paper addresses depth data recovery in multiview video-plus-depth communications affected by transmission errors and/or packet loss. The novel aspects of the proposed method rely on the use of geometric transforms and warping vectors, capable of capturing complex motion and view-dependent deformations, which are not efficiently handled by traditional motion and/or disparity compensation methods. By exploiting the geometric nature of depth information, a region matching approach combined with depth contour reconstruction is devised to achieve accurate interpolation of arbitrary shapes within lost regions of depth maps. The simulation results show that, for different packet loss rates, up to 20%, the depth maps recovered by the proposed method produce virtual views with better quality than existing methods based on motion information and spatial interpolation. An average PSNR gain of 1.48 dB is obtained in virtual views synthesised from depth maps using the proposed method.     

A wideband RF receiver with extended statistical element selection based harmonic rejection calibration

In this paper we present a wideband harmonic rejection (HR) RF receiver design. Both gain mismatch and phase mismatch of the HR mixer have been calibrated using a design and calibration method called extended statistical element selection to achieve best-in-class HR ratio (HRR) performance. The achieved concurrent 3rd order HRR and 5th order HRR are greater than 80 dB and 70 dB, respectively, after calibration. The even order HRR is also calibrated to greater than 80 dB. A single calibration performed at 750 MHz was further observed to be effective over more than two octaves of bandwidth with greater than 70 dB HRR. The receiver was manufactured in 65 nm CMOS technology. Input RF frequency range was 0.15–1 GHz and the receiver consumes 64 mW at 1 GHz. Noise figure is 3.2 dB and out-of-band IIP3 is −7 dBm at a total gain of 48 dB.     

Depth reconstruction filter for depth coding

Depth images represent the distances of scene elements from a camera in 3D space; their efficient coding is crucial for emerging applications such as free-viewpoint TV and 3D video. An in-loop reconstruction filter that improves the depth-coding performance as well as the rendering quality of virtual views based upon the coded depth is proposed.     

3.1–10.6 GHz ultra-wideband LNA design using dual-resonant broadband matching technique

This paper presents an ultra-wideband low noise amplifier design using the dual-resonant broadband matching technique. The proposed LNA achieves a 10.2 dB gain with ±0.9 dB gain flatness over a frequency range of 3.1–10.6 GHz and a ?3-dB bandwidth of 2.4–11.6 GHz. The measured noise figure ranges from 3.2 to 4.7 dB over 3.1–10.6 GHz. At 6.5 GHz, the measured IIP3 and input-referred P1dB are +6 dBm and ?5 dBm, respectively. The proposed LNA occupies an active chip area of 0.56 mm² in a TSMC 0.18 μm RF-CMOS process and consumes 16 mW from a 1.8 V supply.     

A low-voltage low-power CMOS transmitter front-end using current mode approach for 2.4 GHz wireless communications

This paper presents a low-voltage low-power transmitter front-end using current mode approach for 2.4 GHz wireless communication applications, which is fabricated in a chartered 0.18 μm CMOS technology. The direct up-conversion is implemented with a current mode mixer employing a novel input driver stage, which can significantly improve the linearity and consume a small amount of DC current. The driver amplifier utilizes a transimpedance amplifier as the first stage and employs an inter-stage capacitive cross-coupling technique, which enhances the power conversion gain as well as high linearity. The measured results show that at 2.4 GHz, the transmitter front-end provides 15.5 dB of power conversion gain, output P?1 dB of 3 dBm, and the output-referred third-order intercept point (OIP3) of 13.8 dBm, while drawing only 6 mA from the transmitter front-end under a supply voltage of 1.2 V. The chip area including the testing pads is only 0.9 mm×1.1 mm.     

A compact broadband MMIC sub-harmonic mixer using quasi-lumped transmission lines

A compact broadband monolithic microwave integrated circuit (MMIC) sub-harmonic mixer using an OMMIC 70 nm GaAs mHEMT technology is demonstrated for 60 GHz down-converter applications. The present mixer employs an anti-parallel diode pair (APDP) to fulfill a sub-harmonic mixing mechanism. Quasi-lumped components are employed to broaden the operational bandwidth and minimize the chip size to 1.5×0.77 mm². The conversion gain is optimized by a quasi-lumped 90° phase shift stub. Experimental results show that from 50 GHz to 70 GHz, the conversion gain varies between −12.1 dB and −15.2 dB with a LO power level of 10 dBm and 1 GHz IF. The LO-to-RF, LO-to-IF and RF-to-IF isolations are found to be greater than 19.5 dB, 21.3 dB and 25.8 dB, respectively. The second harmonic component of the LO signal is suppressed. The proposed mixer has an input 1 dB compression point of -2 dBm and exhibits outstanding figure-of-merits.     

Realization of current-mode biquadratic filter employing multiple output OTAs and MO-CCII

This paper presents a low voltage low power operational transconductance amplifier circuit. By using a source degeneration technique, the proposed realization powered at ±0.9 V shows a high DC gain of 63 dB with a unity gain frequency at 3.5 MHz, a wide dynamic range and a total harmonic distortion of −60 dB at 1 MHz for an input of 1 Vpp. According to the connection of negative current terminal to positive voltage terminal of double output OTA circuit, a second generation current conveyor (CCII-) has been realized. This circuit offers a good linearity over the dynamic range, an excellent accuracy and wide current mode of 56 MHz and voltage mode of 16.78 MHz cut-off frequency f-3 dB.Thereafter, new SIMO current-mode biquadratic filter composed by OTA and CCII as active elements and two grounded capacitors is implemented. This filter is characterized by (i) independent adjusting of pole frequency and quality factor, (ii) it can realize all simulations results without changing the circuit topology, (iii) it shows low power consumption about 0.24 mW. All simulations are performed by Cadence (Cadence Design Systems) technology Tower Jazz 0.18 μm TS18SL.     

Design and simulation of a π/2-mode spatial-harmonic magnetron

Design and 3D numerical simulations of a 37.5 GHz spatial-harmonic magnetron (SHM) are presented. The effect of geometrical parameters of the side resonators of the anode block on output power are considered using the results of a theory based on the single harmonic approximation approach. This theory enables determination of the optimum geometrical parameters of the side resonators. SHM design evaluation is carried out via numerical simulations performed with a 3D particle-in-cell (PIC) code embedded in CST-Particle Studio. Effect of varying the external quality factor and DC-anode voltage on output power, efficiency and stability of operation are also considered. The presented SHM shows stable operation in the π/2-mode over a range of DC anode voltages extending from 12.4 kV to 13 kV and for an axial magnetic flux density equal to 0.53 T. RF output power of the SHM varies from 25 kW to 47 kW over these voltages with a maximum efficiency of around 18.5%.     

Experimental validation of a constant-envelope OFDM system for optical direct-detection

In this paper, we experimentally investigate a peak-to-average power ratio (PAPR) reduction technique based on a constant envelope orthogonal frequency division multiplexing (CE-OFDM) approach in direct-detection optical OFDM (DDO-OFDM) systems. In comparison to conventional DDO-OFDM, our results show a 6.37 dB performance gain in terms of error vector magnitude (EVM) with a 5 Gb/s DDO-CE-OFDM transmission system over 40 km of uncompensated standard single-mode fiber (SSMF) at an optical injection power of 5 dBm.     

A low power and small area digital self-calibration technique for pipeline ADC

A digital self-calibration implementation with discontinuity-error and gain-error corrections for a pipeline analog-to-digital converter (ADC) is presented. In the proposed calibration method, the error owing to each reference unit capacitor of the multiplying D/A converter is measured separately using a calibration capacitor and an enhanced resolution back-end pipeline ADC acting as an error quantizer. The offset and finite open loop DC-gain of the operational amplifier and capacitor mismatches, the reference voltage mismatch can all be calibrated. The calibration can be achieved by that only used addition and subtraction. Hence, it needs low power and area consuming. A prototype ADC with the proposed calibration was fabricated on a 0.5 μm double-poly triple-metal CMOS process. The power consumption and area of the calibration circuit are only 10.1 mW and 1.05 mm², respectively. At a sampling rate of 30 MS/s, the calibration improves the DNL and INL from 2.59 LSB and 14.98 LSB to 0.72 LSB and 1.82 LSB, respectively. For a 1.25 MHz sinusoidal signal, the calibration improves the signal-to-noise-distortion ratio and spurious-free dynamic range from 43.1 dB and 52.1 dB to 75.51 dB and 83.61 dB, respectively. The 12.25 effective number of bits at 30 MS/s ADC consumes a total power of 136 mW.     

Design and analysis of implantable CPW fed bowtie antenna for ISM band applications

A novel implantable coplanar waveguide (CPW) fed crossed bowtie antenna is proposed for short-range biomedical applications. The antenna is designed to resonate at 2.45 GHz, one of the industrial-scientific-medical (ISM) bands. It is investigated by use of the method of moments design equations and its simulation software (IE3D version 15). The size of the antenna is 371.8 mm³ (26 mm × 22 mm × 0.65 mm). The simulated and analyzed return losses are −23 and −25 dB at the resonant frequency of 2.45 GHz. We have analyzed some more performances of the proposed antenna and the results show that the proposed antenna is a perfect candidate for implantation. The proposed antenna has substantial merits like low profile, miniaturization, lower return loss and better impedance matching with high gain over other implanted antennas.     

Design of ultra-low voltage integrated CMOS based LNA and mixer for ZigBee application

This work describes the design and implementation of an ultra-low voltage, ultra-low power fully differential low noise amplifier (LNA) integrated with a down-conversion mixer for 2.4 GHz ZigBee application. An inductive-degenerated cascoded LNA is adapted and integrated with a double-balanced mixer which is targeted for low-power application. The proposed design has been extracted and simulated in a 0.13 μm standard CMOS technology. With a power consumption of 905 μW at a voltage headroom of 0.5 V, the proposed LNA-mixer integration reaches out to an integrated noise figure (NF) of 7.2 dB, a gain of 22.3 dB, 1 dB compression point (P1 dB) of −22.3 dBm and input-referred third-order intercept point (IIP3) of −10.8 dBm.     

Low power dissipation SiGe HBT dual-band variable gain amplifier

A dual-band variable gain amplifier operating at 0.9 GHz and 2.4 GHz was designed based on high performance RF SiGe HBT for large amount of signals transmission and analysis. Current steering was adopted in gain-control circuit to get variable trans-conductance and then variable gain. Emitter degeneration and current reuse were considered in amplifying stage for low noise figure and low power dissipation respectively. A single-path circuit resonating at two frequency points simultaneously was designed for input impedance matching. PCB layout parasitic effects, especially the via parasitic inductor, were analyzed theoretically and experimentally and accounted for using electro-magnetic (EM) simulation. The measurement results show that a dynamic gain control of 26 dB/16 dB in a control voltage range of 0.0–1.4 V has been achieved at 0.9/2.4 GHz respectively. Both S₁₁ and S₂₂ are below than –10 dB in all the control voltage range. Noise figures at both 0.9 GHz and 2.4 GHz are lower than 5 dB. Total power dissipation of the dual-band VGA is about 16.5 mW at 3 V supply.