16-Mb synchronous DRAM with 125-Mbyte/s data rate

In order to keep up with the growing need for memory bandwidth at low cost, a new synchronous DRAM (SDRAM) architecture is proposed. The SDRAM has programmable latency, burst length, and burst type for wide variety of applications. The experimental 16M SDRAM (2M×8) achieves a 125-Mbyte/s data rate using 0.5-μm twin well CMOS technology     

250 Mbyte/s synchronous DRAM using a 3-stage-pipelined architecture

A 3.3-V 512-k×18-b×2-bank synchronous DRAM (SDRAM) has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250-Mbyte/s synchronous DRAM with die size of 113.7-mm², which is the same die size as the conventional DRAM, has been achieved with 0.50-μm CMOS process technology     

500-Mb/s nonprecharged data bus for high-speed DRAM's

A nonprecharged data-bus scheme to enhance the intrinsic read data rate of DRAM cores is proposed. Eliminating the precharge cycle of the DRAM data bus can reduce the unit bit time. A differential partial response detection data-bus amplifier is also employed to detect signals on the nonprecharged data bus that are degraded by large intersymbol interference. To enhance the read operation further, column selections are overlapped by interleaved column decoders. To increase the operating margin of the nonprecharged data-bus read, a skew-controlled column-selection pulse generator was developed. An isolated sense-amplifier scheme increases the write data rate of the DRAM core. To verify these schemes, a 4-Mb DRAM was fabricated via 0.24-μm DRAM technology. These schemes realized a 500-Mb/s per data-bus read operation and a 100-Mb/s per data-bus write operation without an area penalty     

A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor

This paper describes three circuit technologies that have been developed for high-speed large-bandwidth on-chip DRAM secondary caches. They include a redundancy-array advanced activation scheme, a bus-assignment-exchangeable selector scheme and an address-zero access refresh scheme. By using these circuit technologies and new small subarray structures, a row-address access time of 12 ns and a row-address cycle time of 16 ns were obtained. An experimental chip made up of an 8-Mbyte DRAM and a 64-bit microprocessor was developed using 0.25-μm merged logic and DRAM process technology     

A 7F2 cell and bitline architecture featuring tiltedarray devices and penalty-free vertical BL twists for 4-Gb DRAMs

A 7F² DRAM trench cell and corresponding vertically folded bitline (BL) architecture has been fabricated using a 0.175 μm technology. This concept features an advanced 30° tilted array device layout and an area penalty-free inter-BL twist. The presented scheme minimizes local well noise by maximizing the number of twisting intervals. A significant improvement of signal margin was measured on a 32-Mbyte test chip     

A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integratedmedia chip

A modular architecture for a DRAM-integrated, multimedia chip with a data transfer rate of 6 to 12 Gbyte/s is proposed. The architecture offers the design flexibility in terms of both DRAM capacity and the logic-memory interface for use in a wide variety of applications. A DRAM macro built from cascadable DRAM bank modules having a 256-kb memory capacity and 128-b I/Os provides flexibility and reconfigurability of DRAM capacity and a high data transfer rate with an area of 6.4 mm² /Mb. A data transfer circuit (called the “reconfigurable data I/O attachment”), which is attached to the I/O lines of the DRAM macro, provides a flexible logic-memory interface by changing the data-transfer routes between the DRAM macro and logic circuits in real time. A 6.4-Gbyte/s test chip (called the “media chip”) for three-dimensional computer graphics was fabricated to test the proposed design methodology. It integrates an 8-Mb DRAM and four pixel processors on an 8.35×14.6-mm chip by using a 0.4-μm CMOS design rule     

0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficientredundancy and enhanced testability

This paper describes the 32-Mb and the 64-Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13-μm triple-well 4-level Cu embedded DRAM technology. Core size of 18.9 mm ² and cell efficiency of 51.3% for the 32-Mb capacity, and core size of 33.4 mm² and cell efficiency of 58.1% for the 64-Mb capacity are realized. This core can achieve 230-MHz burst access at 1.0-V power-supply condition by adopting a new data bus architecture: merged shift column redundancy. We implemented four test functions to improve the testability of the embedded DRAM core. It realizes the DRAM core test in a logic test environment     

A 20-ns 128-kbit×4 high speed DRAM with 330-Mbit/s data rate

The authors describe a high-speed DRAM (HSDRAM), designed primarily for high performance, while retaining the density advantage of the one-transistor DRAM cell. The 128-kb×4, 78-mm² chip shows a random access time of 20 ns and a column access time of 7.5 ns, measured at 5.0 V, 25°C, and 50-pF load. A 256-b×4 high-speed page mode is provided which has 12-ns cycle into 60 pF, resulting in a data rate of 330 Mb/s. Additional measurements on HSDRAM further demonstrate that DRAM operation in a high-speed regime is not precluded by noise, power, wiring delay, and soft error rate. The device is implemented in a 1.0 μm n-well CMOS process     

A Hard Disk Channel Processor

A new hard disk controller (HDQ) LSI for 16/32-bit personal computers has been developed. The key feature of the controller is its on-chip DMA capability. The LSI operates as a channel processor based upon a Channel Control Word (CCW) scheme as well as a hard disk controller. Over 1.75-Mbyte/s disk data speed and over 6.6-Mbyte/s host bus data speed were obtained simultaneously.     

A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems

We describe a DRAM interface operating at 3.6 Gb/s/pin implemented in 130-nm CMOS logic and 110-nm DRAM process technologies. It utilizes simultaneous bidirectional (SBD) signaling in a daisy-chained (repeated), point-to-point configuration to enable high performance scalable memory subsystems; and also provides direct attach capability for DRAMs to memory controllers or other logic devices. Source-synchronous strobes are used for data capture, minimizing strobe-to-data jitter. A low-jitter differential clock retimes the data at each DRAM on a per DIMM basis preventing jitter from accumulating in repeated data. The phase of this clock is adjusted on each DRAM to minimize the latency of the repeaters. 80 mW of total power is dissipated per DRAM I/O at 3.6 Gb/s. We present results from a system using both memory controller and DRAM repeater test chips.     

A 500-Mb/s quadruple data rate SDRAM interface using a skewcancellation technique

A quadruple data rate (QDR) synchronous DRAM (SDRAM) interface processing data at 500 Mb/s/pin with a 125-MHz external clock signal is presented. Since the QDR interface has a narrower data timing window, a precise skew control on data signals is required. A salient skew cancellation technique with a shared skew estimator is proposed. The skew cancellation circuit not only reduces the data signal skews on a printed circuit board down to 250 ps, but also aligns the data signals with an external clock signal. The entire interface, fabricated in a 0.35-μm CMOS technology, includes a high-speed data pattern generator and consumes 570 mW of power at 3.0-V supply. The active die area of the chip with the on-chip data pattern generator is 2.4 mm²     

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface

This paper describes a bidirectional, differential, 16 Gb/s per link memory interface that includes a Controller and an emulated DRAM physical interface (PHY) designed in 65 nm CMOS. To achieve high data rate, the interface employs the following technology ingredients: asymmetric equalization, asymmetric timing calibration, asymmetric link margining, inductor based (LC) PLLs, multi-phase error correction, and a data dependent regulator. At 16 Gb/s, this interface achieves a unit-interval to inverter FO4 ratio of 2.8 (Controller) and 1.4 (DRAM) and operates in a channel with 15 dB loss at Nyquist. Under such bandwidth limitations on and off chip, the Controller and DRAM PHYs consume 13 mW/Gb/s and 8 mW/Gb/s, respectively. Using PRBS 2$^{11}-$1, the link achieves a timing margin of 0.19 UI at a BER of 1e-12 for both read and write operations.      

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/sbandwidth

This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V _cc=2.0 V and 25°C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm ² has been fabricated using 0.16 μm four-poly, four-metal CMOS process technology     

A 130-mm2, 256-Mbit NAND flash with shallow trenchisolation technology

A 256-Mbit flash memory has been developed using a NAND cell structure with a shallow trench isolation (STI) process. A tight bit-line pitch of 0.55 μm is achieved with 0.25-μm STI. The memory cell is shrunk to 0.29 μm², which realizes a 130-mm² , 256-Mbit flash memory. Peripheral transistors are scaled with memory cells in order to reduce fabrication process steps. A voltage down converter, which generates 2.5-V constant internal power source, is applied to protect the scaled transistors. An improved bit-line clamp sensing scheme achieves 3.8-μs first access time in spite of long and tight pitch bit-line. A 1-kbyte page mode with 35-ns serial data out realizes 25-Mbyte/s read throughput. An incremental step pulse with a bit by bit verify scheme programs 1-k cells in 1-V Vt distribution within 200 μs. That realizes 4.4-Mbyte/s programming throughput     

A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration

A 512-Mb DDR-II SDRAM has achieved 700-Mb/s/pin operation at 1.8-V supply voltage with 0.12-/spl mu/m DRAM process. The low supply voltage presents challenges in high data rate and signal integrity. Circuit techniques such as hierarchical I/O lines, local sense amplifier, and fully shielded data lines without area penalty have provided improved data access time and, thus, high data rate can be achieved. Off-chip driver with calibrated strength and on-die termination are utilized to give sufficient signal integrity for over 533-Mb/s/pin operation.     

DRAM macros for ASIC chips

DRAM macros in 4-Mb (0.8-μm) and 16-Mb (0.5-μm) DRAM process technology generations have been developed for CMOS ASIC applications. The macros use the same area efficient one transistor trench cells as 4-Mb (SPT cell) and 16-R Mb (MINT cell) DRAM products. It is shown that the trench cells with capacitor plates by the grounded substrate are ideal structures as embedded DRAM's. The trench cells built entirely under the silicon surface allow cost effective DRAM and CMOS logic merged process technologies. In the 0.8-μm rule, the DRAM macro has a 32-K×9-b configuration in a silicon area of 1.7×5.0 mm² . It achieves a 27-ns access and a 50-ns cycle times. The other DRAM macro in the 0.5-μm technology is organized in 64 K×18 b. It has a macro area of 2.1×4.9 mm and demonstrated a 23-ns access and a 40-ns cycle times. Small densities and multiple bit data configurations provide a flexibility to ASIC designs and a wide variety of application capabilities. Multiple uses of the DRAM macros bring significant performance leverages to ASIC chips because of the wide data bus and the fast access and cycle times. A data rate more than 1.3 Gb/s is possible by a single chip. Some examples of actual DRAM macro embedded ASIC chips are shown     

A 1-Gb DRAM for file applications

A time-shared offset-canceling sensing scheme, a defective word-line Hi-Z standby scheme, and a flexible multimacro architecture have been developed for 1-Gb DRAM. These circuit technologies have been applied to a 1-Gb DRAM for file applications employing 0.25 μm CMOS process technology, a diagonal bit-line cell, and a two-stage pipeline circuit technique. In this DRAM, a 30% chip size reduction and a 400-MB/s data transfer rate have been achieved. A 100% improvement in yield has been estimated by Monte-Carlo simulation. The 1-Gb DRAM die size is 936 mm². The cell size is 0.54 μm². The operating current is 58 mA at 2 V and 100 MHz     

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchicalsquare-shaped memory block and distributed bank architecture

This paper describes key techniques for a 1.6-GB/s high data-rate 1-Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are targeted to the advanced unified memory system in which a single DRAM (array) is used as both the main memory and the three-dimensional (3-D) graphics frame memory in a time sharing fashion. The 200-MHz high-speed operation is achieved by the unique hierarchical square-shaped memory block (SSMB) layout and the novel distributed bank (D-BANK) architecture. A 0.29 μm² cell and 581.8 mm² small die area are achieved using 0.15-μm CMOS technology. The ×61 chip uses 196-pin BGA type chip-scale-package (CSP). Implementation of a built-in self-test (BIST) circuit with a margin test capability is also described     

A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus

This paper describes a low-power synchronous pulsed signaling scheme on a fully AC coupled multidrop bus for board-level chip-to-chip communications. The proposed differential pulsed signaling transceiver achieves a data rate of 1 Gb/s/pair over a 10-cm FR4 printed circuit board, which dissipates only 2.9 mW (2.9 pJ/bit) for the driver and channel termination and 2.7 mW for the receiver pre-amplifier at 500 MHz. The fully AC coupled multipoint bus topology with high signal integrity is proposed that minimizes the effect of inter-symbol interference (ISI) and achieves a 3 dB corner frequency of 3.2 GHz for an 8-drop PCB trace. The prototype transceiver chip is implemented in a 0.10-/spl mu/m 1.8-V CMOS DRAM technology and packaged in a WBGA. It occupies an active area of 330/spl times/85 /spl mu/m/sup 2/.     

An experimental 1-Mbit cache DRAM with ECC

A cache DRAM which consists of a dynamic RAM (DRAM) as main memory and a static RAM (SRAM) as cache memory is proposed. An error checking and correcting (ECC) scheme utilizing the wide internal data bus is also proposed. It is constructed to be suitable for a four-way set associated cache scheme with more than a 90% hit rate estimated to be obtained. An experimental cache DRAM with 1-Mb DRAM and 8-kb SRAM has been fabricated using a 1.2-μm, triple-polysilicon, single-metal CMOS process. A SRAM access time of 12 ns and a DRAM access time of 80 ns, including an ECC time of 12 ns, have been obtained. Accordingly, an average access time of 20 ns is expected under the condition that the hit rate is 90%. The cache DRAM has a high-speed data mapping capability and high reliability suitable for low-end workstations and personal computers