基于BiCMOS工艺的D类功率放大器设计

文章首先详细研究了D类音频放大器和相关的BiCMOS的基本原理和结构,并在此基础上综合现阶段国内市场对D类功率放大器的需求,开发了基于0．6μm特征线宽、双层多晶、双层金属的多晶发射极BiCMOS工艺的D类功率放大器。该D类音频放大器,在5V电压下可以以1．4W／Ch的功率驱动阻抗为8的负载。它同样可驱动阻抗为4的负载,5V电压下提供的最大功率为2．1W／Ch。同时还详细描述了前置音频放大器,三角波产生电路、比较器,死区控制电路,输出驱动电路等子模块的设计内容。电路在Cadence环境下进行设计和仿真验证,经过仿真表明电路设计性能良好,符合设计要求,可广泛应用于便携式电子产品。     

D类音频功率放大器的分析和设计要素

D类音频功率放大器是基于脉冲宽度调制（PWM）技术的开关放大器,包括PWM调制器、功率H桥、三角波发生器和低通滤波器等。文章首先对D类音频功率放大器与传统的音频功放进行了分析和比较,然后对D类音频功率放大器的工作原理、系统结构和两种拓扑结构进行了详细的分析和研究,最后对具有低功耗、低失真、高效率等高性能D类音频功放设计的难点和要点进行了研究,并提供了可行的解决方案,展望D类音频功放的发展趋势。     

D类音频功率放大器的设计

BL6352是一款输出功率可达15W的双声道D类音频功率放大器芯片。BL6352既可放大两路音频信号,驱动8Ω的立体声扬声器,也可以作为全差分放大器,桥接单一扬声器。该放大器主要应用在平板电视,有源音箱等大功率音响领域。该电路采用BCD工艺和滤波器设计,以及ESD和封装散热考虑完成了这一电路的设计。     

产品选购指南

高效率D类(Class-D)音频功率放大器；内置音频放大器的子系统；Boomer音频信号增强放大器；Boomer单声道音频放大器；Boomer耳机音频放大器；高集成度Boomer立体声放大器；     

模拟器件

MAX9700B:D类音频放大器 Maxim推出高效、D 类音频功率放大器 MAX9700B,它能 够以D类放大器的 效率(94％)提供AB 类放大器的性能: 0.81％THD N,可 有效节省线路板尺 寸、延长电池使用 寿命。利用Maxim专用的调制和开关结构省去了传统D类放大器的输出滤波器,完     

PWM型D类音频功率放大器的设计

D类音频功放具有高效、节能、小型化的优点,广泛应用于便携式产品、家庭AV设备及汽车音响等多个领域。文章设计了一款工作于5V电源电压并采用PWM来实现的D类音频功率放大器,整个系统包含了输入放大级、误差放大器、比较器、内部振荡电路、驱动电路、全桥开关电路及基准电路。通过引入反馈技术来减小系统的THD指数,采用双路反宽调制...     

制作完美的无失真功率放大器——《音频功放设计手册》出版

《音频功放设计手册》深入浅出地讲解了音频功率放大器的设计理念和制作细节,并以大量的电路试验数据向读者展现功率放大器的技术发展水平。该书至今已经历多次修订,这次修订添加了D类级放大器和用于控制输出偏移的直流伺服系统等内容。这些新增内容在近年的音频功放设计中已被广泛应用。     

驱动死区时间控制及其对D类音频功率放大器稳定性的影响

在D类音频功率放大器中,驱动死区时间控制是一个很流行的术语。它被用来防止击穿的发生。在当今的D类音频功率放大器的设计中,随着开关频率的不断提高,死区时间间隔相对于开关周期也变得足够的长,以至于影响了系统的性能。然而,短而有效的死区时间设置对于在D类转换端口获得更好的线性总是有益的。本文将详细阐述驱动死区时间控制对D类音频功率放大器的影响。通过采用内置的死区时间产生模块的驱动集成电路芯片来降低D类音频功率放大器外部端口器件的数量。仅通过两个额外的电阻来设置DT引脚电压就很容易地得到可选择的预编程死区时间。这种设置死区时间的方式可以阻止外部噪声对系统转换时间的影响,这对于音频的性能是至关重要的。     

业界资讯

25～500 W可扩展输出功率D类音频功率放大器国际整流器公司推出针对每通道25W以上D类音频放大器的IRAUDAMP7参考设计,适用于包括家庭影院设备、乐器和汽车娱乐系统等应用。IRAUDAMP7的功率范围为25～500 W,为单层PCB提供了高度的扩展性。     

数字音频功率放大器的技术与现状

1 前言 功率放大器通常根据其工作状态分为5类。即A类、AB类、B类、C类和D类。在音频功放领域中，前4类均可直接采用模拟音频信号直接输入，放大后将此信号用以推动扬声器发声。D类放大器比较特殊，它只有两种状态，不是通就是断。因此，它不能直接输入模拟音频信号，而是需要通过某种变换后再放大。人们把此种具有“开关”方式的放大，称为“数字放大器” 国外在数字音频功率放大器领域进行了二、三十年的研究，60年代中期，日本研制出8 bit数字音频功率放大器。1983年，M．B Sandler等学者提出D类（数字）PCM功率放大器的基本结构。…     

A high efficiency PWM CMOS class-D audio power amplifier

Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.     

CMOS PWM D类音频功率放大器的过流保护电路

基于Class-D音频功率放大器的应用,采用失调比较器及单边迟滞技术,提出了一种过流保护电路,其核心为两个CMOS失调比较器。整个电路基于CSMC0.5μmCMOS工艺的BSIM3V3Spice典型模型,采用Hspice对比较器的特性进行了仿真。失调比较器的直流开环增益约为95dB,失调电压分别为0.25V和0.286V。仿真和测试结果显示,当音频放大器输出短路或输出短接电源时,过流保护电路都能正常启动,保证音频放大器不会受到损坏,能完全满足D类音频放大器的设计要求。过流保护电路有效面积为291μm×59.5μm。     

Performance comparison of integrated fully-differential filterless class-D amplifiers with different feedback techniques

Two integrated stereo fully differential filterless class-D amplifiers are presented in this paper. The object is to develop a modulation of a class-D audio amplifier with high power efficiency in this paper. The traditional H-bridge class-D audio amplifier has a shortcoming of large signal distortion which is worse than realized. However, the proposed circuit improves the drawback and provides high power efficiency at the same time. The circuit implements a modified scheme of pulse-width modulation. In this paper, we presented two class-D amplifiers, compared their differences and explained why the efficiency and distortion performance can be modified. The increase in total harmonic distortion (THD) is due to non-linearity in the triangle wave. To overcome this problem, a negative feedback from the output of the switching power stage is adopted to reduce the THD. When a 0.7-V_PP and 1 kHz sine wave is used as an input signal, the minimum THD is 0.029 % and the maximum power efficiency is 83 %. The fully differential class-D audio amplifier is implemented with a TSMC 0.35-μm 2P4M CMOS process, and the chip area is 2.57 × 2.57 mm² (with PADs).     

D类音频功率放大器的研究与实现

介绍了采用D类放大器来完成音频信号变换与放大的电路设计。D类放大器采用了改进的方案,即用FPGA作为逻辑控制器实现对PWM H全桥功率放大电路的控制。设计的D类放大器可对数字音源输出的音频信号进行直接放大,为数字音源和功率放大的整合提供了完整的解决方案。他具有比其他类型放大器更高的效率和更低的转换失真,正越来越多地应用在便携式器件中,因此设计课题具有很好的现实意义。     

A 280 mW, 0.07% THD+N class-D audio amplifier using a frequency-domain quantizer

Pulse density modulation (PDM) based class-D amplifiers can reduce non-linearity and tonal content due to carrier signal in pulse width modulation based amplifiers. However, their low-voltage analog implementations also require a linear loop filter and a quantizer. A PDM based class-D audio amplifier using a frequency-domain quantization is presented. The digital intensive frequency-domain approach achieves high linearity under low supply regimes. An analog comparator and a single-bit quantizer are replaced with a current controlled oscillator (ICO) based frequency discriminator. By using the ICO as a phase integrator, a third-order noise shaping is achieved using only two analog integrators. A single-loop, single-bit, class-D audio amplifier is presented with an H-bridge switching power stage, which is designed and fabricated on a 0.18???m CMOS process with 6 layers of metal achieving a total harmonic distortion plus noise (THD+N) of 0.065% and a peak power efficiency of 80% while driving a 4-?? loudspeaker load. The amplifier can deliver the output power of 280 mW.     

A THD-reduction high-efficiency audio amplifier using inverter-based OTAs with filter-output feedback

This paper presents an integrated low-voltage THD-reduction high-efficiency class-D audio amplifier using inverter-based operational transconductance amplifiers (OTAs). We propose a negative feedback loop which can compensate for external perturbations and improving output precision. The compensator increases the audio-frequency loop gain, and leads to a better rejection of audio-frequency disturbances. The use of inverter-based OTA and comparator provides low-voltage operation and low-power dissipation. The audio amplifier operates with a 1.5 V supply voltage with maximum power efficiency of 90%. The proposed class-D amplifier was implemented using a TSMC 0.18-μm 1P6M CMOS process, and the active chip area is 1.87 mm².     

低失真正弦波逆变电源设计

D类功率放大器是一种相当成熟的宽频率功率低失真放大器件,直接用他构成当前大量使用的逆变电源核心电路,具有正弦波形失真低,电路结构简化,易于扩展设计等特点。使用现有技术成熟的成品器件有利于减少专用电源器件的开发和设计费用。通过对TDA7490的正弦逆变电源运用设计,尝试出一种利用D类开关音频器件设计低失真逆变电源的方法。     

Automatic topology selection and sizing of class-D loop-filters for minimizing distortion based on an evolutionary optimization kernel

This paper presents an optimization methodology for continuous time loop-filters design applied to Class-D amplifiers. The methodology is based on an evolutionary optimization approach which integrates both the topology selection and circuit sizing by automatically generating optimal sized topologies and performance tradeoffs for the Class-D amplifier. The presented approach is demonstrated on two cases: for the design of a half-bridge amplifier and for a fully differential BTL class-D loop filter topology that achieves less than 0.003% THD at 680?mW output power in typical 0.18???m CMOS technology.     

高效率音频功率放大器的设计

本文主要介绍的是通过普通电子元件设计出高效率音频功率发大器的方法.它不仅能够减少电路的成本,同时还能够将放大器的效率给提高.该设计中的PWM电路是由基本的运算放大器所构成,从而形成了能满足高效率,低失真要求的D类功率放大器.     

Sliding mode audio class-D amplifier for portable devices

Audio class-D amplifiers are widely used in industrial and consumer portable electronic devices, such as mobile phones, thanks to their high efficiency. However, these amplifiers have a limited linearity due to their switching behavior and also a limited control bandwidth. To overcome these major drawbacks, this paper introduces a self-oscillating control technique based on the sliding mode theory which combines a large control bandwidth and a spread spectrum technique. A high power supply rejection, which is a crucial parameter in modules directly connected to a noisy battery, has also been achieved by introducing a variable hysteresis window. Theoretical analysis, behavioral and electrical simulations are discussed in detail in this paper. An integrated circuit using 0.13 μm CMOS process has been realized focused on mobile phone applications (0.8 W, 3.6 V and 8 Ω). The audio amplifier achieves 97 dB(A) signal-to-noise ratio, 0.02 % harmonic distortion and up to 80 dB of power supply rejection. The die area is smaller than 0.4 mm² while keeping more than 90 % efficiency at 1 W.