一个对温度不敏感的高增益运算放大器设计

功率放大器是大功率器件,其自身会消耗大部分的功耗,并导致功率放大器芯片的温度在一个很大的范围内变化,因此功率放大器的控制电路需要对环境温度的变化不敏感。针对这一要求,设计出一个对温度不敏感的全差分CMOS运算放大器,该运算放大器采用TSMC 0.18μm工艺,选用折叠式共源共栅、宽摆幅偏置电路结构。在负载电容为10 pF条件下,最大直流增益达到115 dBm,相位裕度为70°;在整个温度范围内（-40~＋125℃）运算放大器的增益变化仅为1 dBm,相位裕度仅变化5°,满足设计要求。     

S波段超宽带固态功率放大器的研制

本文结合一款新研制的S波段超宽带固态功率放大器,介绍了超宽带固态功率放大器的设计理论和方法,根据砷化镓场效应晶体管的小信号S参数和I-V曲线,用微波仿真软件对功率管的输入、输出阻抗匹配电路及其偏置电路进行优化仿真设计.通过制作并测试此放大器,验证了该设计方法的可行性.最后,给出了测试数据,它在2GHz～4GHz的频带范围内,输入功率为40mW时,输出功率大于20W,带内功率起伏小于1.5dB.     

Application of enhancement mode FET technology for wirelesssubscriber transmit/receive circuits

Single-supply power amplifiers have become the new paradigm in portable phone handsets due to the recent availability of heterojunction bipolar transistor (HBT) and pseudo enhancement mode PHEMT technology. We have developed a true enhancement mode heterostructure insulated-gate FET device (HIGFET) which is suitable for use in both saturated and linear power amplifiers. A three-stage power amplifier designed for 1900-MHz NADC application delivered +30-dBm output power and 41.7% power-added efficiency with an adjacent channel power of -29.8 dBc and alternate adjacent channel power of -48.4 dBc. In addition to this, we have demonstrated excellent noise figure and linearity performance for small-signal applications. At 900 MHz and bias conditions V_DS=1.0 V and I_DSQ=1 mA, a single-stage amplifier achieved a noise figure of 1.17 dB with an associated gain of 18.5 dB. These results make the technology an ideal candidate for application in both transmitter and receiver circuits     

一种温度不敏感的高线性功率放大器

设计了一种温度不灵敏的高线性度的射频功率放大器芯片,采用新颖的带温度反馈环路的有源片上自适应偏置电路,该电路降低了温度引起的放大器集电极直流电流分量的变化量,补偿了由温度变化而引起的性能偏差,进而有效提高了放大器的线性度。基于这个温度不灵敏的偏置结构采用InGaP/GaAs HBT工艺设计了一个工作在2110~2170 MHz频段的功率放大器。测试结果表明,该功放在工作频段内的增益大于等于35.3 dB;在中心频率2140 MHz处,1 dB功率压缩点大于33 dBm,功率附加效率在输出功率24.5 dBm时为18%;使用LTE_FDD调制信号,获得邻信道功率比为-47 dBc。在环境温度为-40℃、+25℃和+80℃条件下,功放的增益平坦度较好,增益变化量小于1.5 dB,输出级集电极电流基本不变,有效降低了功放对温度的敏感性。     

High-performance V-band cascode HEMT mixer and downconverter module

A high-performance V-band cascode HEMT mixer is presented together with a compact downconverter module integrating the mixer with other receiver MMICs. The cascode mixer was optimized for conversion gain and/or linearity by employing the low-pass interstage networks and by optimizing the bias voltages. The low-pass interstage network effectively filters out the unwanted harmonics and spurious signals, and therefore, enhances the gain and the linearity of the cascode mixer. On a two-tone test, the cascode mixer showed a high conversion gain of 6.3 dB with an LO power of 2.6 dBm at 60 GHz. When the gate bias to the upper common-gate HEMT was tuned for the intermodulation distortion "sweet spot" theoretically predicted by the authors , the mixer showed a high third-order intercept point of 11.2 dBm with a decent gain of 4.1 dB under a small DC power consumption of 8 mW. To benchmark the performance of the cascode mixer of this work, a waveguide-based compact V-band downconverter module was built by integrating the mixer with an MMIC LNA, a VCO, and a LO driving amplifier. The downconverter module showed a conversion gain higher than 20 dB from 57.5 to 61.7 GHz. This paper shows the potential of the cascode FET mixer for high-performance compact downconverter applications at millimeter-wave frequencies.     

Monolithic micropower amplifier using SiGe n-MODFET device

A micropower-relevant model is extracted from the DC characteristics of an n-type buried channel Si/SiGe hetero-junction modulation doped FET (HMODFET). This model is then used to design a novel monolithic SiGe single-stage class-A power amplifier for micropower operation (sub 500 /spl mu/W). The amplifier is fabricated and measured data of the power-gain against operating power are presented for the first time.     

匹配电路谐波特性对功率放大器性能的影响

用 HP EESOF Series IV软件的负载牵引法对功率放大器进行分析 ,给出了匹配电路的基波特性及谐波特性对功率放大器性能的负载牵引结果 ,提出了功率放大器匹配电路谐波设计的思想 ,并给出了设计实例     

Modeling the bias and temperature dependence of a C-class MESFETamplifier

In this paper, a complete bias and temperature-dependent large-signal model for a MESFET is determined from experimental S-parameters and dc measurements. This model is used in the analysis of the performance of a C-class amplifier at 4 GHz over a -50° to 100°C temperature range and for different bias conditions. The dependencies of the elements of the equivalent circuit, as well as the amplifier gain on the temperature and the operating point, are evaluated. The gain optimization and the analysis as a function of temperature of the MESFET amplifier are done by using the describing function technique. Optimum bias device conditions in the C-class are obtained for maximum gain and also the flattest gain versus input power rate. A comparison between theoretical and measured results over temperature and bias ranges is shown. Experimental results show an excellent agreement with the theoretical analysis     

230W C-band GaN-FET power amplifier

A C-band high-power amplifier with two GaN-based FET chips exhibits record output powers under continuous-wave (CW) and pulsed operation conditions. At 5.0 GHz, the developed GaN-FET amplifier delivers a CW 208 W output power with 11.9 dB linear gain and 34% power-added efficiency. It also shows a pulsed 232 W output power with 8.3 dB linear gain.     

A monolithic three-stage 2-8-GHz feedback amplifier

A monolithic three-stage resistive-feedback amplifier has been developed for the 2-8-GHz band. This amplifier uses a novel approach which incorporates three stages with varying FET gate widths. The measured gain is 19 ± 1 dB and the VSWR is 2.3:1 in this band. The amplifier chip has a noise figure of ∼6 dB over the bandwidth. The chip size is less than 2.0 × 1.6 mm²and includes the bias circuitry. The amplifier also has AGC capability with more than 20 dB of gain control.     

A high-yield, 3—7-GHz, 0.5-W push-pull GaAs MMIC amplifier

A high-yield, 3-7-GHz, 0.5-W MMIC GaAs amplifier has been successfully designed and tested. The amplifier features small chip size (1.2 mm sq.), high gain (12 ± 1.5 dB), high power-added efficiency (20 percent), good RF yield (57 percent, and high tolerance to process variations. Packaged amplifiers were built with this chip for both the 2-6-GHz and the 5.9-6.4-GHz bands. Saturated output power of 25 dBm was achieved in the 2-6-GHZ band, and 27 dBm in the 5.9-6.4-GHz band. Infrared measurements show that the device has low FET channel temperatures when operated at full bias power over the full range of military ambient temperatures.     

GaAs cryo-cooled LNA for C-band radioastronomy applications

The design procedure and measurements of a C-band high-performance GaAs cryo-cooled low noise amplifier (LNA) are presented. The latter provides 30 dB gain, a noise figure (NF) lower than 0.12 dB (i.e. 8 K equivalent noise temperature) at 25 K operating temperature, with 35 mW DC bias power only. An appropriate scaling of the device gate periphery has been adopted to trade-off the LNA's NF and DC power consumption.     

PCS/W-CDMA dual-band MMIC power amplifier with a newly proposed linearizing bias circuit

A personal communications service/wide-band code division multiple access (PCS/W-CDMA) dual-band monolithic microwave integrated circuit (MMIC) power amplifier with a single-chip MMIC and a single-path output matching network is demonstrated by adopting a newly proposed on-chip linearizer. The linearizer is composed of the base-emitter diode of an active bias transistor and a capacitor to provide an RF short at the base node of the active bias transistor. The linearizer enhances the linearity of the power amplifier effectively for both PCS and W-CDMA bands with no additional DC power consumption, and has negligible insertion power loss with almost no increase in die area. It improves the input 1-dB gain compression point by 18.5 (20) dB and phase distortion by 6.1/spl deg/ (12.42/spl deg/) at an output power of 28 (28) dBm for the PCS (W-CDMA) band while keeping the base bias voltage of the power amplifier as designed. A PCS and W-CDMA dual-band InGaP heterojunction bipolar transistor MMIC power amplifier with single input and output and no switch for band selection is embodied by implementing the linearizer and by designing the amplifier to have broad-band characteristics. The dual-band power amplifier exhibits an output power of 30 (28.5) dBm, power-added efficiency of 39.5 % (36 %), and adjacent channel power ratio of -46 (-50) dBc at the output power of 28 (28) dBm under 3.4-V operation voltage for PCS (W-CDMA) applications.     

A new "active" predistorter with high gain and programmable gain and phase characteristics using cascode-FET structures

A MMIC-compatible miniaturized "active" predistorter using cascode FET structures is presented. The predistorter has added functionality of gain, as well as programmable gain and phase variation characteristics, which are required to compensate or the nonlinear distortion of a wide range of power amplifiers (PAs). Thanks to the inherent gain of the predistorter, a need for an additional buffer amplifier is eliminated. Furthermore, it can eventually replace the first-stage amplifier in the multistage PAs, making this approach well suited to MMIC implementation. A simple analysis is performed to understand the phase variation mechanisms in the proposed predistorter and to identify the dominant sources of phase variation. To demonstrate the general usefulness of this predistorter, the cascode predistorter was applied to linearize watt-level MMIC amplifiers for CDMA handset applications, as well as 30 W high power amplifiers for base-station applications. Adjacent channel power ratio (ACPR) improvement of 3-5 dB was achieved with off-chip predistorter when applied to 0.9 W monolithic amplifiers. The predistorter was also integrated with a 1.6 W MMIC PA on a single chip, replacing the first-stage transistor of the amplifier.     

Integrated amplifiers using fully ion-implanted InP JFETs with hightransconductance

Monolithically integrated amplifiers have been fabricated using JFETs with a gate length of 1.5 μm and a maximum transconductance of 110 mS/mm, the highest ever reported for ion-implanted InP JFETs. The amplifiers utilized both a conventional direct-coupled design and a new symmetrical design. The conventional direct-coupled amplifier shows a maximum gain of 8 (18 dB) while the symmetrical amplifier design exhibits the same gain without DC offset regardless of the FET threshold voltage and the power supply voltage used     

C波段高效率高线性GaN MMIC功率放大器

基于SiC衬底0.25μm GaN HEMT工艺,设计实现了一款C波段、高效率和高线性的单片微波集成电路(MMIC)功率放大器。通过优化电路匹配结构,选择合适的有源器件和恰当的直流偏置条件,实现低视频漏极阻抗;利用后级增益压缩和前级增益扩张对消等手段,实现高功率附加效率和好的线性指标。功率放大器芯片尺寸为2.35 mm×1.40 mm。芯片测试结果表明,在3.7~4.2 GHz频率范围内,漏极电压28 V、末级栅极电压-2.2 V、前级栅极电压-1.8 V和连续波条件下,该功率放大器的小信号增益大于25 dB,大信号增益大于20 dB,饱和输出功率大于39 dBm,在输出功率回退至32 dBm时,功率附加效率大于30%,三阶交调失真小于-37 dBc。     

Ultrahigh power efficiency operation of common-emitter andcommon-base HBT's at 10 GHz

The DC and RF characteristics of microwave power HBTs are described. Ultrahigh power-added efficiency is reported for AlGaAs-GaAs HBTs operating at 10 GHz in common-emitter (CE) and common-base (CB) modes. A record high 67.8% power-added efficiency with 11.6 dB associated gain was achieved with a CE HBT at a CW output power of 0.226 W, corresponding to a power density of 5.6 W/mm. With a CB HBT, 62.3% power-added efficiency with 11.85 dB gain and 0.385 W total CW power was demonstrated. Power saturation characteristics of CE and CB HBTs are compared. The importance of bias schemes is discussed. High-efficiency operation in near class B mode is described and compared with FET operation. An advantage of HBT over FET is the low leakage current during the off half cycle in class B operation. Stability conditions for CE and CB HBTs are discussed     

基于0.25μm GaAs PHEMT工艺的32GHz毫米波单片功率放大器

设计、制造和测试了基于0.25μm栅长GaAs工艺的32GHz毫米波单片功率放大器.该功率放大器采用三级放大,工作电压为6V,工作电流为600mA.带内最大小信号增益为17.4dB,在32GHz具有0.5W的饱和功率输出.     

High-efficiency linear RF Amplifier - a unified circuit approach to achieving compactness and low distortion

The realization of a highly efficient linearized amplifier has emerged as a paramount issue in the design of advanced mobile handsets. In this paper, a new RF amplifier linearization scheme using a compensating transistor combination is proposed. The devised approach ably utilizes all terminals of an additional transistor that offers a unified pre-post-distortion and cubic distortion characteristic for performance improvement. Meticulous modeling along with a power-dependent Volterra series is performed to identify contributions on each mechanism under various power levels. An experimental four-tone test reveals a maximum 28-dB reduction for the intermodulation distortion at 1.95 GHz, which outperforms typical pre-distortions of 5-10 dB. A single-ended two-stage amplifier module demonstrates a state-of-the-art power efficiency of 55% with 27-dB transducer gain at 24-dBm output power. Meanwhile, the adjacent channel power ratio (ACPR/sub 1/) is maintained with good margins of -35dBc for a four-channel wideband code-division multiple-access signal under all output dynamics. Graceful degradations on modulation bandwidths, tone spacing, bias, and gain variations are also discussed, showing superb performance with virtually no dedicated retuning circuit parameters for multicarrier applications. By combining a bias control along with the proposed linearization technique, the average efficiency (12%) is 3/spl times/ higher than that of the fixed bias (3.94%), demonstrating the potential utility on further prolonging battery lifetime in practical scenarios.     

低噪声1.21.8GHz致冷FET放大器

本文介绍了低噪声1.21.8 GHz致冷FET放大器的研制工作。在20K环境温度下,带宽1.21.7GHz范围内,放大器噪声温度低于10K,最佳为4K。增益约30dB。设计了一个噪声温度自动测试系统。另外对输入电缆的噪声和总测量误差作了分析。测试总误差为2K。