星座组网中直扩信号快速同步改进算法

基于直扩体制的时分多址(TDMA)卫星星座组网,信号帧前导段长度越短、净荷长度越长,数据传输的效率就越高.但是,直扩体制信号帧前导段长度越短意味着接收信号捕获增益就越低,捕获概率就越低.另外,前导段长度越短要求锁相环信号跟踪收敛速度越快.星座组网整网数据传输效率受到卫星信号同步算法性能的制约.为了提高直扩信号同步算法的性能,从捕获与跟踪两个部分对同步算法进行了改进,提出了一种直扩信号快速同步改进算法.针对捕获部分,分析了前置低通滤波器带宽对扩频信号的自相关函数的影响,通过选择滤波器参数在保证相关主峰无明显恶化情况下提升1/4码片偏差相关峰能量1 dB以上.针对跟踪部分,提出了一种调整闭环控制系统的零极点分布优化锁相环时域响应的锁相环设计方法,给出了基于控制理论优化锁相环闭环系统的零极点分布的四点原则,利用该方法设计的锁相环能大大降低信号跟踪的收敛时间.仿真结果表明,所提改进算法与传统同步方法相比能有效提高信号的捕获概率,加快信号跟踪的收敛速度,明显减少信号的同步时间.     

Designing on-chip clock generators

With recent improvements in semiconductor technology, the speed of state-of-the-art microprocessors has doubled roughly every other year. At such high speed, distributing clock signals across the system and making sure every component in the system is synchronized become very important issues. It is shown that one way to solve the inter-chip clock synchronization problem is to use an on-chip phase-locked loop (PLL) for clock generation. The PLL can generate an on-chip clock that is phase-locked to the off-chip clock. Since the buffer to the PLL is lightly loaded, the delay through it is much smaller than the delay through a conventional clock buffer. As a result, inter-chip clock skew is substantially reduced. The functional blocks of a PLL clock generator, including phase detectors, charge pumps, loop filters, and voltage-controlled oscillators (VCOs) are described. Frequency synthesis in VCO-based PLLs and problems associated with designing and simulating PLLs are discussed     

Analysis and Software Implementation of a Robust Synchronizing PLL Circuit Based on the pq Theory

This paper presents the analysis and software implementation of a robust synchronizing circuit, i.e., phase-locked loop (PLL) circuit, designed for use in the controller of active power line conditioners. The basic problem consists of designing a PLL circuit that can track accurately and continuously the positive-sequence component at the fundamental frequency and its phase angle even when the system voltage of the bus, to which the active power line conditioner is connected, is distorted and/or unbalanced. The fundamentals of the PLL circuit are discussed. It is shown that the PLL can fail in tracking the system voltage during startup under some adverse conditions. Moreover, it is shown that oscillations caused by the presence of subharmonics can be very critical and can pull the stable point of operation synchronized to that subharmonic frequency. Oscillations at the reference input are also discussed, and the solution of this problem is presented. Finally, experimental and simulation results are shown and compared     

Synthesis of Sinusoidal Waveform References Synchronized With Periodic Signals

This paper proposes a novel method to generate a sinusoidal waveform synchronized with any measurable periodic signal whose frequency is within a given neighborhood. The synthesized sinusoidal signal could be used as a reference current for certain applications of parallel active power filters or any other where such synchronization would be necessary (e.g., ac/dc converters for renewable energy resources, power factor correctors, power supplies, UPS, etc.) The method is based on the behavior of a dynamical system and avoids employing the usual combination of phase-locked loop (PLL) and lookup table found in most parallel active filters synthesizing a sinusoidal source current (a table also means using significant storage memory). The novel method produces two high-quality sinusoidal waveforms that are in quadrature and is applicable to those parallel active filters whose control methodology is in the reference frame, or alternatively, it produces three sinusoidal waveforms shifted 120 degrees for designs that work in the frame. Here, a th order implementation is described, including a proof of convergence. For its most simple implementation , simulated and experimental results are included.     

Intelligent PLL Using Digital Processing for Network Synchronization

By combining the advanced technologies of a crystal oscillator, LSI, and a computer, an intelligent phase-locked loop (PLL) which uses digital processing (DP) can be created. This kind of PLL, which is referred to here as DP-PLL, includes a microprocessor and a digitally controlled crystal oscillator. It features excellent performance and countermeasures for disturbances of the input signal by stored program control. In this paper, implementation and performance of the DP-PLL are presented with the aim of application in a master-slave network synchronization system.     

运动误差对双站SAR相位同步及成像的影响

收、发系统间的相位同步是双站合成孔径雷达的一项关键技术,采用锁相环接收机是实现双站SAR系统相位同步的一种可能方法.本文主要就锁相环接收机在运动误差条件下的相位同步问题进行了研究,并分析了锁相环相位误差对系统成像的影响,最后,给出了计算机仿真结果.     

Damping factor influence on linewidth requirements for optical PSKcoherent detection systems

Spectral linewidth requirements for optical phase-shift-keying (PSK) coherent detection systems are found to depend on the phase-locked loop (PLL) parameters. Until now, the damping factor of the PLL has been assumed to be 1/√2 when deriving the required spectral linewidth of a light source, because it is at this value that an electrical PLL offers near optimum performance in many cases. By increasing the PLL damping factor above 1/√2, it is shown that there exists a maximum value of the required linewidth that achieves a received optical power penalty of 1 dB at a bit error rate of 10^-10. The required beat linewidths so obtained are 50% larger than previously reported results (which assume a damping factor of 1/√2). As for PLL frequency acquisition performance, it is shown that raising the camping factor above 1/√2 does not seriously affect the hold-in limit or the pull-in limit. It is also shown that the normalized loop gain that optimizes PLL performance is roughly one half the normalized loop gain at which the PLL oscillation commences     

大气激光通信PPM调制解调系统设计与仿真研究

脉冲位置调制(PPM)是大气激光通信的关键技术之一,可以减少激光器的发射功率,增加通信距离。从实际出发,采用高速数字信号处理器(DSP)设计出PPM调制解调系统;同时介绍了PPM解调时对时隙同步和帧同步的处理方法。仿真结果表明,该调制解调系统具有较好的抗干扰能力,可以满足通信系统的要求。     

QPSK扩频调制信号载波跟踪环路设计

扩频接收基带通常需要载波跟踪环来完成本地载波与接收信号载波的同步,科斯塔斯环是常用的非相干载波相位跟踪环,具有较好的鉴相特性。本文基于常规的单路单载波解调的科斯塔斯环原理,对科斯塔斯环做了改进,提出了对双通道平衡QPSK扩频基带所用载波跟踪环科斯塔斯环的改进方法,并推导出环路误差鉴相信号,用Matlab进行了仿真实验,结果证明利用本环路可实现载波稳定跟踪。     

Properties of Optical Phase-Locked Loop Based on Four Wave Mixing in Semiconductor Laser Amplifiers

In this paper, the properties of the optical phase-locked loop(PLL) based on the four-wave mixing in the semiconductor laser amplifiers (SLAs) are discussed. The components that achieve the function of detecting the bit phase of the input optical signal are concerned and discussed in detail together as a function module named as the optical bit phase detector referred to the general electronic PLL. Therefore, most of the properties of the optical PLL can be analyzed by applying the general phase-locked theory. Here the stability of the optical PLL is discussed. It's shown that the variance of input signal power in the practical application will cause optical PLL system unstable because of its long loop delay. The influence on the output phase jitter of the optical PLL is also investigated.     

A new PLL frequency synthesizer with high switching speed

A phase-locked loop (PLL) frequency synthesizer with high switching speed is proposed. Mobile communication networks are evolving towards microcellulars operating in narrowband TDMA and microwave bands to meet the rapidly increasing demands for both voice and data services. Therefore, synthesizers with high switching speed are required for the realization. However, it will be difficult for conventional synthesizers to provide switching times of shorter than 1 ms. The PLL synthesizer proposed is composed entirely of digital signal processors except for a voltage-controlled oscillator (VCO). The VCO control signal is derived by the subtraction of the linear reference phase and the feedback phase; therefore, it does not need the band-limited loop filter which limits the ability of the loop to switch fast. The experimental results show that it can provide switching times as short as 0.1 ms, which is 10²~10³ times higher than conventional PLL synthesizers, and spurs of less than -60 dB     

A 1.75-GHz highly integrated narrow-band CMOS transmitter withharmonic-rejection mixers

A highly integrated 1.75-GHz 0.35-μm CMOS transmitter is described. The I/Q modulator-based transmitter facilitates integration through the use of a unique mixer, termed a harmonic-rejection mixer, and a wide loop bandwidth phase-locked loop (PLL) for the RF synthesizer. The harmonic-rejection mixers are used to eliminate the need for a discrete IF filter and the use of a wide loop bandwidth PLL allowed for the complete integration of the synthesizers using low-Q components while achieving low phase noise. The entire transmit signal path from the digital-to-analog converters to the power amplifier, including two fully integrated frequency synthesizers, is integrated into a single-chip solution. The transmitter was tested with a testing buffer before the power amplifier (PA) and achieved less than 1.3° rms phase error when modulating a DCS-1800 GMSK signal. The prototype consumed 151 mA from a 3-V supply. A class-C PA, capable of driving 25 dBm off-chip, was included and the output was compared to the testing buffer with little change in the transmitter performance     

锁相环在SDH网络中的应用

在同步数字网络中,同步是数据流正确传输的基础,因此同步技术是数字传输领域的关键技术。为了实现网络的同步,业界普遍采用锁相技术,因为锁相环的性能优越,尤其是数字锁相环的可调范围更宽而且更容易实现。文中以SDH(同步数字系列)技术为例,介绍了以锁相环为基础的同步技术的原理和特点,根据SDH网络中的同步结构和方式,提供了锁相环在SDH网络同步中的具体应用方案,着重分析了这种结构的特性。这种方案在实际应用中有较好的稳定性,对各种网络的同步是一种很好的参考。     

Partially coherent DS-SS performance in frequency selectivemultipath fading

The bit-error rate (BER) performance of a direct sequence spread spectrum (DS-SS) signal, operating over a multipath Rayleigh fading channel, is investigated when corrupted by phase noise as well as additive white Gaussian noise (AWGN). The phase noise arises from phase locked loop (PLL) dynamics and results in imperfect receiver phase estimates whereby the phase errors assume Tikhonov densities. The phase estimates are used by a multipath-combining RAKE receiver for demodulation. Approximate upper-bounds on the bit error probability are obtained and evaluated for different combinations of channel parameters and for various values of the average loop signal-to-noise ratio (SNR). Results indicate that for a PLL with loop SNR 10 dB above the system E _b/η₀, the degradation is less than 3 dB, and for a loop SNR of 20 dB above E_b/η₀, the degradation is less than 1 dB     

Word timing recovery in direct detection optical PPM communicationsystems with avalanche photodiodes using a phase lock loop

A technique for word timing recovery in a direct detection optical pulse position modulation (PPM) communication system is described. It tracks on back-to-back pulse pairs in the received random PPM data sequences with the use of a phase locked loop. The experimental system consisted of an AlGaAs laser diode transmitter (λ=833 nm) and a silicon avalanche photodiode photodetector, and its used Q=4 PPM signaling at a source data rate of 25 Mb/s. The mathematical model developed to characterize system performance is shown to be in good agreement with the experimental measurements. Use of this recovered PPM word clock, along with a slot clock recovery system described previously, caused no measurable penalty in receiver sensitivity when compared to a receiver which used common transmitter/receiver clocks. The completely self-synchronized receiver was capable of acquiring and maintaining both slot and word synchronizations for input optical signal levels as low as 20 average detected photons per information bit. The receiver achieved a bit error probability of 10^-6 at less than 60 average detected photons per information bit     

快速建立时间的自适应锁相环

该文简要讨论了环路性能(建立时间,相位噪声和杂散信号)和环路参数(带宽,相位裕度等)的相互关系。提出并分析了一种自适应的具有快速建立时间的锁相环结构及其关键模块(鉴相鉴频器和电荷泵)。该结构基于两个环路:粗调谐环路和精调谐环路。粗调谐环路用于快速收敛,而精调谐环路用于精细的调整。环路参数调整连续发生,无需切换环路滤波器元件和外面的控制信号。基于SMIC 0.18m 1.8V CMOS工艺的Spectre仿真表明:粗调谐鉴相鉴频器能够有效地关断粗调谐回路;电荷泵上下电流具有小于0.1%的静态失配特性;在相同的环路带宽下与传统的锁相环相比,自适应锁相环能减少超过30%的建立时间。     

Effect of optical amplifier noise on laser linewidth requirementsin long haul optical fiber communication systems with Costas PLLreceivers

The impact of optical amplifier noise is analyzed in investigating the performance of optical long-haul PSK homodyne communication systems with Costas phase locked loop (PLL) receivers. The laser linewidth requirement for an optically amplified system becomes relaxed in comparison with the system with no optical amplifier, owing to the fact that the effect of incomplete phase tracking becomes less important as a larger signal power is demanded to maintain a fixed bit-error rate. Also, it is found that the power splitting ratio regarding the power distributions for the I-arm and the Q-arm of a Costas loop can vary in a wide range without having much influence on the performance of an optically amplified system. As a matter of fact, the power penalty induced by incomplete phase tracking for a system with a large number of cascaded optical amplifiers is mainly due to the finite phase error and not due to the power splitting ratio, and this may fail a previously-reported method for finding the required laser linewidth by assigning a certain amount of power penalty that is due to the power splitting ratio     

Slot clock recovery in optical PPM communication systems withavalanche photodiode photodetectors

Slot timing recovery in a direct-detection optical PPM communication system can be achieved by processing the photodetector output waveform with a nonlinear device whose output forms the input to a phase-locked loop. The choice of a simple transition detector as the nonlinearity is shown to give satisfactory synchronization performance. The RMS phase error of the recovered slot clock and the effect of slot timing jitter on the bit error probability were directly measured. The experimental system consisted of an AlGaAs laser diode (λ=834 nm) and a silicon avalanche photodiode photodetector. The system used Q =4 PPM signaling and operated at a source data rate of 25 Mb/s. The mathematical model developed to compute the RMS phase error of the recovered clock is shown to be in good agreement with results of actual measurements of phase errors. The use of the recovered slot clock in the receiver resulted in no significant degradation in receiver sensitivity compared to a system with perfect slot timing. The system achieved a bit error probability of 10^-6 at a received optical signal energy of 55 detected photons per information bit     

Low Cost Built-in Sensor Testing of Phase-Locked Loop Dynamic Parameters

Phase-locked loops (PLLs) serve as core building blocks for communication systems and are often used to synthesize IO clocks for data synchronization and frequency sources for RF conversion. Testing of PLL loop performance is consequently important for guaranteeing the reliability of the underlying communication systems. In this paper, a low cost testing method based on loop triggering and use of built-in analog sensors (small number of transistors) to accurately predict phase-locked loop dynamic parameters is proposed. The sensor responses show strong statistical correlation with the PLL parameters being tested. Accordingly, supervised learning is applied to predict the required PLL parameters from the observed sensor response after “training”. In order to verify analog sensor testing in PLL loop response evaluation, an off-the-shelf PLL and a PLL on printed circuit board (PCB) are tested using this method. The results are analyzed and shown with high correlation to loop parameters. Parameters including charge pump current, voltage-controlled oscillator (VCO) gain, bandwidth, phase margin, and locking time are predicted accurately to prove the viability of the proposed test method.     

无线光通信中的定长数字脉冲间隔调制

针对脉冲位置调制(PPM)需要符号同步和数字脉冲间隔调制(DPIM)符号长度不固定所引起的问题,提出了一种新的定长数字脉冲间隔调制(FDPIM)。给出了相应的编码结构,并分析了平均功率效率和带宽需求。在弱湍流信道模型下推导了定长数字脉冲间隔调制的误包率,并与开关键控(OOK)、脉冲位置调制和数字脉冲间隔调制等调制方式进行了比较分析。结果表明,定长数字脉冲间隔调制的误包率劣于脉冲位置调制和数字脉冲间隔调制,但明显优于开关键控的误包率。虽然定长数字脉冲间隔调制的带宽要求较高,但不需要符号同步,相对于脉冲位置调制系统,实现的复杂性大大简化;相对于数字脉冲间隔调制,其符号长度固定,不会出现因符号时隙个数不固定所引起的调制器等待或缓冲器溢出问题。