A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior     

Sub-quarter-micrometer CMOS on ultrathin (400 Å) SOI

MOS transistors with effective channel lengths down to 0.2 μm have been fabricated in fully depleted, ultrathin (400 Å) silicon-on-insulator (SOI) films. These devices do not exhibit punchthrough, even for the smallest channel lengths, and have performance characteristics comparable to deep-submicrometer bulk transistors. The NMOS devices have a p⁺-polysilicon gate, and the PMOS devices have an n⁺-polysilicon gate, giving threshold voltages close to 1 V with very light channel doping. Because the series resistance associated with the source and drain regions can be very high in such thin SOI films, a titanium salicide process was used using a 0.25 μm oxide spacer. With this process, the sheet resistance of the silicided SOI layer is approximately 5 Ω/□. However, the devices still exhibit significant series resistance, which is likely due to contact resistance between the silicide and silicon source/drain regions     

MOSFET's with PolySilicon gates self-aligned to the field isolation and to the source and drain regions

The fabrication procedure and device characteristics of MOSFET's having a unique gate electrode structure are described. The polysilicon gate electrode of the structure is self-aligned on its ends with respect to the conductive source and drain regions, and is also self-aligned on its sides with respect to the nonconductive field oxide isolation regions. This double self-alignment feature results in a polysilicon gate electrode area that matches the channel region of the FET. Another novel feature of this "recessed-gate" device is a self-registering electrical connection between the gate and the metallic interconnection pattern. Compared to MOSFET's fabricated using more conventional methods, smaller FET's with increased packing density result from this misregistration-tolerant contacting technique and the doubly self-aligned gate electrode structure. The new FET structure may be applied to various integrated circuits such as ROM's, PLA's, and dynamic RAM's. The use of a second layer of polysilicon and the addition of a fifth masking operation yields a dynamic RAM cell of small area with a diffused storage region.     

Fabrication of fully self-aligned joint-gate CMOS structures

A six-mask process that yields stacked CMOS structures with the source and drain of both transistors self-aligned to a joint-gate electrode has been developed. The features that permit full self-alignment are an edge-defined silicon nitride "filament," used as an oxidation mask, and overlapping polysilicon "handles," used to form the top transistor source and drain regions. The individual NMOS and PMOS transistors have been characterized and together are functional in joint-gate CMOS inverters.     

Partially depleted SOI NMOSFET's with self-aligned polysilicon gateformed on the recessed channel region

A new SOI NMOSFET with a “LOCOS-like” shape self-aligned polysilicon gate formed on the recessed channel region has been fabricated by a mix-and-match technology. For the first time, we developed a new scheme for implementing self-alignment in both source/drain and gate structure in recessed channel device fabrication. Symmetric source/drain doping profile was obtained and highly symmetric electrical characteristics were observed. Drain current measured from 0.3 μm SOI devices with V_z of 0.773 V and T_ox=7.6 nm is 360 μA/μm at V_GS=3.5 V and V _DS=2.5 V. Improved breakdown characteristics were obtained and the BV_DSS (the drain voltage for 1 nA/μm of I_D at T_GS=0 V) of the device with L_eff=0.3 μm under the floating body condition was as high as 3.7 V     

Novel self-aligned polysilicon-gate MOSFETs with polysilicon source and drain

A novel self-aligned technique is described for self-aligning a polysilicon gate in devices with polysilicon source and drain regions. The technique is demonstrated for two types of polysilicon source and drain devices. In one type of device, the polysilicon serves as the source of dopant for diffused source and drain junctions. In the second type, the polysilicon, together with an underlying interfacial oxide, forms a tunneling CIS (conductor-thin insulator-semiconductor) structure. The characteristics of devices of both types fabricated under almost identical conditions using the new self-alignment technique are compared.     

A novel source/drain on void (SDOV) MOSFET implemented by local co-implantation of hydrogen and helium

In this paper a novel device named as SDOV MOSFET is proposed for the first time. This structure features localized void layers under the source and drain regions. The short channel effects of this device can be improved due to the SOI-like source/drain structure. In addition, without the dielectric layer under the channel region, this device can avoid some weaknesses of UTB SOI devices caused by the thin silicon film and the underlying buried oxide, such as mobility degradation, film thickness fluctuation and self-heating effect. Based on self-aligned hydrogen and helium co-implantation technology, the new device can be fabricated by a process compatible with the standard CMOS process. The SDOV MOSFETs with 50 nm gate length are experimentally demonstrated for verification.     

An ITLDD CMOS process with self-aligned reverse-sequenceLDD/channel implantation

An advanced inverse-T LDD (ITLDD) CMOS process has been developed. This process features self-aligned lightly-doped-drain/channel implantation for improved hot-carrier protection. Selective polysilicon deposition is used to define the thick polysilicon gate regions with a thin polysilicon gate regions overlying the lightly doped n^- and p⁺ regions. Since the thick poly gate regions are defined by nitride sidewall spacers, optical lithography can be used to define sub-half-micrometer gate length MOSFETs. The LDD implants are performed after the n⁺ and p⁺ implants are annealed, resulting in MOSFET's with improved short-channel behavior due to the smaller lateral source/drain diffusion     

An Amorphous Silicon Local Interconnection (ASLI) CMOS with Self-Aligned Source/Drain and Its Electrical Characteristics

A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional ones. The electrical characteristics of this device are as good as those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3 V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.     

Thin-oxide silicon-gate self-aligned 6H-SiC MOSFETs fabricated witha low-temperature source/drain implant activation anneal

We have demonstrated self-aligned (SA) n+ polysilicon gate n-channel inversion MOSFETs in 6H-SiC with 25-nm thick gate oxides. The nitrogen-implanted source/drain regions were activated with a furnace anneal at 1050°C. These devices exhibit a positive threshold voltage (about +1 V), and peak transconductance of 3.6 mS/mm at V_g=7 V, comparable to the best nonself-aligned 6H-SiC MOSFETs. The subthreshold slope is 200 mV/decade, about two times higher than that of typical silicon MOSFETs. This represents the first demonstration of a viable process for silicon-gate self-aligned MOSFETs in 6H-SiC     

A new MOSFET structure with self-aligned polysilicon source and drain electrodes

A new MOSFET structure whose source and drain electrodes are self-aligned to the gate electrode is proposed. The new structure utilizes a second layer of polysilicon which is defined by a preferrential etching to form the source and drain regions. Due to the self-alignment property of the source and drain regions, the total device size is decreased by about 50 percent over the conventional MOS transistors when the same design rule is used. Experimental results of the new structure are presented.     

The effect of fluorine from BF2 source/drain extensionimplants on performance of PMOS transistors with thin gate oxides

Boron penetration from the gate electrode into the Si substrate presents a significant problem in advanced PMOS device fabrication. Boron penetration, which causes a degradation of many transistor parameters, is further enhanced when BF₂ is used to dope the gate electrode. It is known that pile-up of fluorine from the BR gate implant at the polysilicon/gate oxide interface is responsible for the enhanced boron penetration. However, no reports have been made that address enhanced boron penetration due to fluorine from the source/drain (S/D) implants. It is shown here that fluorine from the S/D extension implants is also a significant problem, degrading transistor performance for gate oxide thickness less than 27 Å and gate lengths less than 0.5 μm     

Hydrogenation by ion implantation for scaled SOI/PMOS transistors

Hydrogenation by ion implantation has been investigated as a promising technique for VLSI/SOI and has been correlated with the resultant characteristics of silicon-on-insulator (SOI) PMOS transistors fabricated in Polycrystalline silicon. SOI/PMOS ON currents increase by one order of magnitude and OFF currents decrease by two orders of magnitude. Hydrogenation improves weak-inversion slopes by nearly an order of magnitude. Channel-length scaling does not adversely affect leakage currents in SOI/PMOS devices in hydrogenated fine grain polysilicon down to a channel length of 2 µm on the mask, whereas devices in laser recrystallized polysilicon do show a degradation. SOI/PMOS transistors can be expected to replace resistors as load elements for 256K SRAM's.     

A novel self-aligned poly-Si TFT with field-induced drain formed by the damascene Process

We have proposed and fabricated a self-aligned polysilicon thin-film transistor (poly-Si TFT) with a thick dielectric layer at the gate edges near the source and drain. A T-shaped polysilicon gate was successfully formed by the damascene process used in VLSI interconnection technology. During the on state, an inversion layer is induced by the subgate as a drain so that the on current is still high and the poly-Si region under the subgate behaves as an offset, reducing the off-state leakage current during the off-state. As the subgate dielectric becomes 3.5 times thicker than the main gate oxide, the minimum off-state leakage current of the new TFT is decreased from 1.4/spl times/10/sup -10/ to 1.3/spl times/10/sup -11/ without sacrifice of the on current. In addition, the on-off current ratio is significantly improved.     

Comparison of self-heating effect in GAA and SOI mosfets

An analytical model is developed to estimate the effect of the scaling of the buried oxide on the heat flow in SOI devices. The heat evacuation is shown to follow the buried oxide thickness to the n-th power with −0.5 > n > −1, and it strongly depends on device dimensions. Three experimental independent evidences of reduced self-heating in GAA devices are provided and analyzed in the light of an analytical model. The advantage of the GAA structure is to replace the buried oxide below the channel by a back polysilicon gate that benefits for a much larger thermal conductivity. To achieve the same result in SOI devices, the buried oxide thickness should be reduced down to twice the gate oxide thickness, which unfortunately would also lead to a dramatic increase of source and drain parasitic capacitances. In the GAA transistor, on the contrary, source and drain regions still lie on the thick buried oxide layer such that those parasitic elements keep a low value.     

Back-gated buried oxide MOSFETs in a high-voltage bipolartechnology for bonded oxide/SOI interface characterization

A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N- epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2×10¹²/cm² at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4×10¹⁰/cm² in the buried oxide     

High-voltage normally off GaN MOSFETs on sapphire substrates

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. Silicon was implanted into an unintentionally doped GaN layer using the polysilicon gate to define the source and drain regions, with implant activation at 1100/spl deg/C for 5 min in nitrogen. The GaN MOSFETs have a low gate leakage current of less than 50 pA for circular devices with W/L=800/128 /spl mu/m. Devices are normally off with a threshold voltage of +2.7 V and a field-effect mobility of 45 cm/sup 2//Vs at room temperature. The minimum on-resistance measured is 1.9 m/spl Omega//spl middot/cm/sup 2/ with a gate voltage of 34 V (W/L=800/2 /spl mu/m). High-voltage lateral devices had a breakdown voltage of 700 V with gate-drain spacing of 9 /spl mu/m (80 V//spl mu/m), showing the feasibility of self-aligned GaN MOSFETs for high-voltage integrated circuits.     

Fully-depleted SOI devices with TaSiN gate, HfO/sub 2/ gate dielectric, and elevated source/drain extensions

We report for the first time the performance of ultrathin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO/sub 2/ gate dielectric and TaSiN gate material. The transistors feature 100-150 /spl Aring/ silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high-k dielectric and metal gate on the performance of ultrathin film FD SOI devices.     

An 1800 V triple implanted vertical 6H-SiC MOSFET

6H silicon carbide vertical power MOSFETs with a blocking voltage of 1800 V have been fabricated. Applying a novel processing scheme, n ⁺ source regions, p-base regions and p-wells have been fabricated by three different ion implantation steps. Our SiC triple ion implanted MOSFETs have a lateral channel and a planar polysilicon gate electrode. The 1800 V blocking voltage of the devices is due to the avalanche breakdown of the reverse diode. The reverse current density is well below 200 μA/cm² for drain source voltages up to 90% of the breakdown voltage. The MOSFETs are normally off showing a threshold voltage of 2.7 V. The active area of 0.48 mm² delivers a forward drain current of 0.3 A at Y_GS=10 V and V _DS=8 V. The specific on resistance was determined to 82 mΩdcm² at 50 mV drain source voltage and at V_GS =10 V which corresponds to an uppermost acceptable oxide field strength of about 2.7 MV/cm. This specific on resistance is an order of magnitude lower than silicon DMOSFET's of the same blocking capability could offer     

CMOS on buried nitride—A VLSI SOI technology

A CMOS technology in silicon on insulator (SOI) for VLSI applications is presented. The insulator is a buried silicon nitride formed by nitrogen implantation and annealing. The CMOS devices are fabricated in the superficial monocrystalline silicon layer without an epitaxial process, 1-µm PMOS and 2-µm NMOS transistors have been realized, which have been used to built inverters, ring Oscillators, and other circuits. With 40-nm gate oxide the transistors withstand gate and drain voltages of 10 V. Mobilities, subthreshold behavior, and leakage currents are nearly the same as in bulk-CMOS devices. Ring-oscillator measurements yield inverter delay times of 230 ps and power delay products of 14 fJ.