Low-loss coplanar waveguides interconnects on low-resistivity silicon substrate

This paper describes fabrication, characterization and simulation of low-loss coplanar waveguide (CPW) interconnects on low-resistivity silicon substrate. The fabrication of CPWs is low-temperature (below 250/spl deg/C) and incorporates a spin-on low-k dielectric benzocyclobutene (BCB) and self-aligned electroplating of copper. The performance of CPWs is evaluated by high-frequency characterization and EM simulation. CPWs with different line width (W) and line spacing (S) are investigated and compared. Using a BCB layer as thick as 20 /spl mu/m, CPW fabricated on a low-resistivity silicon substrate exhibits an insertion loss of 3 dB/cm at 30 GHz.     

High frequency electrical circuits on a planar lightwave circuitplatform

We investigated the propagation losses and the characteristic impedances Z_L of coplanar waveguides (CPWs) and microstrip lines (MSLs) on a planar lightwave circuit (PLC)-platform formed on a silica/silicon substrate. The loss of the CPWs was 2.7 dB/cm at 10 GHz on the PLC-platform with 30 μm thick silica layer. Thus, a cm-order circuit of this CPW is difficult to fabricate in the 10 Gb/s module. This is because the silicon substrate has a large loss tangent (tan δ). On the other hand, the loss of the MSLs, where a ground plane shielded the high loss silicon substrate, could be improved to 0.9 dB/cm at 10 GHz with 30 μm thick polyimide. These lower loss MSLs on a PLC-platform can be applied to module operation at 10 Gb/s. Furthermore they have the advantage that they are suitable for application to array device circuits or circuits in a module where several devices are integrated because unlike CPWs the ground planes are not divided by signal lines or DC bias lines. The structure of CPWs and MSLs on a PLC-platform with a Z_L of 50 Ω was also studied in detail     

Surface-passivated high-resistivity silicon substrates for RFICs

Surface passivation of high-resistivity silicon (HRS) by amorphous silicon thin-film deposition is demonstrated as a novel technique for establishing HRS as a microwave substrate. Metal-oxide-silicon (MOS) capacitor measurements are used to characterize the silicon surface properties. An increase of the quality factor (Q) of a 10-nH spiral inductor by 40% to Q=15 and a 6.5-dB lower attenuation of a coplanar waveguide (CPW) at 17 GHz indicate the beneficial effect of the surface passivation for radio frequency (RF) and microwave applications. Regarding CPW attenuation, a nonpassivated 3000-/spl Omega//spl middot/cm substrate is equivalent to a 70-/spl Omega//spl middot/cm passivated substrate. Surface-passivated HRS, having minimum losses, a high permittivity, and a high thermal conductivity, qualifies as a close-to-ideal radio frequency and microwave substrate.     

在高阻硅衬底上制备低微波损耗的共面波导

分别在普通的低阻硅衬底、带有3μm厚氧化硅介质层的低阻硅衬底和高阻硅衬底上设计并制备了微波传输共面波导.结果表明,低阻硅衬底导致过高的微波损耗从而不能使用,通过加氧化硅介质层,微波损耗可以大大减少,但是需要较厚的氧化硅厚度.直接制备在高阻硅衬底上的共面波导在所测试的26GHz的频率范围内获得低于2dB/cm的微波损耗,而且工艺十分简单.     

Characterization of silver CPWs for applications in silicon MMICs

High-Q broadband passives are needed for monolithic microwave circuits in silicon. Coplanar waveguides (CPWs) provide an effective way to implement passives in silicon monolithic microwave integrated circuits. Silver "fat" wires in the backend interconnects, used for CPW fabrication, will reduce the bulk resistive loss in metallization to the lowest possible level, which is vital to minimize noise. Electromigration, electrochemical migration, and agglomeration issues are not a problem for silver microwave passives, because of their coarse dimensions and the low current densities encountered in these structures. In this letter, Ag and Cu CPWs were designed, fabricated and tested. Silver CPWs showed a 2-3/spl Omega//cm improvement in resistance over copper devices at 20GHz. A circuit was identified in which the application of silver passives could provide an improvement in noise performance.     

Characterization and attenuation mechanism of CMOS-compatible micromachined edge-suspended coplanar waveguides on low-resistivity silicon substrate

This paper presents detailed characterization of a category of edge-suspended coplanar waveguides that were fabricated on low-resistivity silicon substrates using improved CMOS-compatible micromachining techniques. The edge-suspended structure is proposed to provide reduced substrate loss and strong mechanical support at the same time. It is revealed that, at radio or microwave frequencies, the electromagnetic waves are highly concentrated along the edges of the signal line. Removing the silicon underneath the edges of the signal line, along with the silicon between the signal and ground lines, can effectively reduce the substrate coupling and loss. The edge-suspended structure has been implemented by a combination of deep reactive ion etching and anisotropic wet etching. Compared to the conventional silicon-based coplanar waveguides, which show an insertion loss of 2.5dB/mm, the loss of edge-suspended coplanar waveguides with the same dimensions is reduced to as low as 0.5 dB/mm and a much reduced attenuation per wavelength (dB//spl lambda//sub g/) at 39 GHz. Most importantly, the edge-suspended coplanar waveguides feature strong mechanical support provided by the silicon remaining underneath the center of the signal line. The performance of the coplanar waveguides is evaluated by high-frequency measurement and full-wave electromagnetic (EM) simulation. In addition, the resistance, inductance, conductance, capacitance (RLGC) line parameters and the propagation constant of the coplanar waveguides (CPWs) were extracted and analyzed.     

Development of low loss organic-micromachined interconnects on silicon at microwave frequencies

We present the design and development of an ultra-violet (UV) LIGA (a German acronym for electroplating, lithography and molding) micromachining process on silicon substrates at microwave/millimeter wave frequencies. The process employs an ultra-thick negative photoresist SU-8 that can be spin-coated and processed using conventional lithography techniques. Using this process, we have developed micromachined coplanar waveguide (CPW) interconnects on Si substrates. The conductor-backed micromachined CPW on Si (7.2 /spl Omega/-cm) achieves a measured attenuation of 0.18 dB/cm at 20 GHz.     

Low-loss on-chip transmission lines with micro-patterned artificial dielectric shields

Low-loss coplanar waveguide (CPW) transmission lines integrated on a standard (5 -10 Omega ldr cm) silicon substrate are realised by using an artificial dielectric shield with a very high in-plane dielectric constant. The shield consists of a 30 nm-thick Al₂O₃ film sandwiched by two 100 nm-thick aluminium layers patterned into lattices of mum-size elements. The individual metallic elements are micro-patterned to suppress the flow of eddy currents at microwave frequencies. Inserted below the CPW, the shield blocks the electric field of the line from entering the silicon substrate. The resulting line attenuation (measured up to 25 GHz) is comparable to that of identical CPWs built on a high-resistivity silicon wafer.     

Influence of the SRO as passivation layer on the microwave attenuation losses of the CPWs fabricated on HR-Si

In this letter, silicon rich oxide (SRO) is used as the passivation layer of coplanar wave guides (CPWs) fabricated on high resistivity silicon (HR-Si). The microwave performance of the CPWs is evaluated computing the attenuation loss (/spl alpha/) of the device in the 0.045-50 GHz frequency range. It is shown that for frequencies lower than 5 GHz the losses of CPWs using SRO as a passivation layer are lower than those of CPWs using SiO/sub 2/. It is also shown that using a combination of thermal and CVD SiO/sub 2/, a reduction of the losses of CPWs is obtained.     

K-band monolithic InGaP-InGaAs DCFET amplifier using BCB coplanar waveguide technology

A K-band (20 GHz) monolithic amplifier was developed and fabricated by adopting a low-/spl kappa/ benzocyclobutene (BCB) coplanar waveguide (CPW) line and InGaP-InGaAs doped-channel HFETs (DCFETs). This monolithic microwave integrated circuit (MMIC) utilizes a high impedance BCB CPW microstrip line (Z/sub 0/=70 /spl Omega/) for the biasing circuits, and a Z/sub 0/=50 /spl Omega/ line for the RF signal transmission. The low dielectric constant characteristic of the BCB interlayer is beneficial for a common-ground bridge process, which reduces the parasitics. The calculated loss tan/spl delta/ is 0.036 for the BCB at 20 GHz. The one-stage MMIC amplifier achieves an S/sub 21/ of 5 dB at 20 GHz, which is the first demonstration of the K-band InGaP-InGaAs DCFET monolithic circuit.     

Miniaturized CBCPW bandpass filter basedon thin film polyimide on lossy silicon

This letter reports a miniaturized conductor-backed coplanar waveguide (CBCPW) bandpass filter (BPF) based on a thin film polyimide layer coated on a lossy silicon. With a 20-/spl mu/m-thick polyimide interface layer and back metallization, the interaction of electromagnetic fields with the lossy silicon substrate has been isolated, and as a result low-loss and low-dispersive CBCPW line has been obtained. The measured attenuation at 20GHz is below 1.2dB/cm, which is comparable with the CPW fabricated on GaAs. In addition, by using the proposed CBCPW geometry, a miniaturized Ku-band BPF was designed and its measured frequency response demonstrated excellent correlation with the predicted value which validated the performance of the proposed CBCPW geometry used for radio frequency integrated circuit interconnects and filter applications.     

低阻硅衬底上形成的低损耗共平面波导传输线

在厚膜多孔硅 (PS) /氧化多孔硅 (OPS)衬底上 ,结合聚酰亚胺涂层改善表面 ,研制低损耗、高性能射频 (RF) /微波 (MW)共平面波导CPW(CoplanarWaveguide) .通过在N和P型硅上形成不同厚度PS膜 ,并对其上的CPW进行分析比较 ,厚膜PS与石英的共面波导插入损耗非常接近 ,远小于在 2 0 0 0Ω·cm高阻硅上形成的多晶硅 -氧化硅组合衬底 :在 0 33GHz范围 ,插入损耗小于 5dB/ 1.2cm ;33 4 0GHz范围 ,小于 7.5dB/ 1.2cm .     

Ku-band antenna array feed distribution network with ferroelectric phase shifters on silicon

This paper presents the design, fabrication, and experimental results of a 1 : 4 monolithic power distribution network for Ku-band array antenna applications. The network integrated on a high-resistivity silicon (HRS) substrate surface stabilized by polysilicon consists of three Wilkinson power dividers, four dc blocking filters, and four coplanar waveguide (CPW)-to-microstrip (MS) transitions. Each output ports are fed with a barium-strontium-titanate phase shifter. It is found that the introduction of the polysilicon layer between the oxide and HRS reduces RF losses significantly, which will enable the monolithic integration of high-power controller modules onto silicon because of the existence of the oxide layer, preventing any degradation of RF performances. The individual components show insertion losses ranging from 0.4 to 2.6 dB at 15 GHz, and the interconnecting CPW lines result in a loss of 0.064 dB/mm. This network was successfully integrated with MS patch antennas monolithically, showing good performance of 32-dB return loss at 14.85 GHz, and 10/spl deg/ beam-steering capability.     

High transmission gain inverted-F antenna on low-resistivity Si for wireless interconnect

Inverted-F antennas of 2-mm axial length are designed and fabricated on a low-resistivity silicon substrate (10 /spl Omega//spl middot/cm) using a post back-end-of-line process. For the first time, their performances are measured up to 110 GHz for wireless interconnects. Results show that a sharp resonance can be seen at 61 GHz for the antenna, and a high transmission gain of -46.3 dB at 61 GHz is achieved from the pair of inverted-F antennas at a separation of 10 mm on a standard 10 /spl Omega//spl middot/cm silicon wafer of 750-/spl mu/m thickness.     

The influence of finite conductor thickness and conductivity onfundamental and higher-order modes in miniature hybrid MIC's (MHMIC's)and MMIC's

The effect of finite metallization thickness and finite conductivity on the propagation characteristics of conductor-backed CPW on thin substrate is rigorously analyzed. A self-consistent approach is used together with the method of lines (MoL) to determine the propagation constant, losses and field distribution of the fundamental and first two higher-order modes in coplanar waveguides (CPWs) with finite metallization thickness and lossy backmetallization. The method used is general and can be applied to miniature MHMICs and MMICs including lossy semiconductor substrate. It is shown that the onset of higher-order modes limits the usable frequency range of conductor-backed CPWs. The analysis also includes microstrip transmission lines on thin substrate material. It is demonstrated that a resistive strip embedded into the microstrip ground plane may potentially be useful in the design of integrated planar attenuators     

DC isolation and RF dissipation loss of coplanar waveguide on GaAs multi conductive Layers bombarded by H/sup +/ and Fe/sup +/ ions

This letter explores the dc isolation and radio frequency (RF) dissipation loss of coplanar waveguide (CPW) lines of H/sup +/ and Fe/sup +/ ion bombarded GaAs multi conductive epitaxial layers. It is demonstrated that although a sheet resistivity as high as 10/sup 8/ /spl Omega/sq has been achieved by ion bombardment, showing excellent dc isolation, the RF dissipation loss of gold metallized CPW lines on the bombarded multi conductive epitaxial layers are higher than that on a semi-insulating GaAs substrate, especially at higher frequencies (0.5 dB/cm higher at 50 GHz). This is probably caused by deep level trappings due to the ion bombardment.     

Wafer-level packaging technology for high-Q on-chip inductors and transmission lines

In the current trend toward portable applications, high-Q integrated inductors have gained considerable importance. Hence, much effort has been spent to increase the performance of on-chip Si inductors. In this paper, wafer-level packaging (WLP) techniques have been used to integrate state-of-the-art high-Q on-chip inductors on top of a five-levels-of-metal Cu damascene back-end of line (BEOL) silicon process using 20-/spl Omega//spl middot/cm Si wafers. The inductors are realized above passivation using thick post-processed low-K dielectric benzocyclobutene (BCB) and Cu layers. For a BCB-Cu thickness of 16 /spl mu/m/10 /spl mu/m, a peak single-ended Q factor of 38 at 4.7 GHz has been measured for a 1-nH inductor with a resonance frequency of 28 GHz. Removing substrate contacts slightly increases the performance, though a more significant improvement has been obtained by combining post-processed passives with patterned ground shields: for a 2.3-nH above integrated-circuit (above-IC) inductor, a 115% increase in Q/sub BW//sup max/ (37.5 versus 17.5) and a 192% increase in resonance frequency (F/sub res/: 12 GHz versus 5 GHz) have been obtained as compared to the equivalent BEOL realization with a patterned ground shield. Next to inductors, high-quality on-chip transmission lines may be realized in the WLP layers. Losses below -0.2 dB/mm at 25 GHz have been measured for 50-/spl Omega/ post-processed coplanar-waveguide lines, above-IC thin-film microstrip lines have measured losses below -0.12 dB/mm at 25 GHz.     

基于QMSIW小型化带通滤波器设计

为有效减小X波段基片集成波导(SIW)滤波器的尺寸和插入损耗,提出了基于四分之一模基片集成波导(QMSIW)和共面波导(CPW)混合结构的小型化带通滤波器。为了提高滤波器的选择性和带外抑制,将两个CPW合并到两个级联的QMSIW谐振器中,由于两个CPW谐振器之间的耦合是电耦合,有助于产生两个传输零点,因而具有较高的选择性。该小型化滤波器尺寸仅为8.1 mm×15.4 mm,中心频率为8.7 GHz,相对带宽是16.1%,仿真测得插入损耗为0.83 dB,带外抑制大于40 dB。     

Ultrawideband characteristics of fractal dipole antennas integrated on Si for ULSI wireless interconnects

Ultrawideband characteristics of Sierpinski carpet fractal antennas fabricated on silicon substrates with the resistivities of 2290, 79.6, and 10 /spl Omega//spl middot/cm were investigated. The return losses lower than -10 dB and high transmission gains of approximately -14 dB were obtained for the antennas with 10-mm distance on the Si substrate with the resistivity of 2290 /spl Omega//spl middot/cm in the frequency range from 18 to 26.5 GHz. Gaussian monocycle pulses with 70 ps pulsewidth were transmitted in the Si substrates successfully and the corresponding voltage gains were -23, -26, and -39 dB for the Si resistivities of 2290, 79.6, and 10 /spl Omega//spl middot/cm, respectively.     

Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits

This paper introduces floating shields for on-chip transmission lines, inductors, and transformers implemented in production silicon CMOS or BiCMOS technologies. The shield minimizes losses without requiring an explicit on-chip ground connection. Experimental measurements demonstrate Q-factor ranging from 25 to 35 between 15 and 40 GHz for shielded coplanar waveguide fabricated on 10 /spl Omega//spl middot/cm silicon. This is more than a factor of 2 improvement over conventional on-chip transmission lines (e.g., microstrip, CPW). A floating-shielded, differentially driven 7.4-nH inductor demonstrates a peak Q of 32, which is 35% higher than an unshielded example. Similar results are realizable for on-chip transformers. Floating-shielded bond-pads with 15% less parasitic capacitance and over 60% higher shunt equivalent resistance compared to conventional shielded bondpads are also described. Implementation of floating shields is compatible with current and projected design constraints for production deep-submicron silicon technologies without process modifications. Application examples of floating-shielded passives implemented in a 0.18-/spl mu/m SiGe-BiCMOS are presented, including a 21-26-GHz power amplifier with 23-dBm output at 20% PAE (at 22 GHz), and a 17-GHz WLAN image-reject receiver MMIC which dissipates less than 65 mW from a 2-V supply.