A high-speed low-power Hi-CMOS 4K static RAM

A high-speed low-power CMOS fully static, 4096 word by 1 bit random-access memory (RAM) has been developed, which contains a bipolar-CMOS (BCMOS) circuit on the same chip. The device is realized using low-power-oriented circuit design and high-performance CMOS technology utilizing 3-µm gate length. The fabricated 4K static RAM has an address access time of 43 ns and a power dissipation of 80 mW.     

High-speed low-power Darlington ECL circuit

Presents an ECL circuit with a Darlington configured dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array application. The dynamic current source provides a large dynamic current during the switching transient to improve the power delay of the logic stage (current switch). A novel self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1 mW/gate, the circuit offers 28% improvement in the loaded (FI/FO=3, C_L=0.3 pF) delay and 42% improvement in the load driving capability compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed     

A high-speed low-power 4096 x 1 bit bipolar RAM

Describes a 4096-word by 1-bit TTL static bipolar RAM with a typical address access time of 25 ns and power dissipation of 350 mW. Emphasis is given to circuit techniques which made the high performance possible. These techniques are: variable impedance cell (VIC) with low standby current capable of fast switching of digit lines, cell margin increasing circuitry which increases the operating margin of the cell with low standby current, sharing of only one pair of read current sources by 64 pairs of digit lines, and Darlington word drivers causing fast switching of word lines. The process and device structure are mentioned briefly.     

A low-power sub 100 ns 256K bit dynamic RAM

A 256K-word /spl times/ 1-bit NMOS dynamic RAM using 2-/spl mu/m design rules and MoSi/SUB 2/ gate technology is described. A marked low-power dissipation of 170 mW (5 V V/SUB cc/, 260-ns cycle time) has been achieved by using a partial activation scheme. Optimized circuits exhibit a typical CAS access time of 34 ns. For the purpose of optimizing circuit parameters, an electron beam tester was successfully applied to observe the internal timing of real chips. Laser repairable redundancy with four spare rows and four spare columns is implemented for yield improvement.     

High-speed low-power charge-buffered active-pull-down ECI circuit

A high-speed, low-power, charge-buffered active-pull-down ECL (emitter-coupled logic) circuit is described. The circuit features a charge-buffered coupling between the common-emitter node of the switching transistors and the base of an active-pull-down n-p-n transistor. This coupling scheme provides a much larger dynamic current than what can be reasonably achieved through the capacitor coupling and a DC path to alleviate the AC-testing requirement. Furthermore, the dynamic current is utilized effectively by the logic stage, thus allowing a reduction in the power consumption of the logic stage without sacrificing the switching speed. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 37% improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed     

High-speed low-power cross-coupled active-pull-down ECL circuit

This paper presents a high-speed low-power cross-coupled active-pull-down ECL (CC-APD-ECL) circuit. The circuit features a cross-coupled active-pull-down scheme to improve the power-delay of the emitter-follower stage. The cross-coupled biasing scheme preserves the emitter-dotting capability and requires no extra biasing circuit branch and power for the active-pull-down transistor. Based on a 0.8 μm double poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 1.7× improvement in the loaded (FI/FO=3, C_L=0.3 pF) delay, 2.1× improvement in the load driving capability, and 3.5× improvement in the dotting delay penalty compared with the conventional ECL circuit. The design considerations of the circuit are discussed     

A low-power half-delay-line fast skew-compensation circuit

A fast skew-compensation circuit is useful for a chip to safely recover from the halt state because it can quickly compensate the clock skew induced by the on-chip clock driver. A low-power half-delay-line fast skew-compensation circuit (HDSC) is proposed in this work. The HDSC circuit features several new design techniques. The first is a new measure-and-compensate architecture, with which the HDSC circuit gains advantages including an enlarged operation frequency range, more robust operation, more accurate phase alignment, higher scalability for using advanced technologies, and lower power consumption, as compared to the conventional fast skew-compensation circuits. The second is a frequency-independent phase adjuster, with which the delay line can be shortened by half and the maximal power consumption is reduced accordingly if the clock signal has a 50% duty cycle. The third is a fine delay cell, which is used to accompany the half-delay-line, comprising of minimum-sized coarse delay cells, to effectively reduce the static phase error. Extensive circuit simulations are carried out to prove the superiority of the proposed circuit. In addition, an HDSC test chip is implemented for performance verification at high frequencies. The test chip is designed based on a 0.35-/spl mu/m CMOS process, and has a coarse cell delay of 220 ps. It works successfully between 600/spl sim/800 MHz, as designed, with a power consumption of 25/spl sim/36 /spl mu/W/MHz. When measured at 616.9 and 791.6 MHz, the static phase error is 76.8 and 124.5 ps, respectively.     

电流自动可调低功耗LED驱动电路

LED光源作为新型绿色环保光源,具有寿命长,发光效率高,高亮度以及工作电压低等优点。基于LED驱动电路的过温保护以及降低功耗要求,本文设计了一种用正温敏电阻来自动调节LED驱动电流以及降低采样电阻功耗的LED驱动电路,与常用的LED驱动电路相比,其优点在于:在温度达到保护点时,驱动电流不是直接降为零,而是在不被人眼明显发觉光变的前提下,LED驱动电流随系统温度的增加而适当的降低,因此,更适应照明等领域。本文所选取的LED驱动电流为ILED=350mA,LED灯阵列由M×N矩阵形式组成。     

低功耗无线收发电路系统设计

目前,无线通信技术发展极其迅速,随之引起系统功耗不断上升。因此人们近几年来对无线通信网络中各方面的低功耗技术进行了深入的研究,使节能成为无线通信发展的一个重要方向。设计了低功耗无线收发电路系统,采用STM32L151系列超低功耗芯片和UTC4432系列无线通信模块作为核心电路系统,通过软件设计及调试实现整个低功耗收发电路系统功能。结果表明:采用合适的微控制器和无线通信模块对于控制无线收发电路系统的功耗有着极其重要的作用,再加上对软件编程的控制,能够使整个系统的功耗大幅度降低。     

A low-power integrated circuit for remote speech recognition

In this paper, a low-power, low-voltage speech processing system is presented. The system is intended to he used in remote speech recognition applications where feature extraction is performed on terminal and high-complexity recognition tasks and moved to a remote server accessed through a radio link. The proposed system is based on a CMOS feature extraction chip for speech recognition that computes 15 cepstrum parameters, each 8 ms, and dissipates 30 μW at 0.9-V supply. Single-cell battery operation is achieved. Processing relies on a novel feature extraction algorithm using 1-bit A/D conversion of the input speech signal. The chip has been implemented as a gate array in a standard 0.5-μm, three-metal CMOS technology. The average energy required to process a single word of the TI46 speech corpus is 10 μJ. It achieves recognition rates over 98% in isolated-word speech recognition tasks     

Niobium-based integrated circuit technologies

Metallurgical and electrical properties of Nb and NbN films for use as Josephson junction electrodes and wiring layers are investigated. The crystallographic and superconducting properties necessary for Nb-based integrated circuit processes are clarified. Tunnel barrier structures of NbN-Nb oxide-NbN (Pb alloy) and Nb-Al oxide-Nb Josephson junctions have been analyzed and correlated with junction characteristics and critical current uniformity. It was found that the surface structure of a base electrode should be smooth to ensure that Josephson junctions have low leakage current and uniform critical current distribution. New types of Josephson junctions with artificial tunnel barriers such as amorphous Si or Mg oxide are reviewed. A variety of Josephson junction structures or processes have been developed for Nb-based Josephson integrated circuits in order to improve circuit performance. These include junction miniaturization, planarization, and stacked junction structures. These structures are mainly intended for Nb-Al oxide-Nb Josephson circuits. The Nb-Al oxide-Nb Josephson junction technology is by far the most advanced and has been used in logic and memory circuits, for example a 4-bit×4-bit parallel multiplier, a Josephson logic gate array, a 16-bit arithmetic logic unit, a 4-bit microprocessor, and 1-kb and 4-kb memory circuits     

High-bit-rate low-power decision circuit using InP-InGaAs HBT technology

We have successfully designed and fabricated a high-bit-rate low-power decision circuit using InP-InGaAs heterojunction bipolar transistors (HBTs). Its main design feature is the use of a novel master-slave D-type flip-flop (MS-DFF) as the decision circuit core to boost the operating speed. We achieved error-free operation at a data rate of up to 60 Gb/s using an undoped-emitter InP-InGaAs HBT with a cutoff frequency f/sub T/ of approximately 150 GHz and a maximum oscillation frequency f/sub max/ of approximately 200 GHz. Our decision circuit operates approximately 15% faster than one with a conventional MS-DFF core. We also achieved 90-Gb/s operation with low power consumption of 0.5 W using an InP-InGaAs DHBT exhibiting f/sub T/ and f/sub max/ of 232 and 360 GHz, respectively. These results demonstrate that InP-based HBTs and our novel MS-DFF are attractive for making ultrahigh-performance ICs for future optical communications systems operating at bit rates of 100 Gb/s or more.     

A low-power rail-to-rail input-range linear delay element circuit

Delay elements are one of the key components in many time-domain circuits such as time-based analog-to-digital converters. In this paper, a new rail-to-rail current-starved delay element is proposed which not only presents good linearity for the voltage-delay curve over the input range of ground to supply voltage, but also it consumes a dynamic power only during the transition times without consuming any static power. The proposed delay element is designed and simulated in a 0.13-µm CMOS technology with a supply voltage of 1.2 V. Post-layout simulation results demonstrate that the proposed circuit has a linear voltage-delay transfer function with a voltage-to-time gain of −1.33 ps/mV. Moreover, when samples of a full-scale sin-wave input signal are applied to the proposed circuit with a clock frequency of 100 MHz, the power consumption is 30 µW, and signal-to-noise-and-distortion ratio (SNDR) of the output delay times is 30.4 dB, making it suitable for use in a time-based analog-to-digital converter with up to 5-bit resolution.     

A low-power RF integrated circuit for implantable sensors

A low-power low-voltage analog signal processing circuit has been designed, fabricated, and tested. The circuit is capable of processing an analog sensor current and producing an ASK modulated digital signal with modulating signal frequency proportional to the sensor current level. An on-chip regulator has been included to stabilize the supply voltage received from an external RF power source. The circuit can operate with a power supply as low as 1 V and consumes only about 20 μW of power, which is therefore very suitable for implantable biomedical applications. The whole chip was laid out and fabricated in a 0.35 μm bulk CMOS technology. Experimental results show good agreement with the simulation results.     

A high-performance, low-power complementary coupled BiCMOS circuit

Reported is a new complementary technique of full-swing BiCMOS circuit design which, though employs a p-n-p, allows the use of n-p-n-only drivers. The simulated results of this new circuit compare favorably among several representative BiCMOS circuits     

A low-power circuit block for digital telephone exchanges

An integrated static 128 bit serial memory with logic circuitry at its input and transmission line drivers at its output is described. It works at a supply voltage of ?2 V ± 17%. Its power dissipation is 90 mW, and its maximum clock frequency is 40 MHz. Chip size is 3 × 4 mm².     

Efficient switched-capacitor common-mode feedback circuit for high-speed low-power amplifiers

A new switched-capacitor (SC) common-mode feedback (CMFB) circuit for fully-differential operational amplifiers (op-amps) is presented. By reducing the amplifier capacitive load with respect to conventional SC-CMFB schemes, the proposed solution guarantees a significant improvement of the op-amp speed performance. A typical SC integrator employing the new CMFB has also been designed in 0.35 μm CMOS technology. Simulation results show that, for a given power consumption, the op-amp settling time can be about halved by using the proposed CMFB instead of the conventional one.     

新型的嵌入式LCD显示系统低功耗技术

随着多媒体在手持移动设备中的广泛应用，包含了显示缓存，显示控制模块，显示背光电路和显示屏的LCD（Liquid Crystal Display）显示系统在系统总功耗中占据了主要地位。提出了一种在文本浏览或使用编辑器时，降低显示系统功耗来达到减低总体功耗的系统设计，它利用新的动态色深调整，缓存驻留，关闭主存的方法使得总体功耗降低了20％～30％。     

Simple oscillators-based readout circuit for low-power biomedical implant system

This paper reports a wireless sensor readout circuit for continuous physiological parameters monitoring including a potentiostat, a data generation unit and a frequency-shift-keying (FSK) modulator unit with the low drop-out (LDO) regulator for biomedical implant system. The potentiostat can generate an output potential of 0.7?V for the data generation unit. The data generation unit is designed based on a relaxation oscillator scheme and can be used to sense a current signal from any amperometric biomedical sensor and convert the signal to a square waveform in which the frequency of the square wave signal is proportional to the sensor current. FSK modulation scheme has been selected for wireless transmission. Designed with a very simple ring oscillator, this modulator integrates the modulation functionality into the oscillator itself by using the data signal to control the oscillation frequency. The prototype circuits have been fabricated in a 0.35???m bulk complementary metal-oxide semiconductor (CMOS) process. Working with a regulated 1.8?V supply, the potentiostat consumes only 2???A of current while the data generation unit can generate around 15.7?kHz output frequency with an input current of 1???A. The FSK modulator consumes a total current of around 19???A for a carrier frequency around 1?MHz. An off-chip demodulator is constructed to demodulate the data signal from the FSK modulator and the demodulated signal has less than 1.6?% variation of frequency.     

一种低功耗无线瓦斯传感器节点硬件电路的设计

能耗是制约无线传感器网络节点寿命的关键因素。无线瓦斯传感器节点因其传感元件的功耗远高于无线收发模块和微处理器,从而使其能耗问题更加突出。本文采用宽电压低功耗单片机C61F120和工作状态可控的直流稳压器件ME3101,设计了电源控制电路,以控制节点处于工作/休眠交替状态,降低节点能耗。最后对整个节点电路进行了能耗分析。结果表明,本文所给出的设计方法大大延长了节点的工作寿命。