Very-high-speed silicon bipolar transistors with in-situ dopedpolysilicon emitter and rapid vapor-phase doping base

We present a detailed study of the performance of very-high-speed silicon bipolar transistors with ultra-shallow junctions formed by thermal diffusion. Devices are fabricated with double-polysilicon self-aligned bipolar technology with U-groove isolation on directly bonded SOI wafers to reduce the parasitic capacitances. Very thin and low resistivity bases are obtained by rapid vapor-phase doping (RVD), which is a vapor diffusion technique using a source gas of B₂H₆. Very shallow emitters are formed by in-situ phosphorus doped polysilicon (IDP) emitter technology with rapid thermal annealing (RTA). In IDP emitter technology, the emitters are formed by diffusion from the in-situ phosphorus doped amorphous silicon layer. Fabricated transistors are found to have ideal I-V characteristics, large current gain and low emitter resistance for a small emitter. Furthermore, a minimum ECL gate delay time of 15 ps is achieved using these key techniques. Analyses of the high performance using circuit and device simulations indicate that the most effective delay components of an ECL gate are cut-off frequency and base resistance. A high cut-off frequency is achieved by reducing the base width and active collector region. In this study, RVD is used to achieve both high cut-off frequency and low base resistance at the same time     

A CMOS mismatch model and scaling effects

In this letter a novel single-pair mismatch model for short-channel MOS devices is developed, and scaling effects of mismatch distributions are investigated based on the model. The mismatch effect is modeled with threshold voltage, current factor, source resistance, and body factor mismatches. SPICE mismatch simulation is defined with mismatch parameters extracted from the model for accurate offset estimation in circuit simulation. Scaling effects with device size are investigated based on statistical mismatch data, and the results indicate that CMOS mismatch is induced by both local edge roughness and global variations. In addition, a √n-law model is developed for modeling gate-finger dependence of mismatch     

Impact of technology scaling and process variations on RF CMOS devices

Inspired by the huge improvement in the RF properties of CMOS devices, RF designers are invading the wireless market with all-CMOS RF transceivers and system-on-chip implementations. In this work, the impact of technology scaling on the RF properties of CMOS; frequency properties, noise performance, linearity, stability, and non-quasi static effects is investigated to provide RF designers with an insight to the capabilities of future CMOS technologies. Moreover, the RF frequency performance of CMOS is investigated under the influence of process variations for different CMOS generations. Using the BSIM4 model, it is found that future CMOS technologies have high prospects in the RF industry and will continue challenging other technologies in the RF domain to be the dominant technology for RF transceivers and system-on-chip implementations.     

Future CMOS scaling and reliability

The goals and constraints of MOSFET scaling are reviewed, and the role of reliability constraints is highlighted. It is concluded that judicial shrinking of MOSFET device dimensions can sustain the historical trend of scaling through the 0.09-μm (4-Gb SRAM) generation of technology, which may be used for IC production in the year 2010. Power supply voltage reduction plus the desire for large transistor current will create a demand for ever thinner gate oxides that can withstand ever higher electric field. Built-in reliability must replace the traditional end-of-the-line reliability testing for future complex circuits. Circuit reliability simulation may be one of the necessary tools for achieving built-in reliability     

Vertical RESURF diodes manufactured by deep-trench etch and vapor-phase doping

A new technique to manufacture vertical reduced surface field (RESURF)/superjunction devices is presented, in which the alternating p-n-junctions in the drift region are formed by a combination of a trench etch and vapor-phase doping process. Electrical measurements on Schottky RESURF diodes exhibit breakdown voltages up to 160 V with an on-resistance of 182 m/spl Omega/.mm/sup 2/ using a 10 /spl mu/m n-type drift region doped at 7.5/spl middot/10/sup 15/ cm/sup -3/. We show experimentally that such a device concept is able to display specific on-resistance well below the one-dimensional silicon limit and is a good candidate to manufacture vertical power RESURF MOSFETs.     

Modeling physical limitations on junction scaling for CMOS

Accurate calculations of diffusion and ion-implantation processes in silicon require the utilization of complex steady-state physical models that include the effects of both vacancies and self-interstitials. A new one-dimensional computer program, PROSIM II, has been developed for use in experimental junction formation studies that impact on advanced MOS technologies. PROSIM II has been used to study the scaling limits of counter-doped junctions for CMOS using both conventional furnace annealing and rapid thermal annealing processes. It is found that double implants of boron and arsenic can be used to produce a minimum 3000-Å-deep junction and still satisfy sheet resistance requirements for a 1-µm process.     

Leakage scaling in deep submicron CMOS for SoC

In this paper, we demonstrate the effects of CMOS technology scaling on the high temperature characteristics (from 25°C to 125°C) of the four components of off-state drain leakage (I_off ) (i.e. subthreshold leakage (I_sub), gate edge-direct-tunneling leakage (I_EDT), gate-induced drain-leakage (I_GIDL), and bulk band-to-band-tunneling leakage (I_B-BTBT)). In addition, the high temperature characteristics of I_off with reverse body bias (V_B) for the further reduction of the standby leakage are also demonstrated. The discussion is based on the data measured from three CMOS logic technologies (i.e., low-voltage and high performance (LV), low-power (LP), and ultra-low-power (ULP)) and three generations (0.18 μm, 0.15 μm, and 0.13 μm). Experiments show that the optimum V_B, which minimizes I_off, is a function of temperature. The experiments also show that for CMOS logic technologies of the next generations, it is important to control I_B-BTBT and I_GIDL by reducing effective doping concentration and doping gradient. It seems that in order to conform on-state gate leakage (I_G-on) and I_EDT specifications and to retain a 10-20% performance improvement at the same time, it is indispensable to use high-quality and high-dielectric-constant materials to reduce effective oxide thickness (EOT). The role of each leakage component in SRAM standby current (I_SB) is also analyzed     

Technology and device scaling considerations for CMOS imagers

This paper presents an analysis of the impact of device and technology scaling on active pixel CMOS image sensors. Using the SLA roadmap as a guideline, we calculate the device characteristics that are germane to the image sensing performance of CMOS imagers, and highlight the areas where the CIMOS imager technology may need to depart from “standard” CMOS technologies. The impact of scaling on those analog circuit performance that pertain to image sensing performances are analyzed. Our analyses suggest that while “standard” CMOS technologies may provide adequate imaging performance at the 2-1 μm generation without any process change, some modifications to the fabrication process and innovations of the pixel architecture are needed to enable CMOS to perform good quality imaging at the 0.5 μm technology generation and beyond. Finally, the challenges to the CMOS imager research community are outlined     

An efficient scaling procedure for domain CMOS logic

The layout area required by a domino CMOS gate to support a specific response-time performance for a particular capacitive load can be substantially reduced by scaling the NFET chain. A scaling procedure that requires little execution time is described and illustrated by its application to AND, AOI, and OAI domino CMOS gates. The procedure is equally applicable to other forms of dynamics logic     

A novel approach to silicon gate CMOS device scaling

A new approach is reported for fabricating scaled Si-gate CMOS devices using medium temperature (?900° C) LPCVD deposited SiO₂ as the dielectric interlayer. The film can be deposited from 850 to 1000°C using a graded temperature profile and optimum pressure. A maximum of 100 wafers with 8% variation of thickness per run has been achieved using the process described in this paper. The medium-temperature LPCVD SiO₂ film exhibited step-coverage as good as the conventional low temperature PSG film. Since the new film requires no high temperature treatment, the convetional Si-gate CMOS diffusion process has been used to obtain the micron and submicron junction depths that are required to fabricate scaled CMOS devices. Such a processing approach, converting a 5–6 μm geometry CMOS process to a 3 μm geometry CMOS process, is described.     

A VLSI-suitable Schottky-barrier CMOS process

Trenched Schottky-barrier (TSB) contact PMOS devices for use in latchup-free CMOS are examined in detail, and compared to Schottky-contact PMOS. Measurements and simulations show that the TSB structure has significant advantages in gain and current leakage over the Schottky-contact structure. CMOS using TSB PMOS may be made unconditionally free of latchup. The tradeoffs involving PMOS source-drain implant dose are made explicit and correlated to latchup measurements.     

A standardized method for CMOS unit process development

The multipurpose mask set described, which consists of three stepper reticles, contains 95% of all test structures required for CMOS process development and random defect detection, thereby dramatically reducing the stepper reticle inventory and the frequency of reticle changes. Realizing the mask set by two dozen standard unit processes minimizes the feedback loop for defect density data, parametric data and unit process data     

突破现有CMOS工艺限制的晶体管技术

很多人都有过这样尴尬的经历,当有急事需要打电话时,却发现手机没电了,而身边又没有固定电话,如果Cornell大学的研究人员成功了,今后,你将不会再碰到这种尴尬事。Cornell大学的一个研究小组将放射材料与MEMS（微型机电系统）悬臂和电路结合在一起,将核能转变为电能,这种能量源的半衰期大约为100年,基于这种技术的新电池可谓是能“永久”供电的电池。近日,     

Supply and threshold voltage scaling for low power CMOS

This paper investigates the effect of lowering the supply and threshold voltages on the energy efficiency of CMOS circuits. Using a first-order model of the energy and delay of a CMOS circuit, we show that lowering the supply and threshold voltage is generally advantageous, especially when the transistors are velocity saturated and the nodes have a high activity factor, In fact, for modern submicron technologies, this simple analysis suggests optimal energy efficiency at supply voltages under 0.5 V. Other process and circuit parameters have almost no effect on this optimal operating point. If there is some uncertainty in the value of the threshold or supply voltage, however, the power advantage of this very low voltage operation diminishes. Therefore, unless active feedback is used to control the uncertainty, in the future the supply and threshold voltage will not decrease drastically, but rather will continue to scale down to maintain constant electric fields     

CMOS scaling into the nanometer regime

Starting with a brief review on 0.1-μm (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling     

Temperature scaling for 35 nm gate length high-performance CMOS

It is commonly assumed that reducing the source–drain extension (SDE) junction depth is a key element for next-generation technology nodes. This can either be achieved by reducing the implantation energy or by reducing the thermal budget of the annealing process.In this paper, we will demonstrate that for transistors with an optimum balance between AC and DC performance a reduction in junction depth results only in very little improvement of the short-channel behaviour for spike anneals in the temperature range between 1050 and 1130 °C. On the other hand, reduced temperatures allow a reduction in in-die parameter variation and therefore improved product performance. There exists an optimum temperature which represents a compromise between reduced parameter variation and reduced dopant activation.For improved threshold voltage roll-off we introduced heavily doped low-energy halos, thus obtaining a physical gate length of 35 nm. The problem of increased drain resistance due to reduced activation at lower temperatures and counter-doping with high halo implant doses was solved by optimizing the lateral diffusion of the deep source–drain regions.All electrical data have been extracted from our triple-spacer transistor architecture, manufactured in 90-nm production technology. An outlook will be given for alternative device concepts, such as SPE and Laser anneal and asymmetric devices.     

A novel CMOS-compatible high-voltage transistor structure

A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, ie described. This device, which can be implemented using a standard CMOS process, is capable of handling high current densities without latching. The IBT exhibits a fivefold increase in current density compared to the lateral DMOS. A simple technique by which the switching speeds of the IBT can be improved by almost an order of magnitude without significantly compromising its current carrying capability is also presented.     

Design model for bulk CMOS scaling enabling accurate latchup prediction

The integration density of advanced bulk CMOS structures heavily depends on SCR type of latch up. Depending on the technology chosen the n-p-n-p-n-p interaction, which can be fired by noise, destroys tile stored information or even the chip itself. This paper presents the first complete two-dimensional numerical analysis for a typical CMOS structure including latchup path in the "OFF," "ON," "firing" and "sustaining" mode. Results and experimental data are discussed and used to develop a simplified, yet accurate CMOS design model. This allows the calculation of the firing and sustaining edge depending on geometrical and processing data.     

Mechanism of doping gallium arsenide with carbon tetrachloride during organometallic vapor-phase epitaxy

The rates of decomposition of carbon tetrachloride (CCl₄), triethylgallium (TEGa), and tertiarybutylarsine (TBAs), and the rate of GaAs film growth, were measured as a function of the process conditions during organometallic vapor phase epitaxy. In addition, the reaction of CCl₄ with the GaAs(001) surface was monitored in ultrahigh vacuum using infrared spectroscopy, temperature-programmed desorption, and scanning tunneling microscopy. These experiments have revealed that CCl₄ adsorbs onto Ga sites, and decomposes by transferring chlorine ligands to other Ga atoms on the surface. Chlorine and gallium desorb from the surface as GaCl, while the carbon incorporates into the lattice. Triethylgallium is consumed by two competing reactions: GaAs film growth and GaCl etching. Depending on the V/III and IV/III ratios and temperature, the etch rate can be high enough to prevent any GaAs deposition.