InGaAs/InP DHBT technology and design methodology for over 40 Gb/soptical communication circuits

High-performance technologies and adequate design methodologies are required to address the needs of very high-speed ICs (VHSICs) for over 40 Gb/s optical communications. We describe improvements we have introduced in our InP DHBT technology, and how our design methodology has evolved, we show how it results in improved circuit designs, and present some recent results, with some considerations on measurement limitations     

40Gbit/s master-slave D-type flip-flop in InP DHBT technology

A D-type flip-flop (MS D-FF) fabricated in a self-aligned InP DHBT technology is presented. 40 Gbit/s on-wafer measurements (limited by measurement setup) show good rise/fall times, low time jitter, as well as important regenerating capabilities. Some important design aspects are highlighted     

InP DHBT technology and design methodology for high-bit-rateoptical communications circuits

High-bit-rate optical communication links require high performance circuits. Electrical time division multiplex (ETDM) single channel bit-rate of 40 Gb/s is at hand, due to recent progress in both technology and design methodology. Multilevel modulation format can be envisaged for ETDM transmission. An InP double heterojunction bipolar transistor technology is presented in this paper. The methodology used and tools developed with optical communications in mind are also discussed. Fabricated circuits are reported: 40 Gb/s multiplexer and demultiplexer, a 20 Gb/s driver, a 30 Gb/s selector-driver, a 22 Gb/s decision circuit, and a decision-decoding circuit for multilevel transmissions     

A 6-b 12-GSamples/s track-and-hold amplifier in InP DHBT technology

This paper presents a 6-b 12-GSample/s track-and-hold amplifier (THA) fabricated in an InP-InGaAs-InP double heterojunction bipolar transistor (DHBT) technology. The THA is intended for the front end of a high-speed analog-to-digital converter in a digital-based electronic polarization-mode dispersion compensation circuit for a 10-Gb/s optical receiver. With a high-speed switched emitter follower and clocked track-to-hold transition operation, it shows the signal bandwidth over 14 GHz and features a total harmonic distortion (THD) compatible with 6-b operation with input frequency of 6 GHz and a sampling frequency of 12 GHz. The THD increases better than -23 dB with a 12-GHz input signal of 1 V/sub pp/, corresponding to a 4-b resolution, under a differential clock of 12 GHz.     

A compact 43-GHz monolithic differential VCO in 0.5-/spl mu/m InP DHBT technology

A compact monolithic integrated differential voltage controlled oscillator (VCO) using 0.5-/spl mu/m emitter width InP/InGaAs double-heterostructure bipolar transistors with a total chip size of 0.42 mm /spl times/ 0.46 mm is realized by using cross-coupled configuration for extremely high frequency satellite communications system applications. The device performance of F/sub max/ greater than 320 GHz at a current density of 5 mA//spl mu/m/sup 2/ and 5-V BVceo allows us to achieve a low phase noise 42.5-GHz fundamental VCO with -0.67-dBm output power. The VCO exhibits the phase noise of -106.8 dBc/Hz at 1-MHz offset and -122.3 dBc/Hz at 10-MHz offset from the carrier frequency.     

3.21 ps ECL gate using InP/InGaAs DHBT technology

A new circuit configuration for an emitter-coupled logic (ECL) gate that can reduce propagation delay time has been demonstrated. Nineteen-stage ring oscillators were fabricated using InP/InGaAs double-heterojunction bipolar transistors (DHBTs) with cutoff frequency f/sub T/ and maximum oscillation frequency f/sub max/ of about 232 and 360 GHz, respectively, to evaluate the speed performance of the proposed ECL gate. The minimum propagation delay is 3.21 ps/gate. The proposed ECL gate is about 8% faster than the conventional ECL gate.     

Ultrahigh-speed direct digital synthesizer using InP DHBT technology

Direct digital synthesizers (DDS) offer advantages such as precise beam shaping and forming over conventional RF approaches. This paper discusses novel design and process techniques that enable direct digital synthesis of S-band output frequencies using our current InP double-heterojunction bipolar transistor technology with a cantilevered base layer and undercut collector. The DDS chip operates at the world record clock rate of 9.2 GHz and capable of generating sinewaves up to 4.56 GHz. It also demonstrates state-of-the-art phase noise of -140 dBc at a frequency offset of 1 kHz and a clock frequency of 2.5 GHz. Further design and process improvements will be implemented in future generation circuits that will enable synthesis of Ku-band frequencies.     

A 165-Gb/s 4:1 Multiplexer in InP DHBT Technology

This paper presents a 4:1 multiplexer fabricated in InP double heterojunction bipolar transistor (DHBT) technology. The multiplexer works up to 165 Gb/s at a supply voltage of$-hbox3.2~V$consuming 1.6 W. It is a half-rate multiplexer using a multi-phase clock architecture. The main design challenge was to ensure correct timing between clock and data signals.     

48 Gbit/s InP DHBT MS-DFF with very low time jitter

A master-slave D-type flip-flop (MS DFF) fabricated in a self-aligned InP DHBT technology is presented. The packaged circuit shows full-rate clock operation at 48 Gbit/s. Very low time jitter and good retiming capabilities are observed. Layout aspects, packaging and measurement issues are discussed in particular     

43 Gbit/s automatic gain control amplifier based on InP SHBT technology

A high bandwidth automatic-gain-control (AGC) amplifier has been designed and characterised. Fabricated in InP single-heterojunction-bipolar transistor (SHBT) technology, the measured bandwidth of the amplifier is 36 GHz with maximum small signal gain 22 dB. Capable of operating at 43 Gbit/s, this is believed to be the fastest AGC amplifier reported to date.     

All-Fiberized Dispersion-Managed Multichannel Regeneration at 43 Gb/s

We report on the simultaneous 2R regeneration of up to three 42.7-Gb/s wavelength-division-multiplexing channels in a simple dispersion-managed fiber section with signal quality improvements higher than 1.7 dB. The regenerator relies on self-phase modulation-induced spectral broadening of the optical channels inside the fiber section and subsequent bandpass filtering at shifted wavelengths, and it is experimentally investigated in single-, dual-, and three-channel operation using optical pulses of 33% duty cycle.      

Fully monolithic integrated 43 Gbit/s clock and data recoverycircuit in InP HEMT technology

A fully monolithic integrated 43 Gbit/s clock and data recovery circuit for optical fibre communication systems is described. The circuit is based on a phase-locked loop technique, and the input data signal is regenerated with the data-rate clock signal. The circuit was fabricated with 0.1 μm gate-length InAlAs/InGaAs/InP HEMTs, and error-free operation was confirmed for 2³¹-1 PRBS data signal at 43 Gbit/s     

带有复合掺杂层集电区的InP/InGaAs/InP DHBT直流特性分析

设计了一种新结构InP/InGaAs/InP双异质结双极晶体管(DHBT),在集电区与基区之间插入n -InP层,以降低集电结的导带势垒尖峰,克服电流阻挡效应.采用基于热场发射和连续性方程的发射透射模型,计算了n -InP插入层掺杂浓度和厚度对InP/InGaAs/InP DHBT集电结导带有效势垒高度和I-V特性的影响.结果表明,当n -InP插入层掺杂浓度为3×1019cm-3、厚度为3nm时,可以获得较好的器件特性.采用气态源分子束外延(GSMBE)技术成功地生长出InP/InGaAs/InP DHBT结构材料.器件研制结果表明,所设计的DHBT材料结构能有效降低集电结的导带势垒尖峰,显著改善器件的输出特性.     

带有复合掺杂层集电区的InP/InGaAs/InP DHBT直流特性分析

设计了一种新结构InP/InGaAs/InP双异质结双极晶体管(DHBT),在集电区与基区之间插入n+-InP层,以降低集电结的导带势垒尖峰,克服电流阻挡效应.采用基于热场发射和连续性方程的发射透射模型,计算了n+-InP插入层掺杂浓度和厚度对InP/InGaAs/InP DHBT集电结导带有效势垒高度和I-V特性的影响.结果表明,当n+-InP插入层掺杂浓度为3×1019cm-3、厚度为3nm时,可以获得较好的器件特性.采用气态源分子束外延(GSMBE)技术成功地生长出InP/InGaAs/InP DHBT结构材料.器件研制结果表明,所设计的DHBT材料结构能有效降低集电结的导带势垒尖峰,显著改善器件的输出特性.     

InP DHBT selector-driver with 2 X 2.7 V swing for 100 Gbit/s operation

An integrated selector-driver is designed for 100 Gbit/s operation and fabricated using 0.7 μm InP double-heterojunction bipolar transistor (DHBT) technology. The driver has a lumped architecture and operates in differential mode. Two complementary signals each with 2.7 V amplitude (3.2 V_{pp) have been measured at 100 Gbit/s.}     

4-bit adder-accumulator at 41-GHz clock frequency in InP DHBT technology

A 41-GHz 4-b adder-accumulator test circuit implemented in InP double heterojunction bipolar transistor (DHBT) technology using 624 transistors is reported. High clock rates are obtained by combining the logic functions into pipelined latches. The adder-accumulator contains a single-level parallel-gated carry circuit that is used as a step toward reduced power consumption. The carry circuit has a maximum clock frequency of 55 GHz. The accumulator architecture employs modular, pipelined 2-b adders and is cascadable to 2 N-bits. The test circuit includes a 4-b digital to analog converter (DAC) that facilitates demonstration of high-speed operation.     

Comparison of InP/InGaAs DHBT distributed amplifiers as modulator drivers for 80-Gbit/s operation

This paper compares three single-ended distributed amplifiers (DAs) realized in an in-house InP/InGaAs double heterojunction bipolar transistor technology featuring an f/sub t/ and f/sub max/ larger than 200 GHz. The amplifiers use five or eight gain cells with cascode configuration and emitter follower buffering. Although the technology is optimized for mixed-signal circuits for 80 Gbit/s and beyond, DA results could be achieved that demonstrate the suitability of this process for the realization of modulator drivers. The results are documented with scattering parameter, eye diagram, and power measurements. This includes amplifiers featuring a 3-dB bandwidth exceeding 80 GHz and a gain of over 10 dB. One of the amplifiers exhibits clear eyes at 80 Gbit/s with a gain of 14.5 dB and a voltage output swing of 2.4 V/sub pp/ limited by the available digital input signal. This amplifier delivers an output power of 18 dBm (5.1 V/sub pp/) at 40 GHz and 1-dB compression. Two amplifiers offer a tunable gain peaking, which can be used to optimize circuit performance and to compensate losses in the circuit environment. The results show that, using our InP/InGaAs technology, an integration of high-speed mixed-signal circuits (e.g., multiplexers) and high-power modulator drivers on a single chip is feasible.     

可达到40Gb/s的材料选择:SiGe与GaAs和InP的比较

对可达到 2 .5～ 40 Gb/s数据速率的 Si Ge与 Ga As和 In P材料进行了比较 ,还对各种材料和工艺的典型特征进行了分析