A low oversampling ratio 14-b 500-kHz ΔΣ ADC with aself-calibrated multibit DAC

Delta-sigma (ΔΣ) analog-to-digital converters (ADC's) rely on oversampling to achieve high-resolution. By applying multibit quantization to overcome stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14-bit 500-kHz ΔΣ ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2-μm CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date     

A fourth-order bandpass Δ-Σ modulator usingsecond-order bandpass noise-shaping dynamic element matching

This paper describes a multibit bandpass ΔΣ modulator (DSM) for a frequency-interleaved analog-to-digital (A/D) converter (ADC). A frequency-interleaved ADC using low oversampling ratio (OSR) DSMs is an attractive approach for broadband and high resolution A/D conversion. A multibit DSM is suitable for low-oversampling operation; however, the overall resolution of a multibit DSM is restricted by the accuracy of the internal D/A converter (DAC). Some methods have been reported for improving the internal DAC accuracy of a low-pass DSM, but no bandpass-shaping technique applicable to a bandpass DSM has been implemented, although some methods have been proposed by using simulation. This paper proposes a multibit bandpass DSM with bandpass noise-shaping dynamic element matching (BPNSDEM), which enables bandpass shaping to mismatch error of the internal DAC, and presents its implementation. The modulator was implemented in a 0.25-μm CMOS technology. It operates at a 2.5-V power supply and achieves a signal-to-noise ratio of 77.4 dB over a 250-kHz bandwidth centered at 566 kHz     

A 14-bit current-mode ΣΔ DAC based upon rotated dataweighted averaging

A new dynamic element matching (DEM) algorithm, referred to as rotated data weighted averaging (RDWA), is implemented in a third-order ΣΔ digital-to-analog converter (DAC) with 64× oversampling and a conversion bandwidth of 25 kHz. The systematic and random errors are considered in the design of the 14-bit converter. The ΣΔ DAC is fabricated in a 2-μm CMOS process and includes the on-chip reconstruction filter. The prototype was designed to test the performance of the DAC without DEM, with data weighted averaging (DWA), and with RDWA. The results show that the new RDWA algorithm is capable of achieving first-order noise shaping while eliminating the signal-dependent harmonic distortion present in DWA     

Multi-bit cascade ΣΔ modulator for high-speed A/Dconversion with reduced sensitivity to DAC errors

The authors present a ΣΔ modulator (ΣΔM) which combines single-bit and multi-bit quantisation in a cascade architecture to obtain high resolution with a low oversampling ratio. It is less sensitive to the nonlinearity of the digital-to-analogue (DAC) than those previously reported, thus enabling the use of very simple analogue circuitry with neither calibration nor trimming required     

Mismatch shaping for a current-mode multibit delta-sigma DAC

Mismatch shaping allows the use of multibit quantization in delta-sigma analog-to-digital converters and digital-to-analog converters (DAC's) since it noise-shapes the error caused by static element mismatch in a multibit DAC. In this paper, mismatch-shaping techniques for low-pass delta-sigma (ΔΣ) modulators are reviewed, and a mismatch-shaping technique for bandpass ΔΣ modulators is described. The dynamic error caused by frequent element switching is identified as a major source of error in a current-mode DAC with a continuous-time output. Modifying the mismatch-shaping algorithm to account for this effect yields a continuous-time ΔΣ DAC that is insensitive to both element mismatch and element switching dynamics. Experimental results confirm the effectiveness of the proposed techniques     

A 2.5-V sigma-delta modulator for broadband communicationsapplications

Oversampled sigma-delta (EA) modulators offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters. This paper explores how oversampling and feedback can be employed in high-resolution ΣΔ modulators to extend the signal bandwidth into the range of several megahertz when the oversampling ratio is constrained by technology limitations. A 2-2-1 cascaded multibit architecture suitable for operation from a 2.5-V power supply is presented, and a linearization technique referred to as partitioned data weighted averaging is introduced to suppress in-band digital-to-analog converter (DAC) errors. An experimental prototype based on the proposed topology has been integrated in a 0.5-μm double-poly triple-metal CMOS technology. Fully differential double-sampled switched-capacitor integrators enable the modulator to achieve 95-dB dynamic range at a 4-Msample/s Nyquist conversion rate with an oversampling ratio of 16. The experimental modulator dissipates 150 mW from a 2.5-V supply     

Deterministic analysis of oversampled A/D conversion and decodingimprovement based on consistent estimates

Discusses the deterministic analysis of oversampled A/D conversion (ADC), the properties derivable from such an analysis, and the consequences on reconstruction using nonlinear decoding. Given a band-limited input X producing a quantized version C, the authors consider the set of all input signals that are band-limited and produce C. They call any element of this set a consistent estimate of X. Regardless of the type of encoder (simple, predictive, or noise-shaping), they show that this set is convex, and as a consequence, any nonconsistent estimate can be improved. They also show that the classical linear decoding estimates are not necessarily consistent. Numerical tests performed on simple ADC, single-loop, and multiloop ΣΔ modulation show that consistent estimates yield a mean square error (MSE) that decreases asymptotically with the oversampling ratio faster than the linear decoding MSE by approximately 3 dB/octave. This implies an asymptotic MSE of the order of 𝒪(R/sup -(2n+2/)) instead of 𝒪(R/sup -(2n+1/)) in linear decoding, where R is the oversampling ratio and n the order of the modulator. Methods of improvement of nonconsistent estimates based on the deterministic knowledge of the quantized signal are proposed for simple ADC, predictive ADC, single-loop, and multiloop ΣΔ modulation     

An audio ADC Delta-Sigma modulator with 100-dB peak SINAD and102-dB DR using a second-order mismatch-shaping DAC

A second-order audio analog-to-digital converter (ADC) ΔΣ modulator using a second-order 33-level tree-structured mismatch-shaping digital-to-analog converter (DAC) is presented. Key logic simplifications in the design of the mismatch-shaping DAC encoder are shown which yield the lowest complexity second-order mismatch-shaping DAC known to the authors. The phenomenon of signal-dependent DAC noise modulation in mismatch-shaping DACs is illustrated, and a modified second-order input-layer switching block is presented which reduces inband DAC noise modulation by 6 dB. Implementation details and measured performance of the 3.3-V 0.5-μm single-poly CMOS prototype are presented. All 12 prototype devices achieve better than 100-dB signal-to-noise-and-distortion and 102-dB dynamic range over a 10-20 kHz measurement bandwidth     

A 1.8-V ΔΣ modulator interface for an electretmicrophone with on-chip reference

The design of a delta-sigma (ΔΣ) analog-to-digital converter (ADC) for direct voltage readout of an electret microphone is presented. The ADC is integrated on the same chip with a bandgap voltage reference and is designed to be packaged together with an electret microphone. Having a power consumption of 1.7 mW from a supply voltage of 1.8 V, the circuit is well suited for use in mobile applications. The single-loop, single-bit, fourth-order ΔΣ ADC operates at 64 times oversampling for a signal bandwidth of 11 kHz. The measured dynamic range is 80 dB and the peak signal-to-(noise+distortion) ratio is 62 dB. The harmonic distortion is minimized by using an integrator with an instrumentation amplifier-like input which directly integrates the 125-mV peak single-ended voltage generated by the microphone. A combined continuous-time/switched-capacitor design is used to minimize power consumption     

A third-order Δ-Σ modulator using second-ordernoise-shaping dynamic element matching

A multibit Δ-Σ modulator is an attractive way of realizing a high-accuracy, high-speed, and low-power data converter. However, the overall resolution of the modulator is determined by the internal digital-to-analog conversion (DAC) linearity. Methods for high-order noise shaping, noise-shaping dynamic element matching (NSDEM), have been proposed in order to overcome this drawback. However, a real implementation has not been realized until now. This paper presents the actual circuit configuration of a tree-structured NSDEM (TNSDEM) technique, which is applied to a multibit Δ-Σ DAC and analog-to-digital converter (ADC) using a nine-level internal DAC. This is the first report of a Δ-Σ ADC and DAC using the second-order NSDEM method. The test chip of the third-order Δ-Σ ADC realizes a signal bandwidth of 100 kHz and a dynamic range of 79 dB in the ADC and 80 dB in the DAC. The test chip only consumes 9.6 mW in the ADC and 5.2 mW in the DAC with a 2.7 V power supply     

A 50-MHz multibit sigma-delta modulator for 12-b 2-MHz A/Dconversion

The authors examine the application of oversampling techniques to analog-to-digital conversion at rates exceeding 1 MHz. A cascaded multibit sigma-delta (ΣΔ) modulator that substantially reduces the oversampling ratio required for 12-b conversion while avoiding stringent component matching requirements is introduced. Issues concerning the design and implementation of the modulator are presented. At a sampling rate of 50 MHz and an oversampling ratio of 24, an implementation of the modulator in a 1-μm CMOS technology achieves a dynamic range of 74 dB at a Nyquist conversion rate of 2.1 MHz. The experimental modulator is a fully differential circuit that operates from a single 5-V power supply and does not require calibration or component trimming     

Dynamic range extension technique for high-order ΣΔADCs by digital level control

A new architecture is presented for a high-order multi-bit ΣΔ ADC which does not require a precision multi-bit DAC in the feedback loop. Local digital level control is employed to extend integrator output dynamic range. A prototype fourth-order modulator is simulated with circuit non-idealities, showing an SNR of ~110 dB     

Digital estimation and correction of DAC errors in multibitΔΣ ADCs

An adaptive digital algorithm is described for acquiring and correcting the errors of the feedback DAC used in a multibit ΔΣ ADC. The method is highly accurate, and is particularly useful for wideband ADCs, where mismatch error shaping becomes ineffective     

A 10.7-MHz IF-to-baseband ΣΔ A/D conversion system forAM/FM radio receivers

ΣΔ modulation with integrated quadrature mixing is used for analog-to-digital (A/D) conversion-of a 10.7-MHz IF input signal in an AM/FM radio receiver. After near-zero IF mixing to a 165 kHz offset frequency, the I and Q signals are digitized by two fifth-order, 32 times oversampling continuous-time ΣΔ modulators. A prototype IC includes digital filters for decimation and the shift of the near-zero-IF to dc. The baseband output signal has maximum carrier-to-noise ratios of 94 dB in 9 kHz (AM) and 79 dB in 200 kHz (FM), with 97 and 82 dB dynamic range, respectively. The IM3 distance is 84 dB at full-scale A/D converter input signal. Including downconversion and decimation filtering, the IF A/D conversion system occupies 1.3 mm² in 0.25-μm standard digital CMOS. The ΣΔ modulators consume 8 mW from a 2.5-V supply voltage, and the digital filters consume 11 mW     

A CMOS analog front-end circuit for an FDM-based ADSL system

A CMOS analog front-end circuit for an FDM-based ADSL system is presented. The circuit contains all analog functions including AGC amplifiers, continuous-time band pass filters, ΣΔ AD/DA converters, and digital decimation and interpolation filters. On-chip automatic tuning of the bandpass filters provides more than 300% center frequency range with 1% frequency accuracy. The higher-order ΣΔ AD/DA converters achieve 12-b data conversion at 1.54 Msamples/s with an oversampling ratio of only 32. The 0.7 μm CMOS circuit measures 65 mm² and consumes 1.9 W from a single 5 V power supply     

Architecture optimization for energy-efficient resolution-scalable 8–12-bit SAR ADCs

Low power analog-to-digital converters (ADCs) in energy constrained devices, such as wireless sensor readout modules, often target dynamic resolution scalability with application context to reduce the average power consumption. This work implements such an 8–12-bit resolution scalable ADC, using an oversampling and noise-shaping successive approximating register (SAR) architecture. This architecture is selected for its high power efficiency after a detailed comparison of various resolution enhancing techniques within the SAR framework. Specifically, in this paper, three resolution enhancing techniques are reviewed and compared on their energy usage namely: the majority voting, the oversampling, and the oversampling with noise shaping SAR ADC. Furthermore, the proposed resolution scalable ADC simplifies the design of the noise shaping filter by enabling the use of a first order switched-capacitor low-pass filter for shaping the comparator noise and the in-band quantization noise. The ADC design also alleviates the matching concerns by using only an 8-bit capacitive digital-to-analog converter (DAC) for a maximum 12-bit resolution, or 11-bit effective number of bits (ENOB). The architecture can be configured to allow an operation from 8-bit traditional SAR ADC up to an 11-bit ADC by enabling the oversampling and noise shaping loops within the SAR architecture. This ADC is designed to operate with up to 320 kS/s and achieves a power scaling from 80 nW to 1.5 \(\upmu\)W, resulting in an steeper energy-ENOB scaling trend compared to state-of-the art resolution scalable ADCs.     

Chopper stabilised ΠΔΣ analogue to digitalconversion

A chopper stabilised ΠΔΣ ADC architecture is proposed. A chopper stabilised version of ΠΔΣ ADC, which has identical performances to the regular ΠΔΣ ADC but is immune to low frequency noises such as DC offsets, can be obtained without adding hardware complexities     

FPGA signal processing using sigma-delta modulation

FPGA devices maintain the flexibility of software-based solutions, while providing levels of performance that match, and often exceed ASIC solutions. There is a rich and expanding body of literature devoted to the efficient and effective implementation of digital signal processors using FPGA-based hardware. More often than not, the most successful of these techniques involves a paradigm shift away from the methods that provide good solutions in software programmable DSP systems. This article reports on the rich set of design opportunities that are available to the signal processing system designer through innovative combinations of ΣΔ modulation techniques and FPGA signal processing hardware. The applications considered include narrow-band filters, both single-rate and multi-rate; DC canceller; and ΣΔ modulation hybrid digital-analog control loops for simplifying carrier recovery, timing recovery, automatic gain control (AGC) loops in a digital communication receiver     

A 2.7-V 11.8-mW baseband ADC with 72-dB dynamic range for GSMapplications

A receive baseband analog-to-digital converter (ADC) for a GSM cellular radio system is presented. Low voltage and low power techniques have been applied across many aspects of the design. The circuit consists of two second-order double-sampled semi-bilinear ΣΔ modulators followed by two 576-tap digital finite-impulse response (FIR) GSM-channel filters with offset calibration. The complete ADC achieves a dynamic range of 72 dB and dissipates 11.8 mW from a 2.7-V supply. The area is 1.6 mm² in a 0.5-μm n-well double-poly triple-metal CMOS process     

Triangularly weighted zero-crossing detector providingΣΔ frequency-to-digital conversion

It is shown that for delta-sigma (ΣΔ) frequency-to-digital conversion (FDC) there is no need for a ΣΔ modulator, since a limited FM signal itself may be considered as an asynchronous ΣΔ bit-stream. By feeding the limited FM signal directly to a sinc² ΣΔ decimator, a triangularly weighted zero-crossing counter FDC is introduced, providing ΣΔ noise shaping. The results measured confirm the theory