Design of a low-power 3.5-GHz broad-band CMOS transimpedance amplifier for optical transceivers

This paper describes a novel low-power low-noise CMOS voltage-current feedback transimpedance amplifier design using a low-cost Agilent 0.5-/spl mu/m 3M1P CMOS process technology. Theoretical foundations for this transimpedance amplifier by way of gain, bandwidth and noise analysis are developed. The bandwidth of the amplifier was extended using the inductive peaking technique, and, simulation results indicated a -3-dB bandwidth of 3.5 GHz with a transimpedance gain of /spl ap/60 dBohms. The dynamic range of the amplifier was wide enough to enable an output peak-to-peak voltage swing of around 400 mV for a test input current swing of 100 /spl mu/A. The output noise voltage spectral density was 12 nV//spl radic/Hz (with a peak of /spl ap/25 nV//spl radic/Hz), while the input-referred noise current spectral density was below 20 pA//spl radic/Hz within the amplifier frequency band. The amplifier consumes only around 5 mA from a 3.3-V power supply. A test chip implementing the transimpedance amplifier was also fabricated using the low-cost CMOS process.     

GaAs-based high-gain direct-coupled distributed preamplifier using active feedback topology

A single-chip ultra-high gain distributed amplifier (DA) was developed using commercial GaAs PHEMT foundry for 40-Gb/s base band applications. Two seven-section DAs are directly coupled using a lumped dc level-shift circuit. The dc bias level of the second-stage DA can be tuned using the level-shift circuit for optimum gain. The gain of each DA stage has been optimized using a novel active feedback cascode topology, which allows the gain bandwidth product to be maximized while avoiding instability problems. The fabricated single-chip DA with a size of 2.1 mm /spl times/ 2.3 mm showed a high gain of 28 dB, and an average noise figure of 4.6 dB with a 41 GHz bandwidth. The corresponding transimpedance gain was 62 dB/spl Omega/ and the input noise current density was 14.5 pA//spl radic/Hz. The gain bandwidth product (GBWP) is 1030 GHz, which corresponds to the highest performance using GaAs technology for 40 Gb/s applications.     

Bipolar monolithic amplifiers for a gigabit optical repeater

Main amplifier, AGC amplifier, and preamplifier ICs have been designed and fabricated using an advanced silicon bipolar process to provide the required characteristics of repeater circuits for a gigabit optical fiber transmission system. The bipolar technology used involved a separation width of 0.3 /spl mu/m between the emitter and the base electrode. New circuit techniques were also used. The differential type main amplifier has a peaking function which can be varied widely by means of DC voltage supplied at the outside IC terminal. A bandwidth which can be varied to about three times the value for a nonpeaking amplifier is easily obtained. The gain and maximum 3-dB down bandwidth were 4 dB and 4 GHz, respectively. The main feature of the AGC amplifier is that the diodes are connected to the emitters of the differential transistor pair to improve the linearity. The maximum gain and 3-dB down bandwidth were 15 dB and 1.4 GHz, respectively, and a dynamic range of 25 dB was obtained. The preamplifier has a shunt-series feedback configuration. Furthermore, a gain and 3-dB down bandwidth of 22 dB and 2 GHz, respectively, were achieved with an optimum circuit design. The noise figure obtained was 3.5 dB.     

A power efficient differential 20-GHz low noise amplifier with 5.3-GHz 3-dB bandwidth

A 20-GHz differential two-stage low-noise amplifier (LNA) is demonstrated in a foundry digital 130-nm CMOS technology with 8-metal layers. This LNA has 20-dB voltage gain and /spl sim/5.5-dB noise figure at 20GHz with 24-mW power consumption. The measured IP/sub 1 dB/ and IIP/sub 3/ are -11 dBm and -4dBm. Compared to the previously published bulk CMOS LNAs operating above 20GHz, this LNA has exceptionally low power and current consumption especially considering its differential topology and wide bandwidth.     

An inductance enhancement technique and its application to a shunt-peaked 2.5 Gb/s transimpedance amplifier design

This brief presents a bandwidth enhancement technique that is applicable to gigahertz-range broadband circuits. Using the inductance enhancement technique proposed in this brief, a 2.5-Gb/s transimpedance amplifier (TIA) has been implemented based on a 0.35-/spl mu/m CMOS technology. With the input noise reduction, the TIA with the proposed active inductor loads improves the overall system performances including more that 90% increase in bandwidth. Measurements show the bandwidth of 1.73 GHz, transimpedance gain of 68 dB/spl Omega/, and the averaged input referred noise current of 3.3 pA//spl radic/Hz, respectively, while dissipating 50 mW of dc power.     

220-GHz metamorphic HEMT amplifier MMICs for high-resolution imaging applications

In this paper, the development of 220-GHz low-noise amplifier (LNA) MMICs for use in high-resolution active and passive millimeter-wave imaging systems is presented. The amplifier circuits have been realized using a well-proven 0.1-/spl mu/m gate length and an advanced 0.05-/spl mu/m gate length InAlAs/InGaAs based depletion-type metamorphic high electron mobility transistor technology. Furthermore, coplanar circuit topology in combination with cascode transistors was applied, leading to a compact chip size and an excellent gain performance at high millimeter-wave frequencies. A realized single-stage 0.05-/spl mu/m cascode LNA exhibited a small-signal gain of 10 dB at 222 GHz, while a 0.1-/spl mu/m four-stage amplifier circuit achieved a linear gain of 20 dB at the frequency of operation and more than 10 dB over the bandwidth from 180 to 225 GHz.     

Gigahertz-band high-gain low-noise AGC amplifiers in fine-line NMOS

The design and test results of a single-chip NMOS automatic gain control (AGC) amplifier are described. The amplifier has a maximum flat gain of 50 dB, dynamic range of 70 dB, and a noise figure of 11 dB. The flat response from near DC to a 3-dB bandwidth of 1 GHz does not require tuning of any peaking circuits. The chip is also capable of operating at 3 GHz with unity gain delivering -8 dBm into a 50-/spl Omega/ load. The global feedback scheme designed for this chip stabilizes it against large shifts in threshold voltage and ambient temperature variation of 170/spl deg/C. This feedback scheme can provide stable DC feedback for a forward amplifier gain of at least 60 dB. Application of this application in the design of low-noise high-speed fibre-optic systems is envisaged.     

Wideband CMOS transimpedance amplifier

A fully differential wideband CMOS transimpedance amplifier is presented. Simulation results of different inductive peaking configurations are shown. Measured performances give a 19 GHz bandwidth and 45 dB/spl Omega/ transimpedance gain at 6.5 mW power consumption.     

InAlAs/InGaAs/InP基PHEMTs小信号建模及低噪声应用

利用改进的小信号模型对采用100nmInAlAs/InGaAs/InP工艺设计实现的PHEMTs器件进行建模, 并设计实现了一款W波段单片低噪声放大器进行信号模型的验证。为了进一步改善信号模型低频S参数拟合差的精度, 该小信号模型考虑了栅源和栅漏二极管微分电阻, 在等效电路拓扑中分别用Rfs和Rfd表示.为了验证模型的可行性, 基于该信号模型研制了W波段低噪声放大器单片.在片测试结果表明:最大小信号增益为14.4dB@92.5GHz, 3dB带宽为25GHz@85-110GHz.而且, 该放大器也表现出了良好的噪声特性, 在88GHz处噪声系数为4.1dB, 相关增益为13.8dB.与同频段其他芯片相比, 该放大器单片具有宽3dB带宽和高的单级增益.     

60-GHz SOI CMOS traveling-wave amplifier with NF below 3.8 dB from 0.1 to 40 GHz

In this paper, the design and the results of a CMOS traveling-wave amplifier (TWA) optimized for minimum noise figure is presented. Design tradeoffs and optimization guidelines for maximum operation frequency, gain and minimum noise are discussed by means of analytical calculations and simulations. The MMIC is fabricated using digital 90-nm silicon on insulator (SOI) technology and requires a chip area of only 0.3 mm/sup 2/. At a supply voltage of 2 V and a supply current of 66 mA, a gain of 9.7 dB/spl plusmn/1.6 dB is measured over a frequency range from 10 to 59 GHz. Toward dc, the gain increases up to 16 dB. The unity gain cutoff frequency is 71 GHz. At 20 and 40 GHz, the circuit has a 1-dB output compression point of 12.5 and 9.5 dBm, respectively. From 0.1 to 40 GHz, a noise figure below 3.8 dB is measured. The results are achieved at source/load impedances of 50 /spl Omega/ and include the pad parasitics. To the author's knowledge, the TWA has by far the lowest noise figure achieved for a silicon-based amplifier with comparable bandwidth.     

Low-power InP/GaAsSb/InP DHBT cascode transimpedance amplifier with GBP/P/sub dc/ of 7.2 GHz/mW

A low-power high gain-bandwidth monolithic cascode transimpedance amplifier using novel InP/GaAsSb/InP DHBT technology was investigated. The amplifier exhibited state-of-the-art performance of 17.3 dB gain, 12 GHz bandwidth, 55 dB/spl Omega/ transimpedance, and a corresponding gain-bandwidth of 6.7 THz/spl Omega/ while consuming only 12.2 mW DC power. It also achieved good gain-bandwidth-product per DC power figure-of-merit (GBP/P/sub dc/) of 7.2 GHz/mW     

A Reflected-Wave Ruby Maser with K-Band Tuning Range and Large Instantaneous Bandwidth

A novel maser concept is outlined and a unique design described which permits wide bandwidth and waveguide tuning range by employing four stages cascaded via cryogenically cooled circulators. Theoretical considerations for gain, bandwidth, gain ripple, and noise temperature are included. Operated on a chased-cycle helium refrigerator with a superconducting persistence-mode magnet, the four-stage amplifier is tunable from 18.3 to 26.6 GHz with 30 dB of net gain and achieves 240 MHz of 3-dB bandwidth near the center of this band. The measured noise temperature is 13/spl plusmn/2 K referred to the room-temperature input flange. Applications are foreseen utilizing cooled parametric downconverters and upconverters with this amplifier at IF to extend the low-noise performance up to millimeter frequencies and down to L-band for radio astronomy and planetary spacecraft communication.     

A 0.5-8.5 GHz fully differential CMOS distributed amplifier

A fully integrated fully differential distributed amplifier with 5.5 dB pass-band gain and 8.5 GHz unity-gain bandwidth is described. The fully differential CMOS circuit topology yields wider bandwidth than its single-ended counterpart, by eliminating the source degeneration effects of parasitic interconnect, bond wire, and package inductors. A simulated annealing CAD tool underpins the parasitic-aware methodology used to optimize the design including all on-chip active and passive device and off-chip package parasitics. Mixed-mode S-parameter measurement techniques used for fully differential circuit testing are reviewed. Integrated in 1.3/spl times/2.2 mm/sup 2/ in a standard 0.6 /spl mu/m CMOS process, the distributed amplifier dissipates 216 mW from a single 3 V supply.     

A miniature Q-band low noise amplifier using 0.13-/spl mu/m CMOS technology

A miniature Q-band low noise amplifier (LNA) using 0.13-/spl mu/m standard mixed signal/radio frequency complementary metal-oxide-semiconductor (CMOS) technology is presented in this letter. This three-stage common source thin-film microstrip LNA achieves a peak gain of 20dB at 43GHz with a compact chip size of 0.525mm/sup 2/. The 3-dB frequency bandwidth ranges from 34 to 44GHz and the minimum noise figure is 6.3dB at 41GHz. The LNA outperforms all the reported commercial standard CMOS Q-band LNAs, with the highest gain, highest output IP3, and smallest chip size.     

220GHz低噪声放大器研究

基于IHP锗硅BiCMOS工艺,研究和实现了两种220 GHz低噪声放大器电路,并将其应用于220 GHz太赫兹无线高速通信收发机电路。一种是220 GHz四级单端共基极低噪声放大电路,每级电路采用了共基极（Common Base, CB）电路结构,利用传输线和金属-绝缘体-金属(Metal-Insulator-Metal, MIM)电容等无源电路元器件构成输入、输出和级间匹配网络。该低噪放电源的电压为1.8 V,功耗为25 mW,在220 GHz频点处实现了16 dB的增益,3 dB带宽达到了27 GHz。另一种是220 GHz四级共射共基差分低噪声放大电路,每级都采用共射共基的电路结构,放大器利用微带传输线和MIM电容构成每级的负载、Marchand-Balun、输入、输出和级间匹配网络等。该低噪放电源的电压为3 V,功耗为234 mW,在224 GHz频点实现了22 dB的增益,3 dB带宽超过6 GHz。这两个低噪声放大器可应用于220 GHz太赫兹无线高速通信收发机电路。     

（英）D波段InP基高增益、低噪声放大芯片的设计与实现

利用90-nm InAlAs/InGaAs/InP HEMT工艺设计实现了两款D波段（110~170 GHz）单片微波集成电路放大器。两款放大器均采用共源结构,布线选取微带线。基于器件A设计的三级放大器A在片测试结果表明：最大小信号增益为11.2 dB@140 GHz,3 dB带宽为16 GHz,芯片面积2.6×1.2 mm2。基于器件B设计的两级放大器B在片测试结果表明：最大小信号增益为15.8 dB@139 GHz,3dB带宽12 GHz,在130~150 GHz频带范围内增益大于10 dB,芯片面积1.7×0.8 mm2,带内最小噪声为4.4 dB、相关增益15 dB@141 GHz,平均噪声系数约为5.2 dB。放大器B具有高的单级增益、相对高的增益面积比以及较好的噪声系数。该放大器芯片的设计实现对于构建D波段接收前端具有借鉴意义。     

A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end

A fully integrated 10-Gb/s optical receiver analog front-end (AFE) design that includes a transimpedance amplifier (TIA) and a limiting amplifier (LA) is demonstrated to require less chip area and is suitable for both low-cost and low-voltage applications. The AFE is fabricated using a 0.18-/spl mu/m CMOS technology. The tiny photo current received by the receiver AFE is amplified to a differential voltage swing of 400 mV/sub (pp)/. In order to avoid off-chip noise interference, the TIA and LA are dc-coupled on the chip instead of ac-coupled though a large external capacitor. The receiver front-end provides a conversion gain of up to 87 dB/spl Omega/ and -3dB bandwidth of 7.6 GHz. The measured sensitivity of the optical receiver is -12dBm at a bit-error rate of 10/sup -12/ with a 2/sup 31/-1 pseudorandom test pattern. Three-dimensional symmetric transformers are utilized in the AFE design for bandwidth enhancement. Operating under a 1.8-V supply, the power dissipation is 210 mW, and the chip size is 1028 /spl mu/m/spl times/1796 /spl mu/m.     

Precision measurement method for cryogenic amplifier noise temperatures below 5 K

We report precision measurements of the effective input noise temperature of a cryogenic (liquid-helium temperature) monolithic-microwave integrated-circuit amplifier at the amplifier reference planes within the cryostat. A method is given for characterizing and removing the effect of the transmission lines between the amplifier reference planes and the input and output connectors of the cryostat. In conjunction with careful noise measurements, this method enables us to measure amplifier noise temperatures below 5 K with an uncertainty of 0.3 K. The particular amplifier that was measured exhibits a noise temperature below 5.5 K from 1 to 11 GHz, attaining a minimum value of 2.3 K/spl plusmn/0.3 K at 7 GHz. This corresponds to a noise figure of 0.034 dB/spl plusmn/0.004 dB. The measured amplifier gain is between 33.4 dB/spl plusmn/0.3 dB and 35.8 dB/spl plusmn/0.3 dB over the 1-12-GHz range.     

A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique

A differential comparator that can sample 40-Gb/s signals and that operates off a single 1.2-V supply was designed and fabricated in 0.11-/spl mu/m standard CMOS technology. It consists of a front-end sampler, a regenerative stage, and a clocked amplifier to provide a small aperture time and a high toggle rate. The clocked amplifier employs a bandwidth modulation technique that switches the feedback gain to reduce the reset time while keeping the effective gain high. We confirmed that the comparator receives a 40-Gb/s data stream at a toggle rate of 10 GHz with bit error rate less than 10/sup -12/ by laboratory measurements.     

Low-power programmable gain CMOS distributed LNA

A design methodology for low power MOS distributed amplifiers (DAs) is presented. The bias point of the MOS devices is optimized so that the DA can be used as a low-noise amplifier (LNA) in broadband applications. A prototype 9-mW LNA with programmable gain was implemented in a 0.18-/spl mu/m CMOS process. The LNA provides a flat gain, S/sub 21/, of 8 /spl plusmn/ 0.6dB from DC to 6.2 GHz, with an input impedance match, S/sub 11/, of -16 dB and an output impedance match, S/sub 22/, of -10 dB over the entire band. The 3-dB bandwidth of the distributed amplifier is 7GHz, the IIP3 is +3 dBm, and the noise figure ranges from 4.2 to 6.2 dB. The gain is programmable from -10 dB to +8 dB while gain flatness and matching are maintained.