Task Partitioning in Programmable Logic Systems

The advent of low-cost microcomputer chip sets is having a dramatic impact on the direction of digital design. Except for very cost-sensitive products, most new designs are constructed utilizing programmable logic to replace more conventional random logic designs. The premise of this new logic form is based on the cost savings exhibited by solutions consisting of a small number of different LSI parts over those with many SSI/MSI parts performing the same functions. Low LSI parts costs are achieved by producing functions (e.g., RAM, ROM, processor, and I/O parts) with general utility so that each chip can be manufactured in very high volume. Logic functions are realized by specifying a set of step-by-step instructions which are executed sequentially by the processor.     

How ATE planning affects LSI manufacturing cost

To analyze the effects of automatic test equipment planning on total LSI manufacturing cost cost per chip, we simulate manufacturing cost by combining discrete event simulation and detailed parametric models of the LSI manufacturing system. This combination provides a more realistic evaluation than previous methods. For our example of ATE planning, we optimize the distribution of LSI testers between the wafer test process and final test process for cost per chip     

LORES-2: A Logic Reorganization System

LORES-2 is a logic reorganization system which greatly contributes to the effective automation of logic design. LORES-2 uses a macro-expansion technique to help designers transform printed-circuit assembly logic composed of SSI and MSI circuits into master-slice LSI logic circuits. The number of gates of the most reorganized LSI circuit falls within ± 20 percent of the number of gates of the original circuit. When ROMS and/or PLAs are not-allowed on the target LSI circuit, those elements are converted into optimized, multilevel random logic using logic minimization, factoring and macro-expansion techniques.     

The Mips R4000 processor

The R4000, a highly integrated, 64-b RISC microprocessor that provides a simple solution to the increasing demands on the size of address space while maintaining full compatibility with previous Mips processors, is described. The microprocessor's on-chip central processing unit, floating point unit, memory management unit, primary caches, system interface logic, secondary cache control logic with flexible interface, the programmable system interface for high-performance multiprocessor servers and low-cost desktop systems, the flexible multiprocessor support, and the 1.2 million transistors implemented in CMOS technology are discussed. The R4000's superpipelining techniques allow it to process more instructions simultaneously than the previous generation of microprocessors. It is shown that, according to SPEC benchmark tests, it achieves the highest performance of any microprocessor chip     

Integer inverse kinematics method using Fuzzy logic

In this paper, we propose an integer inverse kinematics method for multijoint robot control. The method reduces computational overheads and leads to the development of a simple control system as the use of fuzzy logic enables linguistic modeling of the joint angle. A small humanoid robot is used to confirm via experiment that the method produces the same cycling movements in the robot as those in a human. In addition, we achieve fast information sharing by implementing the all-integer control algorithm in a low-cost, low-power microprocessor. Moreover, we evaluate the ability of this method for trajectory generation and confirm that target trajectories are reproduced well. The computational results of the general inverse kinematics model are compared to those of the integer inverse kinematics model and similar outputs are demonstrated. We show that the integer inverse kinematics model simplifies the control process.     

Automated test generation using model checking: an industrial evaluation

In software development, testers often focus on functional testing to validate implemented programs against their specifications. In safety-critical software development, testers are also required to show that tests exercise, or cover, the structure and logic of the implementation. To achieve different types of logic coverage, various program artifacts such as decisions and conditions are required to be exercised during testing. Use of model checking for structural test generation has been proposed by several researchers. The limited application to models used in practice and the state space explosion can, however, impact model checking and hence the process of deriving tests for logic coverage. Thus, there is a need to validate these approaches against relevant industrial systems such that more knowledge is built on how to efficiently use them in practice. In this paper, we present a tool-supported approach to handle software written in the Function Block Diagram language such that logic coverage criteria can be formalized and used by a model checker to automatically generate tests. To this end, we conducted a study based on industrial use-case scenarios from Bombardier Transportation AB, showing how our toolbox CompleteTest can be applied to generate tests in software systems used in the safety-critical domain. To evaluate the approach, we applied the toolbox to 157 programs and found that it is efficient in terms of time required to generate tests that satisfy logic coverage and scales well for most of the programs.     

Dynamic Architectures: Problems and Solutions

A standardizable LSI microprocessor with on-chip configuration control directed by operating-system commands promises a series of computer sets dynamically matched to user-program characteristics.     

Toward hardware-redundant, fault-tolerant logic for nanoelectronics

This article provides an overview of several logic redundancy schemes, including von Neumann's multiplexing logic, N-tuple modular redundancy, and interwoven redundant logic. We discuss several important concepts for redundant nanoelectronic system designs based on recent results. First, we use Markov chain models to describe the error-correcting and stationary characteristics of multiple-stage multiplexing systems. Second, we show how to obtain the fundamental error bounds by using bifurcation analysis based on probabilistic models of unreliable gates. Third, we describe the notion of random interwoven redundancy. Finally, we compare the reliabilities of quadded and random interwoven structures by using a simulation-based approach. We observe that the deeper a circuit's logical depth, the more fault-tolerant the circuit tends to be for a fixed number of faults. For a constant gate failure rate, a circuit's reliability tends to reach a stationary state as its logical depth increases.     

Personal computers in automation systems

Historically, computer control of processes and experiments has been the domain of large scale industry and research organizations. For small quantity or ‘one off’ systems, the availability of the microprocessor and associated LSI and MSI logic components have lowered the cost of such automation and process control systems by perhaps an order of magnitude. In the case of large quantities, the cost reduction figures are much more dramatic, particularly where the system is realized on a specialized customized VLSI chip. Microprocessor control systems can be realized in a number of ways. This paper explores the conditions and environment in which a personal computer, such as the Commodore PET, can offer lower costs and simpler software and hardware development than systems designed from micromodules i.e. sets of printed circuit boards each performing a specific function.     

Microprocessor-based controllers for single and multiple batch digesters for pulping

Batch digesters are employed in paper mills for pulping, which consists basically of treating a fibrous raw material such as wood with suitable chemicals using steam under closely controlled conditions of digester temperature and pressure and steam flow, and comprises several operational stages. Conventionally pneumatic instruments and controllers have been in use for semi-automatic control of batch digesters. Full control has been achieved through minicomputers, but their high cost has deterred their widespread use. The microprocessor, because of its very low cost and small size, holds the key to computerized control of batch digesters on a wide scale.Not much work has been done on the development of microprocessor software and system hardware for this purpose. The present paper reports the development of 8-bit microprocessor based controllers for single and multiple batch digesters. The control logic adopted is akin to that employed in conventional controllers. The reported controllers were tested under laboratory simulated conditions for the want of an experimental/pilot batch digester.     

A Fully-Automated Electron Beam Test System for VLSI Circuits

A fully automated, stroboscopic electrobeam test system that analyzes the behavior of logic VLSI circuits, this system consists of a stroboscopic electron-beam tester combined with an LSI CAD system. LSI circuit design data, read from the CAD system, provides a designed map. The host computer performs interconnection pattern recognition by superimposing this map onto an observed stroboscopic SEM image. Then, once the circuit nodes for voltage waveform measurements are automatically determined on the superimposed map. Next, the electron beam is positioned on the actual circuit-under-test wires. These automatic processes result in measured waveforms, which are displayed on the host computer terminal. This system has been applied to a 2.3K-gate logic LSI circuits, and has been successful in locating the critical path. This system, coupled with the recently developed fault diagnostic electron-beam tester, Finder, constitutes a unified electron-beam test system.     

采用I2C器件扩展单片机的多机通讯

阐述了采用I^2C器件作为辅助器件，扩展单片机的查询式多机通讯功能。从而使单片机上串口可以用作其他用途，并减少了中断的使用。提高系统的可靠性。     

单相电动机正反转互锁控制电路研究

主要介绍了单相电动机正、反转的原理,阐述了常规单片机控制单相电动机正、反转电路的结构及实现方式,并分析了常规单片机控制电路存在的缺陷;通过对常规单片机控制逻辑电路的研究改进,实现了单相电动机正、反转控制的互锁控制逻辑。     

基于龙芯2F处理器的硬件验证平台的设计与实现

针对高性能处理器龙芯2F的逻辑验证和性能测试,本文设计和实现了一套硬件验证平台环境,既能验证处理器流片前的逻辑功能,也能测试处理器流片后的性能指标。实验结果表明,本文设计的硬件验证平台能够有效验证龙芯2F处理器的各项功能和性能指标。     

An Embedded Microprocessor for Intelligent Control

The conventional approach for the implementation of the knowledge base of a planning agent, on an intelligent embedded system, is solely of software nature. It requires the existence of a compiler that transforms the initial declarative logic program, specifying the knowledge base, to its equivalent procedural one, to be programmed to the embedded systems microprocessor. This practice increases the complexity of the final implementation (the declarative to sequential transformation adds a great amount of software code for simulating the declarative execution) and reduces the overall systems performance (logic derivations require the use of a stack and a great number of jump instructions for their evaluation). The design of specialized hardware implementations, which are only capable of supporting logic programs, in an effort to resolve the aforementioned problems, introduces limitations in their use in applications where logic programs need to be intertwined with traditional procedural ones in a desired application. In this paper, we exploit HW/SW codesign methods to present a microprocessor, capable of supporting hybrid applications using both programming approaches. We take advantage of the close relationship between attribute grammar (AG) evaluation and knowledge engineering methods to present a programmable hardware parser that performs logic derivations and combine it with an extension of a conventional RISC microprocessor that performs the unification process to report the success or failure of logic derivations. The extended RISC microprocessor is still capable of executing conventional procedural programs, thus hybrid applications can be implemented. The presented implementation increases the performance of logic derivations for the control inference process (experimental analysis yields an approximate 1000% – 10 times increase in performance) and reduces the complexity of the final implemented code through the introduction of an extended C language called C-AG that simplifies the programming of hybrid procedural-declarative applications.     

基于逻辑合一的访问控制规则描述

现有的访问控制规则描述方式不易表达一类主体、客体间具有包含关系的访问控制规则。针对此问题,提出 一种基于逻辑中合一思想的算法。算法首先将访问控制请求转换为逻辑提问,同时根据逻辑回答给出相应的访问控 制请求应答;然后使用事实描述访问控制规则中的各个要素,并通过在系统运行过程中对非ground事实的变量的动 态例化实现灵活的访问控制。最后,通过一个实例及分析说明了算法的有效性。     

A cost-effective RISC/DSP microprocessor for embedded systems

Applications in telecommunications or multimedia require a new generation of fast and flexible microprocessors. We present a 32-bit RISC microprocessor with extended functionality for digital signal processing that reduces overall system cost. Due to its optimized design with just 210,000 transistors, this low-cost, medium- to high-performance microprocessor is well suited for a wide range of embedded system applications     

Contributions of tester experience and a checklist guideline to the identification of categories and choices for software testing

An early step for most black-box testing methods is to identify a set of categories and choices (or their equivalents) from the specification. The identification is often performed in an ad hoc manner, thus the quality of categories and choices is in doubt. Poorly identified categories and choices will affect the comprehensiveness of test cases. In this paper, we describe several comparative studies using three commercial specifications and discuss the major results. The objectives of our studies are (a) to investigate the differences in the types and amounts of mistakes made between inexperienced and experienced software testers in an ad hoc identification approach and (b) to determine the extent of mistake reduction after discussing the mistakes with the software testers and providing them with an identification checklist.     

A Mechanically Checked Proof of Correctness of the AMD K5 Floating Point Square Root Microcode

We present a rigorous mathematical proof of the correctness of the floating point square root instruction of the AMD K5 microprocessor. The instruction is represented as a program in a formal language that was designed for this purpose, based on the K5 microcode and the architecture of its FPU. We prove a statement of its correctness that corresponds directly with the IEEE Standard. We also derive an equivalent formulation, expressed in terms of rational arithmetic, which has been encoded as a formula in the ACL2 logic and mechanically verified with the ACL2 prover. Finally, we describe a microcode modification that was implemented as a result of this analysis in order to ensure the correctness of the instruction.     

Data flow control in an online system

Valuable computer time and memory space is saved by using a microprocessor (Mostek F8) to control the flow of data in a multichannel laboratory data collection system.Special digital converters transmit serial BCD signals with added control bits. The F8 is used to translate the BCD to binary, reject unwanted data, and provide buffer storage. Full buffers of 128 bytes cause their contents to be transmitted to a DEC LSI11 installation for writing to its floppydisc in 64-word arrays. Should several buffers become full nearly simultaneously, additional ones are made available until all are cleared. This is done on a priority basis such that those carrying end of run signals are sent first, allowing the computer to proceed with further processing.The microprocessor program is held on disc files and is loaded into the F8 by a simple computer program together with some additional constants that are given by the operator during a question and answer sequence. The extra versatility this gives is enhanced by the resulting ability to make considerable program changes without having to change a PROM, which needs to hold only a bootstrap.