共查询到20条相似文献,搜索用时 93 毫秒
1.
Seong-Jun Song Sung Min Park Hoi-Jun Yoo 《Solid-State Circuits, IEEE Journal of》2003,38(7):1213-1219
A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-/spl mu/m standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2 ps rms and 47 ps pk-pk for 2/sup 31/-1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10/sup -6/ for 2/sup 31/-1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply. 相似文献
2.
This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-μm digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 27-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8×0.4 mm2 相似文献
3.
Tan Kok-Siang Mohd-Shahiman Sulaiman Mamun Reaz Chuah Hean-Teik Manoj Sachdev 《Analog Integrated Circuits and Signal Processing》2007,51(2):101-109
A fully-integrated 5 Gb/s PLL-based clock and data recovery circuit based on a linear half-rate phase detector (PD) architecture
is presented. Data retiming performed by the linear PD provides practically no systematic offset for the operating frequency
of interest. The circuit was designed in a 0.18 μm CMOS process and occupies an active area of 0.2 × 0.32 mm2. The CDR exhibits an RMS jitter of ± 1.2 ps and a peak-to-peak jitter of 5 ps. The power dissipation is 97 mW from a 1.8 V
supply. 相似文献
4.
Hamamoto T. Furutani K. Kubo T. Kawasaki S. Iga H. Kono T. Konishi Y. Yoshihara T. 《Solid-State Circuits, IEEE Journal of》2004,39(1):194-206
This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-/spl mu/m DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified. 相似文献
5.
A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-μm CMOS technology in an area of 1.1×0.9 mm2, the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28×10-6, with random data input of length 223-1. The power dissipation is 72 mW from a 2.5-V supply 相似文献
6.
Kreienkamp R. Langmann U. Zimmermann C. Aoyama T. Siedhoff H. 《Solid-State Circuits, IEEE Journal of》2005,40(3):736-743
This paper presents a 10-Gb/s clock and data recovery (CDR) circuit for use in multichannel applications. The module aligns the phase of a plesiochronous system clock to the incoming data by use of phase interpolation. Thus, coupling between voltage-controlled oscillators (VCOs) in adjacent channels can be avoided. The controller for the phase interpolator is realized with analog circuitry to overcome the speed and phase resolution limitations of digital implementations. Fabricated in a 0.11-/spl mu/m CMOS technology the module has a size of 0.25/spl times/1.4 mm/sup 2/. The power consumption is 220 mW from a supply voltage of 1.5 V. The CDR exceeds the SDH/SONET jitter tolerance specifications with a pseudo random bit sequence of length 2/sup 23/-1 and a bit-error rate threshold of 10/sup -12/. The re-timed and demultiplexed data has an rms jitter of 3.2 ps at a data rate of 2.7 Gb/s. 相似文献
7.
A high speed CMOS signaling interface for application in multiprocessor interconnection networks has been developed. The interface utilizes I-V push-pull drivers, a delay line phase-locked loop (PLL), and sampling of the data on both edges of the clock. In order to increase the noise immunity of the reception, a current-integrating input pin sampler is used to receive the incoming data. Chips fabricated in a 0.8 μm CMOS technology achieve transfer rates of 740 Mb/s/pin operating from a 3.3 V supply with a bit error rate of less than 10-14 相似文献
8.
A 10-Gb/s phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a half-rate phase/frequency detector with automatic data retiming. Fabricated in 0.18-/spl mu/m CMOS technology in an area of 1.75/spl times/1.55 mm/sup 2/, the circuit exhibits a capture range of 1.43 GHz, an rms jitter of 0.8 ps, a peak-to-peak jitter of 9.9 ps, and a bit error rate of 10/sup -9/ with a pseudorandom bit sequence of 2/sup 23/-1. The power dissipation excluding the output buffers is 91 mW from a 1.8-V supply. 相似文献
9.
A phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a quarter-rate bang-bang phase detector. The oscillator is based on differential excitation of a closed-loop transmission line at evenly spaced points, providing half-quadrature phases. The phase detector employs eight flip-flops to sample the input every 12.5 ps, detecting data transitions while retiming and demultiplexing the data into four 10-Gb/s outputs. Fabricated in 0.18-/spl mu/m CMOS technology, the circuit produces a clock jitter of 0.9 ps/sub rms/ and 9.67 ps/sub pp/ with a PRBS of 2/sup 31/-1 while consuming 144 mW from a 2-V supply. 相似文献
10.
11.
12.
Wei-Hung Chen Guang-Kaai Dehang Jong-Woei Chen Shen-Iuan Liu 《Solid-State Circuits, IEEE Journal of》2001,36(10):1498-1505
In this paper, a serial link for AS-memory systems fabricated in a 0.25-μm standard CMOS technology is presented. This serial link utilizes a pulsewidth modulation (PWM) technique. By transmitting the PWM-encoded signal with periodic rising edges, the clock can be implicitly embedded in the data stream and the associating overhead needed in clock/data recovery circuits can, be mitigated. The symbol rate is 200 Mb/s and the equivalent data rate is 400 Mb/s. The PWM transceiver dissipates 66.5 mW at a 2.5-V supply voltage. It is suitable for the AS-memory systems in which the pin count is limited and elaborate clock/data recovery circuits are not required 相似文献
13.
The PLL circuit described here performs the function of data and clock recovery for random data patterns by using a sample-and-hold technique, and four component circuits (a phase comparator, a delay circuit, a voltage-controlled oscillator, and a S/H switch with a low-pass-filter) were specially designed to further stabilize the PLL operation. A test chip fabricated using Si bipolar process technology demonstrated error-free operation with an input of 223-1 PRBS data at 156 Mb/s. The rms data pattern jitter was reduced to only 1.2 degrees with only an external power supply bypass capacitor 相似文献
14.
《Solid-State Circuits, IEEE Journal of》1996,31(8):1170-1176
A power and area efficient CMOS clock/data recovery circuit designed for a wide range of applications in high-speed serial data communications is described. It uses an analog phase-locked loop (PLL) to generate the high-speed clocks with an absolute rms jitter of less than 60 ps and a digital PLL which is designed to minimize chip area and power consumption to recover the clock and data signals from the incoming data stream. Fabricated in a 0.8 μm single-polysilicon, double-metal CMOS process, the digital PLL only consumes 45 mW at 125 Mb/s from a single 5 V supply, while the analog PLL consumes 92 mW. The chip area is 1.7 mm2 for the digital PLL and 0.44 mm2 for the analog PLL. It can handle an input data rate up to 280 Mb/s 相似文献
15.
Hatakeyama A. Mochizuki H. Aikawa T. Takita M. Ishii Y. Tsuboi H. Fujioka S. Yamaguchi S. Koga M. Serizawa Y. Nishimura K. Kawabata K. Okajima Y. Kawano M. Kojima H. Mizutani K. Anezaki T. Hasegawa M. Taguchi M. 《Solid-State Circuits, IEEE Journal of》1997,32(11):1728-1734
This paper describes the key technologies used in a 256-Mb synchronous DRAM with a clock access time of 1 ns. This DRAM is stable against temperature, voltage, and process variation through the use of a register-controlled digital delay-locked loop (RDLL). The total timing error of the RDLL is about 0.4 ns, sufficient for high frequency operation at 150 to 200 MHz. Unlike most conventional high-density DRAMs, the bit lines are placed above the storage capacitors in this DRAM to relax the design rules of the core area. The noise issues were analyzed and resolved to help implement the technology for mass production of 0.28- to 0.24-μm 200-MHz DRAMs 相似文献
16.
Perrott M.H. Tewksbury T.L. III Sodini C.G. 《Solid-State Circuits, IEEE Journal of》1997,32(12):2048-2060
A digital compensation method and key circuits are presented that allow fractional-N synthesizers to be modulated at data rates greatly exceeding their bandwidth. Using this technique, a 1.8-GHz transmitter capable of digital frequency modulation at 2.5 Mb/s can be achieved with only two components: a frequency synthesizer and a digital transmit filter. A prototype transmitter was constructed to provide proof of concept of the method; its primary component is a custom fractional-N synthesizer fabricated in a 0.6-μm CMOS process that consumes 27 mW. Key circuits on the custom IC are an on-chip loop filter that requires no tuning or external components, a digital MASH Σ-Δ modulator that achieves low power operation through pipelining, and an asynchronous, 64-modulus divider (prescaler). Measurements from the prototype indicate that it meets performance requirements of the digital enhanced cordless telecommunications (DECT) standard 相似文献
17.
A 156-Mb/s CMOS optical receiver for burst-mode transmission 总被引:1,自引:0,他引:1
In a point-to-multipoint fiber-optic subscriber system using TDMA (time division multiple access), the receiver should be able to handle burst-data packets with different amplitudes, Moreover, high-bit-rate operation is desired for multimedia communications. The operational speed is mainly restricted by the input parasitic capacitance of the preamplifier. Reducing the input impedance of the preamplifier widens its frequency bandwidth, and it makes high-speed operation possible. A multistaged preamplifier using feedforward phase compensation technique has been devised for small input impedance with stable operation at high frequency. Multistaged feedforward bias control is used for quick response to burst data, and the time constant is also reduced for high-speed operation. Using these design techniques, an optical receiver IC was fabricated using standard 0.5-μm CMOS technology. The instantaneous response receiver has high sensitivity of -35.6 dBm, a wide dynamic range of more than 26 dB for burst-mode optical input at 156 Mb/s, and requires no external adjustment. The use of standard CMOS technology and the freedom from external adjustment make it possible to build an inexpensive receiver module 相似文献
18.
A 2.5 Gbit/s monolithic clock and data recovery integrated circuit (CDR IC) based on a novel duplicated phase-locked loop (PLL) technique has been fabricated using 0.5 μm Si bipolar technology. This CDR IC operates more stably in that it can tolerate greater variations in temperature and supply voltage while continuing to meet the specifications for jitter characteristics stipulated in the ITU-T recommendations 相似文献
19.
Zhigong Wang 《电信纪事》1993,48(3-4):132-147
A regenerative data transmission system is briefly outlined. Some important aspects related to the data regeneration and the clock recovery, such as the forms, the spectra, the jitter and the measurements of the data and clock signal, are summarized. The principle and the ic realisation of dr is discussed. Optimal cr circuits are deduced. Its preprocessing part and three categories of the main processing part, i.e., with a passive filter, with a narrowband regenerative frequency divider and with a phase-locked loop, are studied in detail. All circuits discussed are designed for applications in multibitls optical transmission systems, and are mainly based on high-speed Si bipolar technologies. 相似文献
20.
Matano T. Takai Y. Takahashi T. Sakito Y. Fujii I. Takaishi Y. Fujisawa H. Kubouchi S. Narui S. Arai K. Morino M. Nakamura M. Miyatake S. Sekiguchi T. Koyama K. 《Solid-State Circuits, IEEE Journal of》2003,38(5):762-768
A 1-Gb/s/pin 512-Mb DDRII SDRAM has been developed using a digital delay-locked loop (DLL) and a slew-rate-controlled output buffer. The digital DLL has a frequency divider for DLL input, performs at an operating frequency of up to 500 MHz at 1.6 V, and provides internal clocking with 50% duty-cycle correction. The DLL has a current-mirror-type interpolator, which enables a resolution as high as 14 ps, needs no standby current, and can operate at voltages as low as 0.8 V. The slew-rate impedance-controlled output buffer circuit reduces the output skew from 107 to 10 ps. This SDRAM was tested using a 0.13-/spl mu/m 126.5-mm/sup 2/ 512-Mb chip. 相似文献