1.25Gbps串并并串转换接收器的低抖动设计

对1.25Gbps应用于千兆以太网的低抖动串并并串转换接收器进行了设计,应用了带有频率辅助的双环时钟数据恢复电路,FLL扩大了时钟数据恢复电路的捕捉范围。基于三态结构的鉴频鉴相从1.25Gbps非归零数据流中提取时钟信息,驱动一个三级的电流注入环形振荡器产生1.25GHz的低抖动时钟。从低抖动考虑引入了均衡器。该串并并串转换接收器采用TSMC0.35μm2P3M3.3V/5V混合信号CMOS技术工艺。测试结果表明了输出并行数据有较好的低抖动性能:1σ随机抖动(RJ)为7.3ps,全部抖动(TJ)为58mUI。     

A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC

A GaAs IC that performs clock recovery and data retiming functions in 2.5-Gb/s fiber-optic communication systems is presented. Rather than using surface acoustic wave (SAW) filter technology, the IC employs a frequency- and phase-lock loop (FPLL) to recover a stable clock from pseudo-random non-return-to-zero (NRZ) data. The IC is mounted on a 1-in×1-in ceramic substrate along with a companion Si bipolar chip that contains a loop filter and acquisition circuitry. At the synchronous optical network (SONET) OC-48 rate of 2.488 Gb/s, the circuit meets requirements for jitter tolerance, jitter transfer, and jitter generation. The data input ambiguity is 25 mV while the recovered clock has less than 2° rms edge jitter. The circuit functions up to 4 Gb/s with a 40-mV input ambiguity and 2° RMS clock jitter. Total current consumption from a single 5.2-V supply is 250 mA     

2.488 Gbit/s时钟数据恢复电路的设计

利用Cadence集成电路设计软件,基于SMIC 0.18 μm 1P6M CMOS工艺,设计了一款2.488 Gbit/s三阶电荷泵锁相环型时钟数据恢复(CDR)电路.该CDR电路采用双环路结构实现,为了增加整个环路的捕获范围及减少锁定时间,在锁相环(PLL)的基础上增加了一个带参考时钟的辅助锁频环,由锁定检测环路实时监控频率误差实现双环路的切换.整个电路由鉴相器、鉴频鉴相器、电荷泵、环路滤波器和压控振荡器组成.后仿真结果表明,系统电源电压为1.8V,在2.488 Gbit/s速率的非归零(NRZ)码输入数据下,恢复数据的抖动峰值为14.6 ps,锁定时间为1.5μs,功耗为60 mW,核心版图面积为566 μm×448μm.     

Bit rate and wavelength transparent all-optical clock recovery scheme for NRZ-coded PRBS signals

All-optical clock recovery from 40-Gb/s nonreturn-to-zero (NRZ) pseudorandom binary sequence data streams based on self-pulsating lasers is presented. A compact preprocessing circuit is utilized to convert an NRZ signal to a pseudoreturn-to-zero sequence before injecting into the optical clock. It comprises a semiconductor optical amplifier followed by a periodical wavelength-division-multiplexing demultiplexer filter. A stable sinusoidal clock signal with a root-mean-square jitter below 700 fs is detected at the output of the self-pulsating laser within data dynamic range of more than 8 dB. The performance of the all-optical clock recovery scheme is investigated by varying the bit rates between 39.81 and 43.02 Gb/s as well as for various wavelengths in the C-band.     

A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability

A 10-Gb/s CMU/CDR chip-set presenting multistandard compliance with SDH/SONET and 10-GbE specifications has been fabricated in a commercial SiGe BiCMOS technology. The clock multiplier unit (CMU) features dual reference clock frequency, and the phase tracking loop uses a charge pump with low common-mode current to minimize frequency ripple; the output jitter is below 80 mUIpp. The clock and data recovery (CDR) features a 20-mV-sensitivity limiting amplifier, a 2-DFF-based decision circuit to maximize clock phase margin (CPM) and a dual-loop phase-locked loop (PLL) architecture with external reference clock. A novel phase detector topology featuring a transition density factor compensation loop has been exploited to minimize jitter. Power consumption is 480 mW and 780 mW, respectively, for the two ICs, from 3.3-V and 2.5-V power supplies     

NRZ timing recovery technique for band-limited channels

Nonreturn-to-zero (NRZ) data, when transmitted over band-limited channels, suffer from the lack of zero crossings because the elongated tail of each pulse interferes with subsequent ones, causing intersymbol interference (ISI). An NRZ timing recovery technique working with a decision-feedback equalizer (DFE) recovers the clock from the equalized waveform and enables data transmission at a rate ten times higher than the channel bandwidth. The proposed timing recovery technique uses a data-triggered low-jitter phase detector to sustain phase locking even with 600 missing transitions, A data rate of 30 Mb/s in 3-MHz bandwidth is demonstrated with a peak-peak clock jitter of 2 ns using 2-μm CMOS     

10Gb/s NRZ码时钟信息提取电路

利用法国OMM IC公司的0.2μm G aA s PHEM T工艺,设计实现了10 G b/s NRZ码时钟信息提取电路。该电路采用改进型双平衡G ilbert单元的结构,引进了容性源极耦合差动电流放大器和调谐负载电路,大大提高了电路的性能。测试表明:在输入速率为9.953 28 G b/s长度为223-1伪随机序列的情况下,提取出的时钟的均方根抖动是1.18 ps,峰峰值抖动是8.44 ps。芯片面积为0.5 mm×1 mm,采用-5 V电源供电,功耗约为100 mW。     

Fully electrical 40-Gb/s TDM system prototype based on InP HEMTdigital IC technologies

This paper presents a fully electrical 40-Gb/s time-division-multiplexing (TDM) system prototype transmitter and receiver. The input and output interface of the prototype are four-channel 10-Gb/s signals. The prototype can be mounted on a 300-mm-height rack and offers stable 40-Gb/s operation with a single power supply voltage. InP high-electron mobility transistor (HEMT) digital IC's perform 40-Gb/s multiplexing/demultiplexing and regeneration. In the receiver prototype, unitraveling-carrier photodiode (UTC-PD) generates 1 V_pp output and directly drives the InP HEMT decision circuit (DEC) without any need for an electronic amplifier. A clock recovery circuit recovers a 40-GHz clock with jitter of 220 fs_pp from a 40-Gb/s nonreturn-to-zero (NRZ) optical input. The tolerable dispersion range of the prototype within a 1-dB penalty from the receiver sensitivity at zero-dispersion is as wide as 95 ps/nm, and the clock phase margin is wider than 70° over almost all the tolerable dispersion range. A 100-km-long transmission experiment was performed using the prototype. A high receiver sensitivity [-25.1 dBm for NRZ (2⁷-1) pseudorandom binary sequence (PRBS)] was obtained after the transmission. The 40-Gb/s regeneration of the InP DEC suppressed the deviation in sensitivity among output channels to only 0.3 dB. In addition, four-channel 40-Gb/s wavelength-division-multiplexing (WDM) transmission was successfully performed     

一种适用于NRZ数据的时钟数据恢复电路

提出了一种基于传统电荷泵锁相环结构的时钟数据恢复电路.采用一种适用于NRZ数据的新型鉴频鉴相器电路,以克服传统鉴频鉴相器在恢复NRZ信号时出现错误脉冲的问题,从而准确地恢复出NRZ数据.同时,对其他电路也采用优化的结构,以提高时钟数据恢复电路的性能.设计的电路可在1.1 V超低电压下工作,适合RF ID等需要低电压、低功耗的系统使用.     

A second-order semidigital clock recovery circuit based on injection locking

A compact (1 mm /spl times/ 160 /spl mu/m) and low-power (80-mW) 0.18-/spl mu/m CMOS 3.125-Gb/s clock and data recovery circuit is described. The circuit utilizes injection locking to filter out high-frequency reference clock jitter and multiplying delay-locked loop duty-cycle distortions. The injection-locked slave oscillator output can have its output clocks interpolated by current steering the injecting clocks. A second-order clock and data recovery is introduced to perform the interpolation and is capable of tracking frequency offsets while exhibiting low phase wander.     

A CMOS high-speed data recovery circuit using the matched delaysampling technique

This paper presents a scheme and circuitry for demultiplexing and synchronizing high-speed serial data using the matched delay sampling technique. By simultaneously propagating data and clock signals through two different delay taps, the sampler achieves a very fine sampling resolution which is determined by the difference between the data and clock delays. This high resolution sampling capability of the matched delay sampler can be used in the oversampling data recovery circuit. A data recovery circuit using the matched delay sampling technique has been designed and fabricated in 1.2-μm CMOS technology. The chip has been tested at 417 Mb/s [2.4 ns nonreturn to zero (NRZ)] input data and demultiplexes serial input data into four 104 Mb/s (9.6 ns NRZ) output streams with 800 mW power consumption at 4 V power supply. While recovering data, the sampling clock running at 1/4 of the data frequency is phase-tracking with the input data based on information extracted from a digital phase control circuit     

NMOS IC's for clock and data regeneration in gigabit-per-secondoptical-fiber receivers

The design and performance of two essential analog circuits in optical-fiber receivers is described. A time-interleaved decision circuit is capable of regenerating 35-mV nonreturn-to-zero (NRZ) data inputs to full logic levels at 1.1 Gb/s with 10^-11 bit error rate (BER), and a phase-locked loop (PLL) extracts the clock from a 2 ²³ long pseudorandom sequence at 1.5 Gb/s with 13-ps r.m.s. jitter. The two circuits have been implemented as 1-μm NMOS ICs, and in their core area dissipate 200 and 350 mW, respectively     

一种全速率线性25Gb/s时钟数据恢复电路

面向高速光通信系统的应用,提出了一种全速率线性25Gb/s时钟数据恢复电路(Clock and Data Recovery Circuit,CDRC)。CDRC采用了混频器型线性鉴相器和自动锁频技术来实现全速率时钟提取和数据恢复。在设计中没有使用外部参考时钟。基于45nm CMOS工艺,该CDR电路从版图后仿真结果得到:恢复25Gb/s数据眼图的差分电压峰峰值V_pp和抖动峰峰值分别为1.3V和2.93ps;输出25GHz时钟的差分电压峰峰值V_pp和抖动峰峰值分别为1V和2.51ps,相位噪声为-93.6dBc/Hz@1MHz。该芯片面积为1.18×1.07mm²,在1V的电源电压下功耗为51.36mW。     

2.5Gb/s 0.18μm CMOS时钟数据恢复电路

采用TSMC公司标准的0.18μm CMOS工艺,设计并实现了一个全集成的2.5Gb/s时钟数据恢复电路.时钟恢复由一个锁相环实现.通过使用一个动态的鉴频鉴相器,优化了相位噪声性能.恢复出2.5GHz时钟信号的均方抖动为2.4ps,单边带相位噪声在10kHz频偏处为-111dBc/Hz.恢复出2.5Gb/s数据的均方抖动为3.3ps.芯片的功耗仅为120mW.     

Simultaneous Demodulation and Clock-Recovery of 40-Gb/s NRZ-DPSK Signals Using a Multiwavelength Gaussian Filter

We demonstrate a novel optical circuit that has the potential of simultaneous demodulation and all-optical clock-recovery of 40-Gb/s wavelength-division-multiplexing nonreturn-to-zero differential phase-shift keying (NRZ-DPSK) signals. A key device of the circuit is an ad hoc periodic fiber Bragg grating filter that simultaneously demodulates the input signals and seeds a series of clock recovery circuits. We report the complete characterization of the proposed scheme in the whole-band using a tunable transmitter. The DPSK demodulated signals show enhanced resilience to chromatic dispersion with respect to the usual NRZ _ON-OFF keying format. On the other hand, the recovered clock signals are very stable and have around 200-fs root-mean-square time jitter.     

Analysis and equalization of data-dependent jitter

Data-dependent jitter limits the bit-error rate (BER) performance of broadband communication systems and aggravates synchronization in phase- and delay-locked loops used for data recovery. A method for calculating the data-dependent jitter in broadband systems from the pulse response is discussed. The impact of jitter on conventional clock and data recovery circuits is studied in the time and frequency domain. The deterministic nature of data-dependent jitter suggests equalization techniques suitable for high-speed circuits. Two equalizer circuit implementations are presented. The first is a SiGe clock and data recovery circuit modified to incorporate a deterministic jitter equalizer. This circuit demonstrates the reduction of jitter in the recovered clock. The second circuit is a MOS implementation of a jitter equalizer with independent control of the rising and falling edge timing. This equalizer demonstrates improvement of the timing margins that achieve 10/sup -12/ BER from 30 to 52 ps at 10 Gb/s.     

A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-/spl mu/m CMOS

This paper demonstrates a low-jitter clock multiplier unit that generates a 10-GHz output clock from a 2.5-GHz reference clock. An integrated 10-GHz LC oscillator is locked to the input clock, using a simple and fast phase detector circuit that overcomes the speed limitation of a conventional tri-state phase frequency detector due to the lack of an internal feedback loop. A frequency detector guarantees PLL locking without degenerating jitter performance. The clock multiplier is implemented in a standard 0.18-/spl mu/m CMOS process and achieves a jitter generation of 0.22 ps while consuming 100 mW power from a 1.8-V supply.     

A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator

A clock and data recovery (CDR) circuit with a novel two-mode phase comparator is proposed. The 10-Gb/s CDR integrated circuit (IC) operates both for consecutive identical digits (CID) and data transition density variations. This advance is achieved through the use of our novel two-mode phase comparator, which enables us to determine an optimal phase-locked loop parameter for various data patterns. Experimental results show that the jitter generation of the CDR IC is less than 7 pspp for a 2/sup 7/-1 pseudorandom bit sequence with up to 1024 CIDs. The results also show that the jitter transfer and jitter tolerance are unaffected by data transition density factors of between 1/8 and 1/2.     

A 10-Gb/s CMOS clock and data recovery circuit with a half-ratelinear phase detector

A 10-Gb/s phase-locked clock and data recovery circuit incorporates an interpolating voltage-controlled oscillator and a half-rate phase detector. The phase detector provides a linear characteristic while retiming and demultiplexing the data with no systematic phase offset. Fabricated in a 0.18-μm CMOS technology in an area of 1.1×0.9 mm², the circuit exhibits an RMS jitter of 1 ps, a peak-to-peak jitter of 14.5 ps in the recovered clock, and a bit-error rate of 1.28×10^-6, with random data input of length 2²³-1. The power dissipation is 72 mW from a 2.5-V supply     

利用光电振荡器实现10Gbit/s NRZ码时钟的直接提取和码型转换

本文所研究的光电振荡器（OEO）是一种高速光电混合环路，其振荡频率可以被锁定于外界信号的数据率，本文利用OEO首次实现10Gbit/s的非归零码（NRZ）时钟提取，获得了时间抖动小于0.4ps的时钟信号，测得OEO的注入锁定频率范围可达800kHz。实验中发现OEO中调制器的偏置电压对OEO的注入锁定范围有很大影响。合理控制OEO的工作条件，在进行时钟提取的同时，还可以实现NRZ码到RZ（归零）码的码型转化。将转换后的RZ码进行了160km传输，结果证明这种码型适合传输，该实验说明OEO可以用作不同码型光网络中间的码型转化节点。