A programmable architecture for OFDM-CDMA

Combining multicarrier (OFDM) and CDMA technologies is attractive for future wireless broadband communications and software radio realization. Based on the unified framework known as OFCDMA, we develop a programmable structure for OFDM-CDMA transceivers in spite of three different scenarios to combine OFDM and CDMA. By adjusting system parameters without changing the fundamental hardware and software architecture, various system scenarios can be implemented, which might serve as the foundation to design software radio     

A policy-based management architecture for active and programmable networks

Next generation networks must be capable of supporting a multitude of service providers that exploit an environment in which services are dynamically deployed and quickly adapted over a common heterogeneous physical infrastructure, according to varying and sometimes conflicting customer requirements. In this context, network management must become more flexible in order to cope with these emerging conditions. More specifically, new management architectures must offer service providers the freedom to manage their services according to their own policies and seamlessly extend management functionality as the only way to react to the introduction of new services. Based on a new business model that describes such an environment, we propose a policy-based management architecture that is extensible and operates in an active and programmable network. This management architecture is part of a new network architecture that was developed in the FAIN European Union research and development IST project.     

A programmable router architecture supporting control planeextensibility

The Internet is evolving from an infrastructure that provides basic communication services into a more sophisticated infrastructure that supports a wide range of electronic services such as virtual reality games and rich multimedia retrieval services. However, this evolution is happening only slowly, in part because the communication infrastructure is too rigid. In this article we present a programmable router architecture in which the control plane functionality of the router can be extended dynamically through the use of delegates. Delegates can control the behavior of the router through a well-defined control interface, allowing service providers and third-party software vendors to implement customized traffic control policies or protocols. We describe Darwin, a system that implements such an architecture. We emphasize the runtime environment the system provides for delegate execution and the programming interface the system exports to support delegates. We demonstrate the advantages of using this system with two delegate examples     

A programmable transport architecture with QoS guarantees

The emergence of distributed multimedia applications exhibiting significantly more stringent quality of service requirements than conventional data-oriented applications calls for new transport protocols with different characteristics to coexist and be integrated within single applications. The different delivery requirements posed by these diverse multimedia applications often imply the need for highly customized protocol implementations. Hence, application developers are faced with the threat of code obsolescence caused by the development of even newer delivery techniques. We present an object-oriented transport architecture that allows for dynamically binding a variety of protocol stacks on a per-call basis. By binding protocol stacks together, the special needs of the application can be met without the need to rewrite the code. This differs significantly from the traditional transport architecture which assumes preinstalled transport protocol stacks that cannot be customized. To illustrate some of the advantages provided by the architecture, we describe the transport component of the first reference implementation of the 150 MPEG-4 Delivery Multimedia Integration Framework and demonstrate how quickly it was implemented in our framework     

A scale database architecture for network services

A radical technology for databases, called the Datacycle architecture, which implements a relational model for network services and scales to support throughput of thousands of transactions per second is proposed. A set of data manipulation primitives useful in describing the logic network services is described. The use of the relational model together with an extended structured-query-language-like query language to describe 800 service, network automatic call distribution, and directory-assisted call completion services, is examined. The architectural constraints on the scalability of traditional database systems is reviewed, and an alternative, the Datacycle architecture is presented. The Datacycle approach exploits the bandwidth of fiber optics to circulate database contents among processing nodes (e.g. switching offices or other network elements) in a network, providing highly flexible access to data and controlling the administrative and processing overhead of coordinating changes to database contents. A prototype system operating in the laboratory is described. The feasibility of the Datacycle approach for both existing and future applications is considered     

Distributed mixed-signal architecture for programmable smart image sensors

Smart vision systems on a chip are promising for embedded applications. Currently, flexibility in the choice of integrated pre-processing tools is obtained at the expense of total silicon area and fill factor, which are otherwise optimized provided that the sensor performs a specific task. We propose a new architecture based on macropixel-level processing to improve the trade-off by using the same processing elements (PEs) for a whole group of pixels. In this paper, we show through transistor-level simulations the feasibility of using macropixel PEs. Their operative part is analog to avoid the bottleneck of analog to digital converters and has digital control which is distributed in and out of the matrix of pixels. PEs are designed to be suitable for coefficient-reconfigurable spatial and temporal filtering. Sharing electronics among several pixels and matching existing algorithms to the target architecture allow for such programmability without degrading too much pixel area nor fill factor.     

A routing architecture for mobile integrated services networks

A drawback of the conventional Internet routing architecture is that its route computation and packet forwarding mechanisms are poorly integrated with congestion control mechanisms. Any datagram offered to the network is accepted; routers forward packets on a best-effort basis and react to congestion only after the network resources have already been wasted. A number of proposals improve on this to support multimedia applications; a promising example is the Integrated Services Packet Network (ISPN) architecture. However, these proposals are oriented to networks with fairly static topologies and rely on the same conventional Internet routing protocols to operate. This paper presents a routing architecture for mobile integrated services networks in which network nodes (routers) can move constantly while providing end-to-end performance guarantees. In the proposed connectionless routing architecture, packets are individually routed towards their destinations on a hop by hop basis. A packet intended for a given destination is allowed to enter the network if and only if there is at least one path of routers with enough resources to ensure its delivery within a finite time. Once a packet is accepted into the network, it is delivered to its destination, unless resource failures prevent it. Each router reserves resources for each active destination, rather than for each source–destination session, and forwards a received packet along one of multiple loop-free paths towards the destination. The resources and available paths for each destination are updated to adapt to congestion and topology changes. This mechanism could be extended to aggregate dissimilar flows as well. This revised version was published online in June 2006 with corrections to the Cover Date.     

A hybrid pipelined path-searching architecture for multiplecommunications applications

Many communications applications require similar processing functionality but are implemented independently. In particular, a number of applications (including trellis coding, encryption, and speech recognition) use techniques based on shortest path search algorithms. In this paper, we propose a high-throughput architecture that can search for the shortest path within a graph. The architecture can decode any data encoded with a finite state machine (FSM) or data encrypted in a dynamic trellis code and also serve as a specialized processor for other searching and matching applications. Balance between flexibility and hardware efficiency is achieved by an integrated design of architecture, in-place scheduling, and concurrent algorithms     

Routing architecture optimizations for high-density embedded programmable IP cores

Programmable logic cores differ from stand-alone field-programmable gate arrays in that they can take on a variety of shapes and sizes. With this in mind, we investigate the detailed routing architecture of rectangular programmable logic cores. We quantify the effects of having different X and Y channel capacities and show that the optimum ratio between the X and Y channel widths for a rectangular core is between 1.2 and 1.5. We also present a new switch block family optimized for rectangular cores. Further, we quantify the effects of logic block pin placement. Compared with a simple extension of an existing switch block, our new architecture leads to a density improvement of up to 11.9%. Finally, we show that, if the channel width, switch block, and pin placement are chosen carefully, then the penalty for using a rectangular core (compared to a square core with the same logic capacity) is small; for a core with an aspect ratio of 2:1, the area penalty is 1.6% and the speed penalty is 3.8%.     

An ATM switch architecture for provision of integrated broadbandservices

The author gives some qualitative performance targets to be fulfilled for the service classes proposed by CCITT for the future broadband-ISDN (B-ISDN) and proposes a nonblocking, self-routing asynchronous transfer mode (ATM) switching architecture that is able to fulfil the different performance figures of each class. To exploit the service integration accomplished by ATM switches, the switching bandwidth is allocated at call level and cell level. This allocation gives the flexibility of letting lower-priority services use the reserved bandwidth left temporarily unused by higher-priority services. The architecture adopts mixed input-output queuing. Input queuing is particularly suited to the definition of internal frame structures, making it possible to guarantee the absence of cell loss due to congestion for specific services (such as circuit emulation). Output queuing makes it possible to implement in hardware a switching speedup that practically removes the performance degradation due to the head-of-line blocking phenomenon typical of input queuing     

A multilayer differentiated protection services architecture

Metropolitan area and long-haul networks are migrating toward the deployment of optical mesh technologies. This requires, among other things, a new generation of highly intelligent protection and restoration mechanisms to perform functions of protection and bandwidth management. We introduce an architecture that provides differentiated protection services across multiple layers of network hierarchy. A connection at any client layer can request a protection against resource failures at any lower layer. A key aspect of the architecture is the hierarchical tree organization of shared risk link group (SRLG) resources. They represent routing-related failures across all layers of protocol stack. The architecture is very scalable in terms of communicating link-state and bandwidth information between adjacent layers. SRLG trees are used to aggregate this information and provide a summary to the client layer. We discuss the requirements and challenges for routing and signaling mechanisms in order to support the proposed architecture. The complexity of this architecture is evaluated and compared with the complexity of a nonhierarchical alternative.     

A scalable and programmable simplicial CNN digital pixel processor architecture

We propose a programmable architecture for a single instruction multiple data image processor that has its foundation on the mathematical framework of a simplicial cellular neural networks. We develop instruction primitives for basic image processing operations and show examples of processing binary and gray scale images. Fabricated in deep submicron CMOS technologies, the complexity of the digital circuits and wiring in each cell is commensurate with pixel level processing.     

A hybrid computational grid architecture for comparative genomics.

Comparative genomics provides a powerful tool for studying evolutionary changes among organisms, helping to identify genes that are conserved among species, as well as genes that give each organism its unique characteristics. However, the huge datasets involved makes this approach impractical on traditional computer architectures leading to prohibitively long runtimes. In this paper, we present a new computational grid architecture based on a hybrid computing model to significantly accelerate comparative genomics applications. The hybrid computing model consists of two types of parallelism: coarse grained and fine grained. The coarse-grained parallelism uses a volunteer computing infrastructure for job distribution, while the fine-grained parallelism uses commodity computer graphics hardware for fast sequence alignment. We present the deployment and evaluation of this approach on our grid test bed for the all-against-all comparison of microbial genomes. The results of this comparison are then used by phenotype--genotype explorer (PheGee). PheGee is a new tool that nominates candidate genes responsible for a given phenotype.     

High-speed architecture for a programmable frequency divider and adual-modulus prescaler

We present a prescaler architecture that is suitable for high-speed CMOS applications. We apply the architecture to a 4/5 and an 8/9 dual-modulus prescaler and obtain a measured maximum clock frequency of 1.90 GHz in a standard 0.8 μm CMOS bulk process. This is 13% faster than the traditional prescaler architecture keeping the same power consumption. We also apply the key part of the prescaler to a divide-by-N circuit reaching 1.75 GHz. This is three times faster than any previously reported CMOS implementation and comparable to GaAs implementations     

IMS架构及业务提供

多媒体子系统（IMS）是最初由3GPP制定的,用来提供实时和非实时的IP多媒体业务的通用体系结构,具有分布式、与接入无关、以及标准开放的业务控制接口等特点,被当前业界公认为未来融合的控制平台。文章介绍了IMS的产生背景、业务提供架构,并对基本呼叫流程及presence业务的体系结构进行了分析。     

A unified wireless LAN architecture for real-time and non-real-timecommunication services

This paper addresses how to support both real-time and non-real-time communication services in a wireless LAN with dynamic time-division duplexed (D-TDD) transmission. With D-TDD, a frequency channel is time-shared for both downlink and uplink transmissions under the dynamic access control of the base station. The base station (1) handles uplink transmissions by polling mobiles in a certain order determined on a per-connection (per-message) basis for transmitting real-time (non-real-time) traffic from mobiles and (2) schedules the transmission of downlink packets. To handle location-dependent, time-varying, and bursty errors, we adopt the channel-state prediction, transmission deferment, and retransmission. We consider the problems of scheduling and multiplexing downlink packet transmissions, and polling mobiles for uplink transmissions depending on the channel state. We also establish conditions necessary to admit each new real-time connection by checking if the connection's delivery-delay bound can be guaranteed as long as the channel stays in good condition without compromising any of the existing guarantees. Last, the performance of the proposed protocol is evaluated to demonstrate how the protocol works and to study the effects of various parameters of the protocol     

Design of programmable NoC router architecture on FPGA for multi-cluster NoCs

The next generations of massive, parallel and reconfigurable multi-cluster chips need performance and flexibility, requiring new communication schemes. According to this scenario, a programmable router architecture for networks-on-chips is presented. Results indicate that the proposed router has low area occupation, low power consumption and a high data throughput.