Quasi-saturation capacitance behavior of a DMOS device

This paper reports a simulation study on the capacitance characteristics of a double-diffused metal-oxide semiconductor (DMOS) device operating in the quasi-saturation region. From the analysis, the capacitance effect of the gate oxide upon the drift region cannot be modeled as an overlap capacitance, because the drain-gate/source-gate capacitances of the DMOS device may exceed the gate-oxide capacitance due to the larger voltage drop over the gate oxide than the change in the imposed gate bias when entering the quasi-saturation region. This effect can be the explanation for the plateau behavior in the gate charge plot during turn-on and turn-off of the DMOS device. Based on the small-signal equivalent capacitance model, the accumulated charge in the drift region below the gate oxide may thoroughly associate with the drain terminal in the prequasi-saturation region and with the source terminal in the quasi-saturation region     

A methodology for measuring the gate-drain capacitance of CMOSdevices

In this paper, the author presents a new methodology for measuring the gate drain capacitance of CMOS devices using an accelerated dc measurement scheme. The gate-drain capacitance was measured using a floating gate MOS transistor, i.e., an MOS transistor with an additional capacitor placed in series with the gate oxide capacitance. This was implemented within a standard p-well CMOS process using two matched transistors. The top capacitance couples charge onto the gate oxide capacitor and the gate-drain capacitor. The amount of coupling is determined by the ratio of these two capacitors     

Vertical silicon-on-nothing FET: Threshold voltage calculation using compact capacitance model

The threshold voltage (V_th) model of the novel vertical fully-depleted silicon-on-nothing FET (VFD SONFET) structure is extracted from the compact capacitance equivalent circuit. Due to the absence of the transistor substrate in the VFD SONFET, the channel region is coupled to the source and drain through the buried oxide. Electrostatically, the VFD SONFET resembles the SOI device with thick buried oxide and recessed source/drain, and the developed model can also be applied to these structures. This property is modeled by two-dimensional buried oxide capacitance (C_BOX), which competes for the inversion charge with gate oxide capacitance (C_GOX). Therefore, the V_th is primarily influenced by the ratio of buried and gate oxide capacitances, with the negligible effect of the silicon body equivalent capacitance and the silicon body charge. The relative impact of C_BOX increases with the down-scaling of the effective channel length. In the VFD SONFET structure, the inversion channel can be formed at the back interface of the channel region, due to its coupling to the n⁺ source and drain regions. However, it is shown by the model that the V_th value is minimally changed in this case, due to a small potential change in the silicon channel. The model accurately predicts V_th in comparison to physical simulations, especially in the long channel region, whereas accuracy drops for shorter channels. The maximum absolute deviation is below 50 mV for the channel lengths above 30 nm.     

Charging effect of Si nanocrystals in gate oxide near gate on MOS capacitance

MOS structure with Si nanocrystals embedded in the gate oxide close to the gate has a much larger capacitance compared to a similar MOS structure without the nanocrystals. However, charge trapping in the nanocrystals reduces the capacitance dramatically, and after most of the nanocrystals are charged up the capacitance is much smaller than that of the MOS structure without nanocrystals. An equivalent-capacitance model is proposed to explain the phenomena observed.     

Parasitic capacitance of submicrometer MOSFET's

We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer devices. Furthermore, we proposed a simple model that ensures the same accuracy as that of the Kamchouchi model     

Characteristics and reliability of the SEPROM cell

A new EPROM named SEPROM, based on a modified SEPOX process, is proposed and evaluated. The SEPROM offers a process compatibility to logic LSI's with higher packing density, since the area of the second gate oxide is equal to that of the first gate oxide. To improve the coupling capacitance ratio, which relates to write and read operations, a thin second gate oxide is required for the SEPROM cell at a risk of degradation in charge retention characteristics. A measured test device, however, shows sufficiently good characteristics both in programming and charge retention, due to the desirable structure of the cell. The SEPROM structure appears to be practical and promising for both EPROM and logic device applications.     

绝缘体上硅FinFET亚阈值摆幅研究

在新型多栅器件栅电容模型的研究中,量子电容随着沟道长度及栅氧化层厚度的不断减小而变得越发不可忽略。推导了基于绝缘体上硅(SOI)工艺技术的鳍式场效应晶体管(FinFET)的量子电容,并通过构建囊括量子电容的内部电容网络模型推导了亚阈值摆幅。采用Matlab软件,仿真验证了量子电容对亚阈值摆幅的影响。提出了亚阈值摆幅的优化方法,为如何选取合适的器件尺寸来优化某个特定设计目标的性能提供了指导。     

Modeling of cylindrical surrounding gate MOSFETs including the fringing field effects

A physically based analytical model for surface potential and threshold voltage including the fringing gate capacitances in cylindrical surround gate(CSG) MOSFETs has been developed.Based on this a subthreshold drain current model has also been derived.This model first computes the charge induced in the drain/source region due to the fringing capacitances and considers an effective charge distribution in the cylindrically extended source/drain region for the development of a simple and compact model.The fringing gate capacitances taken into account are outer fringe capacitance,inner fringe capacitance,overlap capacitance,and sidewall capacitance.The model has been verified with the data extracted from 3D TCAD simulations of CSG MOSFETs and was found to be working satisfactorily.     

Separation of interface and nonuniform oxide traps by the DCcurrent-voltage method

Areally nonuniform distribution of oxide charge gives a significant distortion in the gate capacitance and subthreshold DC drain current versus DC gate voltage characteristics. This distortion prevents a reliable determination of the spatial profile of interface and oxide traps generated when a MOS transistor is subjected to channel hot carrier stress. A new procedure is demonstrated which separates the nonuniform oxide charge distribution from interface traps by combining the analysis of two experimental DC characteristics: the subthreshold drain-current and the DC base recombination current versus the gate voltage     

Gate capacitance attenuation in MOS devices with thin gatedielectrics

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the silicon and polysilicon electrodes. For the first time, we quantitatively explore the combined impact of degenerate carrier statistics, quantum effects, and the semiconducting nature of the gate electrode on gate capacitance. Only by including all of these effects can we successfully model the capacitance-voltage behavior of sub-10 nm MOS capacitors. For typical devices, we find the gate capacitance to be 10% less than the oxide capacitance, but it can be attenuated by 25% or more for 4 nm oxides with polysilicon gates doped to less than 10²⁰ cm^-3     

High frequency space charge layer capacitance of strongly inverted semiconductor surfaces

The finite spatial extension of the inversion layer minority carriers shunts the dielectric capacitance of the inversion layer and increases the high frequency semiconductor surface space charge layer capacitance in the strong inversion range by about 5 per cent. This distributed minority carrier distribution also gives rise to a small (about 1 per cent) high frequency capacitance minimum near the onset of strong surface inversion. A simple two-lump model is developed which is accurate to within 0·4 per cent of the numerical solution obtained from the exact transmission line model. Applied gate voltages at the capacitance minimum are presented graphically as a function of oxide thickness with the substrate impurity concentration as a parameter. Surface quantization effect is not taken into account.     

Influence of Si nanocrystal distributed in the gate oxide on the MOS capacitance

In this paper, the authors have studied the influence of silicon nanocrystal (nc-Si) distributed in the gate oxide on the capacitance for the circumstances that the nc-Si does not form conductive percolation tunneling paths connecting the gate to the substrate. The nc-Si is synthesized by Si-ion implantation. The effective dielectric constant of the gate oxide in the nc-Si distributed region is calculated based on a sublayer model of the nc-Si distribution and the Maxwell-Garnett effective medium approximation. After the depth distribution of the effective dielectric constant is obtained, the MOS capacitance is determined. Two different nc-Si distributions, i.e., partial and full nc-Si distributions in the gate oxide, have been considered. The MOS capacitance obtained from the modeling has been compared to the capacitance measurement for a number of samples with various gate-oxide thicknesses, implantation energies and dosages, and an excellent agreement has been achieved for all the samples. A detailed picture of the influence of implantation energy and implantation dosage on the MOS capacitance has been obtained.     

一种p-GaN HEMTs栅电荷表征方法

与Si基金属-氧化物-半导体场效应晶体管(MOSFETs)的绝缘栅结构不同,p-GaN增强型高电子迁移率晶体管(HEMTs)的栅极结构为pn结,其在较大正向电压下处于导通状态,漏电导较大。传统栅电荷测试方法假设栅极注入电流全部存储为栅电荷,因此不适用于p-GaN HEMTs器件,否则会严重高估数值。鉴于此,基于栅电荷积累的基本过程,提出了利用动态电容法来减小漏电流影响来提取p-GaN E-HEMT的栅电荷参数。结果表明,该方法能够得到更理想的栅电荷米勒平台和特性曲线,结果更符合实际,具有重要的应用价值。     

D.C. measurement of the space charge capacitance and impurity profile beneath the gate of an MOST

An analysis of the MOS Transistor with bias between the source and substrate has shown that when the surface is weakly inverted, the silicon space charge capacitance over a wide range of temperature and bias can be obtained from the change in gate voltage required to maintain a constant channel current. The substrate impurity profile beneath the gate oxide can then be calculated from capacitance-bias measurements.     

A new model of gate capacitance as a simple tool to extract MOSparameters

This paper tackles the difficult task to extract MOS parameters by a new model of the gate capacitance that takes into account both poly-Si depletion and charge quantization and includes temperature effects. A new fast and iterative procedure, based on this simplified self-consistent model, will be presented to estimate simultaneously the main MOS system parameters (oxide thickness, substrate, and poly-Si doping) and oxide field, surface potentials at the Si/SiO₂ and at the poly-Si/SiO₂ interfaces. Its effectiveness will be demonstrated by comparing oxide field and oxide thickness to those extracted by other methods proposed in the literature. Moreover, these methods are critically reviewed and we suggest improvements to reduce their errors. The agreement between CV simulation and experimental data is good without the need of any free parameter to improve the fitting quality for several gate and substrate materials combinations. Finally, a simple law to estimate substrate and poly-Si doping in n⁺/n ⁺ MOS capacitors from CV curves is proposed     

一种CMOS工艺离子敏场效应型晶体管的模型

采用CMOS工艺可以实现离子敏场效应型晶体管(ISFET),若在栅极氧化层之上保留多晶硅层,并通过引线使其与 外界的金属层相连作为悬浮的栅极,可实现悬浮栅结构ISFET.从ISFET的传感机理出发,根据表面基模型,利用HSPICE建 立了悬浮栅结构ISFET的物理模型.以该模型为研究对象,探讨了薄膜等效电阻、薄膜等效电...     

A new approach to simulating n-MOSFET gate current degradation byincluding hot-electron induced oxide damage

A new gate current model which considers the hot-electron induced oxide damage in n-MOSFET's was developed for the first time. The spatial distributions of oxide damage, including the interface state (N_it ) and oxide trapped charge (Q_ox) were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated N_it and Q_ox has thus been proposed. Furthermore, the individual contributions of N_it and Q_ox to the degradation of gate current can thus be calculated separately using these oxide damage. For devices stressed under maximum gate current biases, it was found that the interface state will degrade the gate current more seriously than that of the oxide trapped charge. In other words, the interface states will dominate the gate current degradation under I_G,max. Good agreement of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monitor that is superior to substrate current for submicron device reliability applications, in particular for EPROM and flash EEPROM devices     

A capacitance model for GaAs MESFETs

A capacitance model for a GaAs MESFET suitable for implementation in the circuit analysis program SPICE is presented. The model consists of nonlinear capacitances that are a function of two voltages. Such a model gives rise to ordinary nonlinear capacitances and transcapacitances. The placement of these elements in the Y matrix is shown. The empirical equations for the gate charge of a GaAs MESFET given provide an accurate SPICE model for the gate charge and capacitances of a MESFET. A comparison of measured capacitance values with the modeled values gives close enough agreement for circuit simulation purposes     

A 3.3 kV 4H-SiC split gate MOSFET with a central implant region for superior trade-off between static and switching performance

A split gate MOSFET(SG-MOSFET)is widely known for reducing the reverse transfer capacitance(CRSS).In a 3.3 kV class,the SG-MOSFET does not provide reliable operation due to the high gate oxide electric field.In addition to the poor stat-ic performance,the SG-MOSFET has issues such as the punch through and drain-induced barrier lowering(DIBL)caused by the high gate oxide electric field.As such,a 3.3 kV 4H-SiC split gate MOSFET with a grounded central implant region(SG-CIMOS-FET)is proposed to resolve these issues and for achieving a superior trade-off between the static and switching performance.The SG-CIMOSFET has a significantly low on-resistance(RON)and maximum gate oxide field(EOX)due to the central implant re-gion.A grounded central implant region significantly reduces the CRSS and gate drain charge(QGD)by partially screening the gate-to-drain capacitive coupling.Compared to a planar MOSFET,the SG MOSFET,central implant MOSFET(CIMOSFET),the SG-CIMOSFET improve the RON×QGD by 83.7％,72.4％and 44.5％,respectively.The results show that the device features not only the smallest switching energy loss but also the fastest switching time.