基于AD9912镜像频率的应用

常规DDS频率合成方案无法合成超过1/2采样频率的信号频率,这给DDS器件的应用带来了很大限制。在实际应用中通过对DDS器件的输出信号频谱进行分析发现,其频谱中除包含设计频率以外还包含特高频(UHF)频段的镜像频率分量。计算发现这种镜像频率与合成的设计频率成线性关系,故可通过计算确定镜像频率并通过选频滤波提取它们从而获得UHF信号。为扩展DDS器件的应用范围,提出了利用镜像频率实现UHF频率合成方案,设计了基于AD9912芯片的频率合成系统,编写了相应的控制程序。最终实现了利用DDS器件合成了1 500 MHz信号的预想。     

基于DDS三分量感应测井信号源系统设计

介绍了直接数字频率合成（DDS）的原理,依据其基本原理设计一款基于PIC单片机控制的DDS信号源,单片机通过SPI总线方式接收来自上位机发来的频率信号,将其存入EEPROM中,并转换为40位频率控制字写入DDS芯片中使其输出所需频率信号。DDS输出的频率信号含有大量杂散信号,经过7阶椭圆滤波器滤除杂散信号得到纯净的频率信号,再经功率放大后输出至后一级大功率放大电路。实验表明该信号源输出频率范围在1Hz～1MHz,准确度可达0.01Hz,满足三分量感应测井的要求。     

用于DDS系统相位累加器的加法器设计

直接数字频率合成器(DDS)具有频率转换时间短、分辨率高、输出相位连续等优点,是现代频率合成的重要技术之一。在分析了DDS基本原理的基础上,对DDS中的核心单元之一相位累加器进行了系统研究。分别利用镜像电路和超前进位全加器实现信号源累加器模块,进行模拟仿真并比较,结果表明镜像加法器在运算速度、版图布局上都优于超前进位加法器。     

基于AD9851的正弦信号发生器设计

基于直接数字频率合成(DDS)原理,采用AD9851型DDS器件设计一个正弦信号发生器.实现50 Hz～15 MHz范围内的正弦波输出,同时通过对器件的控制编程与相关的简单外部电路切换产生各种调制信号.通过自动增益控制(AGC)和功率放大,在50 Ω负载的情况下,该正弦信号发生器在100 Hz～10 MHz范围内输出稳定正弦波,电压峰峰值为0～5 V±0.3 V.     

基于AD9850的信号发生器的设计

直接数字合成(DDS)是一种重要的频率合成技术,具有分辨率高、频率变换快等优点,在雷达及通信等领域有着广泛的应用前景.系统采用AD9850(DDS)与AT89S52单片机相结合的方法,以AD9850为频率合成器,以单片机为进程控制和任务调度的核心,设计了一个信号发生器.实现了输出频率在10Hz～1MHz范围可调,输出信号频率稳定度优于10-3的正弦波、方波和三角波信号.正弦波信号的电压峰峰值Vopp能在0～5V范围内步进调节,步进间隔达到0.1V,所有输出信号无明显失真,且带负载能力强.     

宽带PCSF雷达信号频率合成器的设计与实现

基于脉内相位编码脉间频率步进（PCSF）雷达信号的特点,提出了利用复杂可编程逻辑器件、直接数字频率合成器（DDS）和锁相环倍频器产生任意PCSF雷达信号的方法,并实际构造了一个宽带、低噪声的S波段PCSF信号源。利用该方法可以实现对输出信号相位的精确控制,通过选择DDS输出信号的频率范围可以减少带内的杂散分量。测试结果表明：该频率源在320 MHz带宽内的无杂散动态范围为62 dBc,相位噪声为-110 dBc/Hz@1 kHz。     

一种基于FPGA的调制指数可调的数字化调频方案

该方案实际上是一个输出频率受控的直接数字频率合成(DDS)系统。通过A/D转换器件将调制信号转换成数字信号,用该数字信号控制DDS的频率控制字,形成输出频率受模拟信号控制的正弦波,从而实现了调频。通过在A/D转换值后补零的方法,可控制调频波的调制指数。系统由FPGA实现。EDA软件Max PlusⅡ的仿真和系统的实际输出波形都表明该数字化调频系统的调制指数可在很大范围内变化。     

DDS的相位截断及相应的杂散信号分析

直接数字频率合成（DDS）的缺点在于输出频率低和存在大量的杂散信号。而杂散信号产生的原因之一就是相位截断。文章首先介绍了DDS的基本结构和原理，总结了产生DDS杂散噪声的来源。重点分析了相位截断误差以及由相位截断引起的杂散频率分量，提出了计算这一杂散频率分量个数及信噪比的方法。     

非理想DDS输出信号分析及滤波处理

直接数字频率合成(DDS)技术广泛应用于可变时钟发生电路中,文中介绍了直接数字频率合成(DDS)技术的基本原理和非理想情况下DDS输出频谱结构,然后分析了工程实际中杂散对时钟信号的影响,最后解释了以滤波器和锁相环(PLL)改善输出时钟信号质量的原理,并给出了实验结果。     

基于DSP Builder的Chirp信号源设计

设计分析了Chirp函数在时域和频域内的一般特点和解析公式.提出首先在Altera DSP开发工具DSP Builder中实现直接数字合成器(DDS)模块,根据Chirp函数特定的输入/输出(线性和非线性)关系,计算出当前输入字与输出频率的对应关系;然后设计控制字子模块产生DDS模块的频率控制字,驱动DDS产生不同的输出频率,通过在Matlab的Simulink环境下的仿真验证,得出不同时刻输出的频谱图,验证了该设计能很好地实现Chirp信号源.     

A direct digital synthesizer with a tunable error feedbackstructure

A basic premise for a direct digital synthesizer (DDS) with error feedback (EF) is that the output frequency being generated is low with respect to the clock frequency used. This is necessary because the transfer function of the EF has zero(s) at DC. In the proposed architecture the clock frequency need only be much greater than the bandwidth of the output signal, whereas the output frequency could be any frequency up to somewhat below the Nyquist frequency. In this novel method, the coefficients of the EF filter are tuned according to the output frequency     

Ka 波段应用的捷变频高频率分辨率频率合成器

传统基于锁相环(PLL)实现带宽信号输出的频率合成方案,常常为了获得高输出频率而降低频率分辨率和缩短跳频时间。相较而言,基于直接数字频率合成器(DDS)实现带宽信号输出的频率合成方案,其频率分辨率更高,跳频时间更快。然而,DDS 输出频率低,须经多次混频或倍频操作以提升输出频率,对频率源中的滤波器设计造成极大压力,并且这种压力随着频率源输出频率的升高而不断上升。对此,基于高性能、小型化无源滤波器的设计能力,实现了基于DDS 变频的34-35GHz 捷变频、高频率分辨率频率源。实验结果表明,其工作相位噪声优于-85dBc/Hz@1kHz,杂散和谐波抑制优于45 dBc,频率分辨率达到1.86Hz,跳频时间最快4ns。     

Very-high-rank avalanche diode frequency multiplier

Recent experimental observations on silicon avalanche diode multipliers operated at about 35-GHz output frequency are presented. High-rank (up to 35) frequency multiplication is achieved with output power over 250 mW and conversion loss of 13 dB. The possibility of frequency multiplication by any integer n ranging from 8 to 35 with the same diode and without any idler circuit is pointed out. It is concluded that any output frequency can be selected between 28 and 39 GHz by varying the input frequency and the circuit tuning.     

Fully integrated SiGe VCOs with powerful output buffer for 77-GHz automotive Radar systems and applications around 100 GHz

It is demonstrated that SiGe bipolar technologies are well suited for voltage-controlled oscillators (VCOs) in 77-GHz automotive radar systems. For this, the design of a VCO with powerful output buffer (with good decoupling capability and high output power), comparatively wide tuning range, and reasonably low phase noise is described. To achieve the required high output power, the potential operating range of the output transistors, limited by high-current effects and avalanche breakdown, respectively, had to be exploited using adequate transistor models. The VCOs need a single supply voltage only and have been fully integrated (including resonant circuit and output buffer) on a single small (1 mm/sup 2/) chip, demonstrating their low-cost potential. Experimental results showed, at a center frequency of around 77 GHz, a usable tuning range of 6.7 GHz and a phase noise of -97 dBc/Hz at 1-MHz offset frequency averaged over this range. In addition, the center oscillation frequency can be coarsely adjusted within a wide range by cutting links in the upper metallization layer. The total signal power delivered by both buffer outputs together is as high as 18.5 dBm at a power consumption of 1.2 W. Simulations let us expect a potential doubling of the output power (for two or four outputs) by extension of the output buffer. To get an impression of the maximum frequency achievable with the circuit concept and technology used, a second VCO (again with buffered output) has been developed. To the best of the authors' knowledge, the measured maximum oscillation frequency of about 100 GHz, at 12.4-dBm total output power (14.3 dBm at 99 GHz), is a record value for SiGe VCOs with buffered output operating at their fundamental frequency. The usable tuning range is still 6.2 GHz.     

C波段宽带下变频型锁相高速跳频合成器

介绍了一种C波段宽带下变频型锁相高速跳频合成器,主要用于雷达及通信领域。该频率合成器采用锁相环(PLL)与外插电路组合的方式,将较高的输出频率迁移到较低频率后送至鉴相器,大大降低N分频器的工作频率,提高了频率合成器的最高输出频率,且输出频率间隔不变,解决了提高合成器输出频率和不降低频率分辨率的矛盾,实现低相位噪声输出。测试结果表明,输出频率4 460 MHz时,在频偏10 kHz处相位噪声为-123 dBc/Hz。采用可控输出的稳压芯片给HMC704LP4供电,通过控制电源的通断,保证HMC704LP4进入正确的工作模式,有效解决了HMC704LP4上电模式选择错误造成的失锁问题。     

4GHz级频率综合器下单片低相位噪声CMOS电感电容压控振荡器的设计

基于0.18μm RF CMOS工艺,采用双端调谐结构实现了一种可应用于WLAN的二次变频收发机的压控振荡器.其输出频率范围可以覆盖收发机所需4.1～4.3GHz的频段,其最大调谐范围为500MHz.在距中心频率4.189GHz为4MHz处的相位噪声为-117dBc/Hz,500kHz处为-107dBc/Hz.输出信号抖动的均方根值为4.423ps,输出功率为-8.68dBm.     

一种自稳频大功率单频He-Ne激光器的功率估算

介绍了一种大功率单频、自稳频、高输出功率He-Ne激光器功率估算方法的改进。用这种方法的估算值与实际输出功率值符合得较好。     

低相噪超多频段VCO宽带锁相环的研究

为了解决宽带锁相环设计中相位噪声和输出频率范围的矛盾,分析并设计了一种基于超多频段压控振荡器(VCO)锁相环的方案。该方案通过降低VCO的频率灵敏度和每个VCO 配置LC矩阵等效多个VCO的方法,使VCO在保证输出的频率范围的同时,优化了相位噪声。实验结果发现,该方案可以使锁相环在保证较大的输出频率范围前提下拥有更低的相位噪声。     

Implementation of a high speed frequency synthesizer employing a dual input phase accumulator

We present a new PLL based frequency synthesizer, in which we have replaced the conventional phase frequency detector and the dividers (programmable counters) with a sequential dual input phase accumulator (DIPA), consisting of a digital circuit employing adders, registers and a ladder. The main feature of the DIPA is that the two input frequencies are not required to be normalized (divided down) to the step frequency of the synthesizer. Instead, the two different high frequencies, that is the reference and the output frequency of the synthesizer, are applied directly. The DIPA samples and normalizes their phases at very high rates, calculates their phase difference, producing an output that consists of a dc component proportional to the phase difference and harmonics of the two input high frequencies. These harmonics are high frequencies and can easily be rejected by a wide bandwidth filter of the loop, without affecting the high convergence speed of the loop. Moreover, these harmonics do not generate spurs near the output frequency. The resolution of the DIPA based synthesizer depends only on the length of the digital word of the DIPA, and its convergence speed depends on the lower of the two input frequencies. The output of the DIPA is a linear function of the phase difference of the two input frequencies and its dynamic range exceeds the limit of ±2π that governs the conventional phase detectors. Thus, the proposed frequency synthesizer based on the DIPA has low phase noise, no spurs nearby the output frequency, high resolution and fast convergence rate. Additionally, the output frequency can be digitally modulated under the control of the closed loop, either by phase or frequency modulation.     

基于加权模值的FDA最优频率间隔选取方法

传统频率分集阵列(FDA)在阵元间引入的是固定的频率间隔,并不能使FDA在不同环境下都具有最优的抗干扰性能。文中提出了一种基于加权模值的自适应选取FDA最优频率间隔方法,通过对FDA最优波束形成器的输出信干噪比(SINR)的分析,推导出输出SINR与频率间隔潜在的关系,自适应选取阵列加权最小模值对应的频率间隔,形成单峰值波束方向图,并反馈给发射机,使得输出SINR最大化。理论和仿真结果均证明了FDA通过该方法选取到最优频率间隔后,具有更好的抗主、副瓣干扰性能。