CMOS: compatible wafer bonding for MEMS and wafer-level 3D integration

Wafer bonding became during past decade an important technology for MEMS manufacturing and wafer-level 3D integration applications. The increased complexity of the MEMS devices brings new challenges to the processing techniques. In MEMS manufacturing wafer bonding can be used for integration of the electronic components (e.g. CMOS circuitries) with the mechanical (e.g. resonators) or optical components (e.g. waveguides, mirrors) in a single, wafer-level process step. However, wafer bonding with CMOS wafers brings additional challenges due to very strict requirements in terms of process temperature and contamination. These challenges were identified and wafer bonding process solutions will be presented illustrated with examples.     

A survey on CAD methods in 3D garment design

With the advance in virtual reality applications, garment industry has strived for new developments. This paper reviews state-of-the-art CAD methods in 3D garment design. A large range of techniques are selected and organized into several key modules which form the core of a 3D garment design technology platform. In each module, basic techniques are presented first. Then advanced developments are systematically discussed and commented. The selected key modules - digital human modeling, 3D garment design and modification, numerical integration of draping, 2D pattern generation, geometric details modeling, parallel computation and GPU acceleration - are discussed in turn. Major challenges and solutions that have been addressed over the years are discussed. Finally, some of the ensuing challenges in 3D garment CAD technologies are outlined.     

Low-temperature wafer-level transfer bonding

In this paper, we present a new wafer-level transfer bonding technology. The technology can be used to transfer devices or films from one substrate wafer (sacrificial device wafer) to another substrate wafer (target wafer). The transfer bonding technology includes only low-temperature processes; thus, it is compatible with integrated circuits. The process flow consists of low-temperature adhesive bonding followed by sacrificially thinning of the device wafer. The transferred devices/films can be electrically interconnected to the target wafer (e.g., a CMOS wafer) if required. We present three example devices for which we have used the transfer bonding technology. The examples include two polycrystalline silicon structures and a test device for temperature coefficient of resistance measurements of thin-film materials. One of the main advantages of the new transfer bonding technology is that transducers and integrated circuits can be independently processed and optimized on different wafers before integrating the transducers on the integrated circuit wafer. Thus, the transducers can be made of, e.g., monocrystalline silicon or other high-temperature annealed, high-performance materials. Wafer-level transfer bonding can be a competitive alternative to flip-chip bonding, especially for thin-film devices with small feature sizes and when small electrical interconnections (<3×3 μm²) between the devices and the target wafer are required     

See in 3D: state of the art of 3D display technologies

With advances in lasers, optics, and electronics, many new 3D display technologies have been proposed with prototypes in research labs or have entered the marketplace. Although some of these technologies (such as Stereoscopy) are familiar to people, other technologies, such as holography, remain far-fetched to most. This survey introduces the principles of current popular 3D display technologies, which are generally categorized into four categories: 3D movies, on-stage holograms, holographic projections and volumetric 3D displays. Furthermore, the limitations of each of the aforementioned technologies are deeply analyzed, and comparisons of these technologies are provided. Moreover, we note appropriate application situations for the various technologies. Because computer-generated hologram (CGH) technologies are considered to be the next generation of 3D display technology and have become a dominant direction in 3D display technology development, we address the challenges that CGH is currently facing and provide an insightful analysis of solutions proposed in recent years. Finally, we study the current 3D display applications associated with the four categorized technology principles.     

Wafer bonding with nano-imprint resists as sacrificial adhesive for fabrication of silicon-on-integrated-circuit (SOIC) wafers in 3D integration of MEMS and ICs

In this paper, we present the use of thermosetting nano-imprint resists in adhesive wafer bonding. The presented wafer bonding process is suitable for heterogeneous three-dimensional (3D) integration of microelectromechanical systems (MEMS) and integrated circuits (ICs). Detailed adhesive bonding process parameters are presented to achieve void-free, well-defined and uniform wafer bonding interfaces. Experiments have been performed to optimize the thickness control and uniformity of the nano-imprint resist layer in between the bonded wafers. In contrast to established polymer adhesives such as, e.g., BCB, nano-imprint resists as adhesives for wafer-to-wafer bonding are specifically suitable if the adhesive is intended as sacrificial material. This is often the case, e.g., in fabrication of silicon-on-integrated-circuit (SOIC) wafers for 3D integration of MEMS membrane structures on top of IC wafers. Such IC integrated MEMS includes, e.g., micro-mirror arrays, infrared bolometer arrays, resonators, capacitive inertial sensors, pressure sensors and microphones.     

Test Challenges for 3D Integrated Circuits

One of the challenges for 3D technology adoption is the insufficient understanding of 3D testing issues and the lack of DFT solutions. This article describes testing challenges for 3D ICs, including problems that are unique to 3D integration, and summarizes early research results in this area. Researchers are investigating various 3D IC manufacturing processes that are particularly relevant to testing and DFT. In terms of the process and the level of assembly that 3D ICs require, we can broadly classify the techniques as monolithic or as die stacking.     

First-order performance prediction of cache memory with wafer-level 3D integration

The advantages of 3D design can be exploited by reducing the memory access time. In this article, the authors use a simulator based on analytical models to build an optimal processor-memory configuration for two designs: a graphics processor and a microprocessor. One emerging alternative approach to relieving these interconnect constraints is the use of wafer-level 3D integration, which provides a high density of high-performance, low-parasitic vertical interconnects. A wafer-level 3D design is partitionable into multiple chips connected by short vertical vias. This arrangement reduces the length of many global interconnects without introducing any logic complexity. Wafer-level 3D integration also reduces the required number of repeaters, thereby improving the area efficiency and reducing the power consumed within the interconnect network. With micron-size interwafer vias, wafer-level 3D integration allows a large memory bandwidth with little wafer area consumption. We have developed a software program that allows a first-order comparison of cache designs in 2D and 3D IC technologies. We present a first-order estimate of the performance improvements achieved by 3D implementation of cache memory, with emphasis on large caches in deep-submicron technologies.     

基于吹塑成型方法的微玻璃空腔的设计与制备

根据硼硅酸盐玻璃的内部结构特殊性和热学性质,设计并制备出两种3D微玻璃空腔,主要讲述了3D微玻璃空腔的设计过程和吹塑成型的制备方法。 CORNING Pyrex 7740玻璃是硼硅酸盐玻璃的代表。将硅片进行深硅刻蚀形成深槽,并与7740玻璃进行常压下的阳极键合,形成微空腔;将得到的微空腔放入真空退火炉中进行退火,使玻璃空腔内部空气膨胀,最终形成3D微玻璃空腔。经过实验得到的两种3D微玻璃空腔表明其制备工艺的可行性,将制备出的3D微玻璃空腔运用到导航器件的设计和微结构的封装等方面,具有比较好的发展前景。     

Static and dynamic 3D facial expression recognition: A comprehensive survey

Automatic facial expression recognition constitutes an active research field due to the latest advances in computing technology that make the user's experience a clear priority. The majority of work conducted in this area involves 2D imagery, despite the problems this presents due to inherent pose and illumination variations. In order to deal with these problems, 3D and 4D (dynamic 3D) recordings are increasingly used in expression analysis research. In this paper we survey the recent advances in 3D and 4D facial expression recognition. We discuss developments in 3D facial data acquisition and tracking, and present currently available 3D/4D face databases suitable for 3D/4D facial expressions analysis as well as the existing facial expression recognition systems that exploit either 3D or 4D data in detail. Finally, challenges that have to be addressed if 3D facial expression recognition systems are to become a part of future applications are extensively discussed.     

Wafer-level bonding and direct electrical interconnection of stacked 3D MEMS by a hybrid low temperature process

The presented fabrication technology enables the direct integration of electrical interconnects during low temperature wafer bonding of stacked 3D MEMS and wafer-level packaging. The low temperature fabrication process is based on hydrophilic direct bonding of plasma activated Si/SiO₂ surfaces and the simultaneous interconnection of two metallization layers by eutectic bonding of ultra-thin AuSn connects. This hybrid wafer-level bonding and interconnection technology allows for the integration of metal interconnects and multiple materials in stacked MEMS devices. The process flow is successfully validated by fabricating test structures made out of a two wafer stack and featuring multiple ohmic electrical interconnects.     

Wafer bonding using Cu–Sn intermetallic bonding layers

Wafer-level Cu–Sn intermetallic bonding is an interesting process for advanced applications in the area of MEMS and 3D interconnects. The existence of two intermetallic phases for Cu–Sn system makes the wafer bonding process challenging. The impact of process parameters on final bonding layer quality have been investigated for transient liquid phase wafer-level bonding based on the Cu–Sn system. Subjects of this investigation were bonding temperature profile, bonding time and contact pressure as well as the choice of metal deposition method and the ratio of deposited metal layer thicknesses. Typical failure modes in intermetallic compound growth for the mentioned process and design parameters have been identified and were subjected to qualitative and quantitative analysis. The possibilities to avoid abovementioned failures are indicated based on experimental results.     

Thermal management in 3d networks-on-chip using dynamic link sharing

3D integration is a practical solution for overcoming the problems of long and slow global wires in current and future generations of integrated circuits. This emerging technology stacks several die slices on top of each other in a single chip. It provides higher-bandwidth and lower-latency in the third dimension than a 2D design due to extremely shorter inter-layer distances. However, thermal challenges are a key impediment to stacking logic dies on top of each other. Particularly, routers in a 3D network-on-chip (NoC) are a main source of thermal hotspots, limiting the potential performance gains of the 3D integration. In this paper, we take advantage of the low-latency 3D vertical links to design a temperature-aware router architecture for 3D NoCs. This architecture reduces the peak temperature of routers, particularly routers that are farther from the heat sink, by balancing the traffic across all layers in a temperature-aware distributed way. This way, a router with high temperature can borrow the link and crossbar bandwidth of the routers in the layers closer to the heat sink to forward its packets, effectively offloading part of its traffic to them to reduce its temperature.Experimental results show that the proposed method can control the temperature of 3D NoCs and reduce the temperature gradient across the network with minimized negative impact on performance, compared to a state-of-the-art 3D NoC temperature management method.     

三维芯片中TSV链式冗余修复电路的设计与实现

由于具有高集成度、高性能及低功耗等优点,三维芯片结构逐渐成为超大规模集成电路技术中的热门研究方向之一。TSV是三维芯片进行垂直互连的关键技术,然而在TSV的制作或晶圆的减薄和绑定过程中都可能产生TSV故障,这将导致与TSV互联的模块失效,甚至整个三维芯片失效。提出了一种基于TSV链式结构的单冗余/双冗余修复电路,利用芯片测试后产生的信号来控制该修复电路,将通过故障TSV的信号转移到相邻无故障的TSV中进行传输,以达到修复失效TSV的目的。实验结果表明,该电路结构功能正确,在面积开销较低的情况下,三维芯片的整体修复率可达91.97%以上。     

一种面向通信特征的3D NoC体系结构设计

三维集成电路(three dimensional integrated circuit, 3D IC)和片上网络(network on chip, NoC)是集成电路设计发展的两个趋势.将两者结合的三维片上网络(three dimensional networks on chip, 3D NoC)是当前研究的热点之一.针对现有3D NoC的研究没有充分关注硅片内与硅片间的异构通信特征.提出了面向通信特征的硅片间单跳步(single hop inter dies, SHID)体系结构,该结构采用异构拓扑结构和硅片间扩展路由器(express inter dies router, EIDR).通过实验数据的分析表明,与3D-Mesh和NoC-Bus这两种已有的3D NoC结构相比,SHID结构有以下特点：1)延迟较低,4层堆叠时比3D-Mesh低15.1%,比NoC-Bus低11.5%;2)功耗与NoC-Bus相当,比3D-Mesh低10%左右;3)吞吐率随堆叠层数增加下降缓慢,16层堆叠时吞吐率比3D-Mesh高66.98%,比NoC-Bus高314.49%.SHID体系结构同时具备性能和可扩展性的优势,是未来3D NoC体系结构良好设计选择.     

基于Petri网的组合设备建模与调度综述

组合设备是半导体晶圆制造的核心装备, 其调度与控制优化是半导体制造领域极具挑战性的课题. Petri网因其强大的建模能力和简约的图形化表达优势, 被广泛地应用于组合设备的建模与调度. 对基于Petri网的组合设备建模与调度方法进行综述, 归纳总结了组合设备的结构类型、晶圆流模式、调度策略及Petri网建模方法, 并系统阐述组合设备的7类典型调度问题, 包括驻留时间约束、作业时间波动、晶圆重入加工、多品种晶圆加工、加工模块(Process module, PM)故障、PM清洗和组合设备群. 最后, 讨论了当前组合设备调度存在的挑战及后续可能的研究方向.     

基于Jini支持X3D的虚拟场景浏览器的研究与探索

随着计算机技术和网络技术的不断发展,为了使多个用户在一个基于网络的计算机集合中,共享同一个虚拟环境,从而设计在一个分布式虚拟环境中。支持多用户共享的具有独立功能的虚拟环境浏览器成为必然。而当前虚拟场景的浏览器大多是设计为IE或Netscape等浏览器的一个插件,而不是一个独立的客户端。随着基于Java的分布式计算平台Jini和面向下一代的三维图形标准X3D的发展,为研究支持分布式虚拟环境的浏览器提供了理论基础。该文在讨论X3D和Jini技术的基础上。实现了一个基于Jini支持X3D的虚拟场景浏览器的简单原型。     

微创手术式硅微机械加工（MISSM）技术

介绍了一种新颖的微创手术式硅微机械加工(MISSM)技术,该技术充分利用(111)硅片的晶向分布和各向异性湿法腐蚀的特性。通过在单晶硅片表面制作一系列微型释放窗口来定义结构的轮廓及尺寸,实现在单晶硅片内部选择性可自停止腐蚀技术,制作出不同结构尺寸的腔体。同时,结合不同器件结构设计的需求,缝合微型释放窗口并进行后续工艺制作及最终可动结构释放。该技术采用微创手术式单硅片单面体硅工艺替代传统的表面微机械工艺,制作工艺简单,既具有单硅片单面加工的优势又便于与IC工艺兼容。文章详细讲述了微创手术式三维微机械结构的成型机理和工艺流程,并针对其关键技术进行了系统的分析,取得了令人满意的结果。     

CO_2激光器加工晶圆切缝控制工艺研究

晶体硅是当前最重要的半导体材料,主要用于微电子技术。随着微电子技术的发展,对晶圆的切割技术要求越来越高,而在实际切割中,对晶圆的切割十分注重于晶圆的切割宽度,以降低晶圆损耗。研究CO2激光切割机的脉宽、频率以及切割速度对晶圆切割宽度的影响,从而达到高效率、小宽度、高标准的激光切割加工。     

Thermal-aware floorplanner for 3D IC,including TSVs,liquid microchannels and thermal domains optimization

3D stacked technology has emerged as an effective mechanism to overcome physical limits and communication delays found in 2D integration. However, 3D technology also presents several drawbacks that prevent its smooth application. Two of the major concerns are heat reduction and power density distribution. In our work, we propose a novel 3D thermal-aware floorplanner that includes: (1) an effective thermal-aware process with three different evolutionary algorithms that aim to solve the soft computing problem of optimizing the placement of functional units and through silicon vias, as well as the smooth inclusion of active cooling systems and new design strategies, (2) an approximated thermal model inside the optimization loop, (3) an optimizer for active cooling (liquid channels), and (4) a novel technique based on air channel placement designed to isolate thermal domains have been also proposed. The experimental work is conducted for a realistic many-core single-chip architecture based on the Niagara design. Results show promising improvements of the thermal and reliability metrics, and also show optimal scaling capabilities to target future-trend many-core systems.     

基于虚拟现实的三维园林景观设计仿真系统

现有的园林景观专业CAD软件对三维模型及虚拟仿真效果表达有限,只能进行二维施工图绘制.为解决动态景观特性,研发了虚拟现实技术的三维园林景观设计仿真系统,采用面向对象的参数化三维实体建模手段,实现了三维实体建模、设计场景的三维实时虚拟呈现、渲染图及动画制作、施工图绘制等功能,并探索了系统计算原理、实现方法及OpenGL扩展功能等相关技术.然后简要介绍了系统整体功能,详细论述了专业模块中的仿真过程.最后以工程实例验证了系统的有效性.