An analytical two-dimensional simulation for the GaAs MESFETdrain-induced barrier lowering: a short-channel effect

An analytic model for simulating the GaAs MESFET drain-induced barrier lowering and its effect on device performance are discussed. The potential barrier between the source and drain of a field-effect transistor in or near the subthreshold region is lowered by increasing the drain voltage. As the barrier is lowered to be comparable to the thermal energy, an appreciable current will flow through the channel, and the device will begin to conduct. This effect causes the threshold-voltage-control problem and degrades the device performance     

A unified analytical model for drain-induced barrier lowering and drain-induced high electric field in a short-channel MOSFET

Using the well known El-Mansy-Ko method, a simple solution of the two dimensional Poisson equation is derived at the SiSiO₂ interface for the region bounded by the source and the drain. The solution is valid for long channel as well as short channel MOSFETs. The effect of variable values of the depletion depth is incorporated using the WKB approximation. The solution yields a new model of the subthreshold voltage of a short channel MOSFET. The solution also provides mathematical justification of the intuitive assumptions made by Hsu, Muller and Hu in their paper on punch through currents in short channel MOSFETs. Since the single solution gives both the drain induced high field, DIHF, and the drain induced barrier lowering, DIBL, it also yields an analytical relation between them. The DIBL increases approximately expnentially as E_max decreases. The results obtained from this model are in agreement with the numerical simulations and are consistent with the known experimental results.     

Optimum scaling of buried-channel CCD's

The maximum charge packet size in a two-phase charge-coupled device (CCD) is limited by many constraints relating to the transfer efficiency requirement and control circuit limitations. The constraints are quantified and an optimization routine is developed for designing CCD's with maximum charge capacity per unit area under these constraints. The optimum charge capacity for scaled down CCD's is calculated and it is shown that the normal buried channel cannot be designed to have adequate charge capacity at small geometries. A novel low-voltage buried-channel structure is introduced which uses a shallow p-type surface implant to minimize surface trapping and increases the charge capacity per unit area 2.4× compared to the normal buried channel. The optimum charge packet size at ∼1-µm geometry for these CCD structures, based on these calculations, is shown to be inadequate for VLSI dynamic memory applications.     

CCD MPP结构制作工艺技术研究

在1024×1024可见光电荷耦合器件(CCD)的基础上增加了MPP(Multi-PinnedPhase)结构设计和工艺制作.制得的1024×1024可见光MPP CCD实现了MPP功能,有效抑制了CCD表面暗电流的产生.当MPP注入剂量为(6±2)×10~(11)cm~(-2)时,其暗电流密度下降了2/3,满阱电荷下降了1/2.

Abstract：

Multi-Pinned Phase (MPP) structure is designed and fabricated on the base of 1024×1024 visible light CCD. The 1024×1024 visible light MPP CCD achieves MPP function and suppresses the surface dark current effectively. Its dark current density and full well capacity decrease 2/3 and 1/2, respectively, when MPP implant dose is(6±2)×10~(11) cm~(-2).     

Very low dark current heterojunction CCD's

A model has been formulated which accounts for the major sources of dark current (JD) associated with a single pixel of a heterojunction, Schottky gate charge-coupled device (CCD). This model predicts the temperature dependence of JDand shows that for properly fabricated gates, bulk generation in the channel is the primary source of dark current. To verify the model, the dark current of Al0.3Ga0.7As/ GaAs n-p⁺heterostructure CCD's was measured over the temperature range 23-55°C. At room temperature,J_{D} approx 83pA/cm², typically, and some pixels have JDas low as 43 pA/cm². These are the lowest dark currents reported to date for a CCD structure. The data at 55°C show that, typically, JDincreases to ∼ 1 nA/cm². Furthermore, the data confirm the temperature dependence of JDpredicted by the model.     

The short-channel IGFET

Formulas are presented which show that arbitrarily short-channel length for an insulated-gate field-effect transistor does not lead to arbitrarily large transconductance. Instead, the Boltzmann limit is indicated.     

Ultrafast shallow-buried-channel CCD's with built-in drift fields

The delay lines are operated with 5-V two-phase clocks, and a potential gradient is permanently built into the storage gates by a step implant in order to improve the charge transfer efficiency (CTE) at high clocking rates. The charge coupled devices (CCDs) with built-in drift fields were tested up to the 325-MHz limit of the existing clock drivers with no degradation in the CTE(>0.99996), while the equivalent CCDs with uniformly doped storage wells degrade rapidly above 240 MHz. These results are consistent with two-dimensional computer simulations     

消除CCD不良背景的工艺研究

对电荷耦合器件(CCD)交流成像中存在的背景发白、亮条、亮点、拖影和固定图像噪声等不良背景进行了分析,并提出了调整栅介质生长方法、本征吸杂、低温退火等消除不良背景的具体工艺方法,获得了高质量的CCD器件.测试结果表明,其交流成像中的不良背景得到了有效控制.     

A technique to measure trap characteristics in CCD's using X-rays

An important type of radiation damage in CCD's used for X-ray spectroscopy is the degradation of charge transfer efficiency (CTE). Traps associated with radiation-induced defects are the basic cause of the damage. Here, we describe a method to extract trap characteristics using small charge packets produced by individual X-ray photon interactions in rectangular imaging CCD's. The method applies the principles of trap occupancy to the framestore CCD configuration, and uses data from CCD's operating in their normal transfer mode. We have measured trap characteristics in radiation damaged CCD's in a range of operating temperatures from 170-200 K, and have found that these data compare well to the expected phosphorus-vacancy (P-V) trap characteristics     

Threshold voltage in short-channel MOS devices

The threshold voltage in short-channel MOS transistors was investigated by use of a two-dimensional numerical solution of Poisson's equation and experimental measurements on devices of 5.15-, 3.15-, and 2.15-µm channel length. The assumption of constant equipotential surface in the oxide implicit in the charge-sharing technique is not valid in devices of shorter Channel lengths and at larger operating voltages. The numerical determination of the threshold voltage from the two-dimensional analysis agrees with experimental results. Unlike previous work, the charge-sharing model was investigated from an electric-field point of view. The inadequacies of the charge-sharing model are elucidated qualitatively and quantitatively.     

Guidelines for reverse short-channel behavior

Necessary conditions for the occurrence of the reverse short-channel (RSC) effect for threshold voltage V_T for submicrometer MOSFETs due to channel profile nonuniformity are established: (1) sufficiently large concentration decrease towards the Si-SiO₂ interface of the channel doping (not necessarily a peak below the surface); (2) laterally nonhomogeneous enhancement of the diffusivity of the channel dopant either by injection of interstitials or vacancies from outside the gate region; and (3) the minimal distance between the point-defect injection next to the gate and the metallurgical channel-to-drain junction is smaller than the characteristic lateral decay length of the point defects. The above conditions are corroborated by the conditions for the threshold-voltage enhancement at the small channel lengths reported     

Distortion in RF CMOS short-channel low-noise amplifiers

An approach to estimate the distortion in CMOS short-channel (e.g. 0.18-/spl mu/m gate length) RF low-noise amplifiers (LNAs), based on Volterra's series, is presented. Compact and accurate frequency-dependent closed-form expressions describing the effects of the different transistor parameters on harmonic distortion are derived. For the first time, the second-order distortion (HD2), in CMOS short-channel based LNAs, is studied. This is crucial for systems such as homodyne receivers. Equations describing third-order intermodulation distortion in RF LNAs are reported. The analytical analysis is verified through simulations and measured results of an 0.18-/spl mu/m CMOS 5.8-GHz folded-cascode LNA prototype chip geared toward sub-1-V operation. It is shown that the distortion is independent of the gate-source capacitance C/sub gs/ of the MOS transistors, allowing an extra degree of freedom in the design of LNA circuits. Distortion-aware design guidelines for RF CMOS LNAs are provided throughout the paper.     

Electron dynamics in short-channel InP field-effect transistors

The transient response of electrons to a high field in InP has been calculated by a Monte Carlo method. The results are compared with previously published results for GaAs, and used to indicate the performance that may be obtained in InP and GaAs microwave f.e.t.s.     

Hysteresis I-V effects in short-channel Silicon MOSFET's

Hysteresis in Ids-Vdscharacteristics is observed at high drain voltages in short-channel silicon MOSFET's biased into the normally off regime, the degree of which depends on the substrate and gate biases. The MOSFET switches at this hysteresis point from subthreshold to space-charge limited current behavior. It is proposed that this hysteresis effect is due to avalanched holes which accumulate at the gate interface, causing a deformation of the potential distribution in the substrate and the triggering of the device into space-charge limited current behavior.     

A method for improving the spatial resolution of frontside-illuminated CCD's

A method is proposed for improving the spatial resolution of frontside-illuminated silicon CCD imagers. The technique involves building the device on an epitaxial layer deposited on a more highly doped substrate of the same conductivity type, creating a high-low junction. A simple theoretical model for the carrier diffusion limited modulation transfer function (MTF) is developed for this structure. Calculations of the MTF using this model are compared to similar calculations for other configurations, e.g., a thinned, backside-illuminated device and a frontside-illuminated imager built on a uniformly doped substrate. The calculations show that the new structure has MTF performance comparable to or better than the backside-illuminated device and has, for λ = 1.06 µm and Nyquist spatial frequency, an MTF which is nearly an order of magnitude higher than that for the nonepitaxial frontside-illuminated device. At the same time, the quantum efficiency of the epitaxial device is reduced by about one order of magnitude. The effects of substrate doping and epitaxial layer thickness are also explored.     

Linearity of potential equilibration method of injecting charge into CCD's

The linearity of injecting charge into charge-coupled devices (CCD's) by potential equilibration method has been studied. Experimental results obtained agree Well with the theoretically derived expression for the input characteristic. If the two input gates have identical structures, i.e., the same oxide thicknesses and substrate dopings, input linearity is obtained irregardless to which gate the signal is applied. On the other hand, if the two gates are different, the signal should always be applied to the second gate in order to obtain a linear input function.     

Double boron implant short-channel MOSFET

Threshold voltage and current-voltage characteristics are presented for a double boron-ion-implanted-n-channel enhancement MOSFET device for high speed logic circuit applications. A 15-Ω. cm-high resistivity p-type     

Transit-time model for short-channel MOSFET's

A new analytical transit-time model for submicrometer MOS devices has been developed. The model is based on a modified SPICE level-three MOSFET DC model, and it allows the use of a physical value for the charge carrier saturation velocity. This is essential for accurate transit-time modeling. Both DC and transit-time models show good agreement with the results obtained from more complicated two-dimensional numerical simulations