地平面的分割

一个完整的地平面能减少电路板的EMI和串扰问题。在数模混合布板时,数字电路的同步开关噪声往往会影响敏感的模拟电路。分割的地平面能够提供高的噪声隔离度,但同时也会引起另外的一些EMI问题。本文就如何正确的分割地平面以及为什么这样分割进行了讨论,并给出了地分割的相应设计原则。     

参考平面的分割

一个完整的地平面能减少电路板的EMI和串扰问题。在数模混合布板时,数字电路的同步开关噪声往往会影响敏感的模拟电路。分割的地平面能够提供高的噪声隔离度,但同时也会引起另外的一些EMI问题。文章就如何正确地分割地平面以及为什么这样分割进行了讨论,并给出了地分割的相应设计原则。     

电源与地平面间谐振电压噪声和阻抗特性仿真

多层PCB板中的电源与地平面间的谐振效应会引发电压噪声及电磁辐射问题。利用Cadence Sigrity软件,从电源和地平面间谐振电压噪声和阻抗特性两个维度对谐振效应进行了评估。通过控制变量,对比不同PCB设计下的仿真结果,发现增加去耦电容、减小平面间距和合理的平面分割方式可以降低谐振效应。     

EMI的最佳解决之道希普列上海办事处

一般来说,任何会产生电流的线路或设备都是潜在的EMI源。EMI指在通信或遥控中使用的可控电磁信号中的不可控的干扰。由于个人电脑、电视游戏和大量微处理器的增加,它们的频带噪声也相应大幅度增加。这样一来,就使EMI问题更严重了。由这些设备产生的EMI会对电子设备发生一个无关的信     

电动汽车充电桩电磁辐射测试研究

本文通过研究电动汽车充电原理,分析噪声生成机理及其传输路径,并利用无线电监测设施设备对充电桩辐射EMI噪声开展实地测试.理论分析与实验结果表明:电动汽车充电过程中,电能变换器的开关管通断状态高速切换会产生大量传导EMI噪声,并通过电源线传输至电网中;充电产生的高频噪声还会通过电路板向周围空间发射电磁波,形成辐射EMI噪...     

射频电子设备的辐射电磁干扰诊断与抑制技术研究

射频电子设备产生的电磁干扰(EMI)噪声包括传导干扰噪声和辐射干扰噪声。其中,辐射EMI噪声是以空间电磁场形式影响其它电子设备的。针对射频电子设备产生的辐射EMI噪声,该文分别建立因传输线缆与芯片时钟信号引起的辐射EMI噪声理论模型与等效电路。同时,还针对上述辐射EMI噪声理论模型提出了相应的噪声抑制方法。实验结果表明,采用该文中方法,某型家用液晶显示器的EMI噪声得到了很好的抑制,从而验证了方法的有效性。     

基于阈值法和区域生长法的图像分割算法研究

由于图像阈值法的直观性和易于实现的性质,使它在图像分割领域中处在中心地位,但是在阈值分割后不可避免地会出现与目标灰度接近的背景区域,从而产生了噪声干扰。由于图像分割技术的不断完善,区域生长法比较完美地解决了噪声干扰的问题,但是随之也会造成欠分割和过分割的现象,同样使得分割效果不理想。因此,本文采用阈值分割法和区域生长法相结合的方法,来尽可能避免目标本身灰度不均匀造成的欠分割现象和有效防止目标边界模糊造成的过分割现象。     

分割单元对电源/地平面输入阻抗影响的研究

研究了在多层印制电路板电源/地平面过孔周围布置具有桥接结构的蚀刻分割单元时过孔信号的返回路径阻抗及转移阻抗。分析了分割单元尺寸变化对返回路径阻抗的影响。采用二维边界元法进行了数值分析,并通过全波有限元分析软件进行了仿真验证。研究结果表明,在频率较高时,分割单元会激发较多的谐振峰值,返回路径阻抗大幅上升,但有助于降低噪声耦合。     

基于DC/AC逆变电源交/直流侧传导EMI噪声机理建模

针对DC/AC逆变电源交/直流侧的传导EMI噪声机理特性,提出直流侧噪声源内阻抗建模方法,理论分析了不同工作模式下交流侧的传导EMI噪声共模/差模噪声传输机理模型和控制参数影响下的噪声建模方法,最后对DC/AC逆变器直流侧噪声源内阻抗进行了提取实验,利用仿真分析控制参数对交流侧传导EMI噪声的影响,该研究内容为DC/AC逆变电源传导EMI问题的解决提供了一定的理论与实践参考。     

可抑制高频噪声的MIRCRO/Q1000/3000平面陶瓷去耦电容

为了降低"电源"和"地"的尖峰噪声,有效抑制EMI/RFI,CCI公司新近推出了两种可抑制高频噪声的平面型陶瓷去耦电容MIRCRO /Q 1000/3000;其中,MIRCRO/Q1000适用于模拟DIP封装的IC,可安装在IC的下方,共用PCB板上的DIP IC的"电源"和"地"安装孔.     

有限地平面上差分对共模噪声的分析

共模噪声是高速数字电路产生电磁干扰的主要原因,而共模电感又是共模噪声大小的决定因素。以多层板的微带线为模型,推导出在偏离地平面中心以及跨越不连续地平面的情况下,PCB上差分对共模电感的定量表达式,并对其共模噪声的特性进行了详细讨论。其结论可以帮助设计人员理解共模噪声产生机制,并针对具体电路走线定量分析,提前准确发现设计中潜在的问题。     

高速PCB镜像层设计

在高速多层PCB上,镜像层在噪声控制方面起着重要作用.良好的镜像层设计可以降低杂散电感引起的噪声,有助于控制串扰、反射和电磁干扰.本文结合作者的实际设计重点探讨了局部接地层的应用,并通过一个数模混合电路实例给出了一种镜像层分割法以及一些实践中需要注意的问题.     

An electromagnetic crystal power substrate with efficient suppression of power/ground plane noise on high-speed circuits

An electromagnetic crystal power substrate (ECPS) in a high-speed circuit package is proposed for suppressing the power/ground planes noise (P/GPN) and the corresponding electromagnetic interference (EMI). The ECPS is simply realized by periodically embedding the high dielectric-constant rods into the conventional package substrate between the continuous power and ground planes. With a small number of embedded rods and low rod filling ratio, the proposed ECPS design can efficiently eliminate the noise of 30dB in average within several designed stopbands. In addition, the radiation or EMI resulting from the P/GPN is also significantly reduced over 25dB in the stopbands. The excellent noise and EMI suppression performance for the proposed structure are verified both experimentally and numerically. Reasonably good consistency is seen.     

Numerical and experimental investigation of radiation caused by the switching noise on the partitioned DC reference planes of high speed digital PCB

Influence of the partitioning and bridging of the power/ground planes on the radiation caused by the switching noise on the dc reference planes is investigated both theoretically and experimentally. Based on the three-dimensional finite-difference time-domain modeling, the electromagnetic interference (EMI) performance of the partitioned power/ground planes is studied. Radiated emission at the 3-m distance from the tested boards is measured in a fully anechoic chamber. The measured and the numerical results agree generally well. The radiation behavior of four kinds of partitioned configuration of the power/ground planes is studied. It is found that completely isolating the noise source by the etched slits, or moats, significantly reduces the radiation level at the frequencies near resonance. However, bridges connecting two sides of the moat not only significantly degrade the ability of the EMI protection of the moat, but also excite a new low-frequency resonant mode. The effect of the geometrical parameters, such as the moat size, moat location, bridge width, and bridge position, on the radiation behavior of the printed circuit board is considered. The radiation mechanism of the EMI behavior of the partitioned dc reference planes is discussed.     

Quantifying EMI resulting from finite-impedance reference planes

Parasitic inductance in printed circuit board (PCB) geometries can detrimentally impact the electromagnetic interference (EMI) performance and signal integrity of high-speed digital designs. This paper identifies and quantifies the parameters that affect the inductance of some typical PCB geometries. Closed-form expressions are provided for estimating the inductances of simple trace and ground plane configurations     

HDI PCB的地平面设计

高密度印制电路板(PCB)设计中,地平面直接影响着整个电路性能和电磁兼容性能.该文基于3G无线终端电路实例,深入研究了高密度互连(HDI)PCB中的地平面设计,并提出了地平面的分割和缝合法,以及全屏蔽措施.采用该设计可以降低PCB中杂散电感引起的噪声,有助于降低信号间串扰、反射和电磁干扰.     

Analysis and suppression of SSN noise coupling between power/ground plane cavities through cutouts in multilayer packages and PCBs

The authors introduced a model of simultaneous switching noise (SSN) coupling between the power/ground plane cavities through cutouts in high-speed and high-density multilayer pack-ages and printed circuit boards (PCBs). Usually, the cutouts are used in multilayer plane structures to isolate the SSN of noisy digital circuits from sensitive analog circuits or to provide multiple voltage levels. The noise-coupling model is expressed in terms of the transfer impedance. The proposed modeling and analysis results are compared with measured data up to 10 GHz to demonstrate the validity of the model. It is demonstrated that the cutout is the major gate for SSN coupling between the plane cavities, and that substantial SSN coupling occurs between the plane cavities through the cutout at the resonant frequencies of the plane cavities. The coupling mechanism and characteristics of the noise coupling, from which a method of suppression of the SSN coupling evaluated was also analyzed and discussed. Proper positioning of the cutout and the devices at each plane cavity achieves significant noise suppression at certain resonant frequencies. The suggested suppression method of the SSN coupling was successfully proved by frequency domain measurement and time domain analysis.     

EMI mitigation with multilayer power-bus stacks and via stitchingof reference planes

General methods for reducing printed circuit board (PCB) emissions over a broad band of high frequencies are necessary to meet EMI requirements, as processors become faster and more powerful. One mechanism by which EMI can be coupled off a PCB or multichip module (MCM) structure is from high-frequency fringing electric fields on the DC power and reference planes at the substrate periphery. An approach for EMI mitigation by stitching multiple ground planes together along the periphery of multilayer PCB power-bus stacks with closely spaced vias is reported and quantified in this paper. Power-bus noise induced EMI and coupling from the board edges is the major concern herein. The EMI at 3 m for different via stitch spacing and layer thickness is modeled with the finite-difference time domain (FDTD) method. Design curves and an empirical equation are extracted from a parametric study to summarize the variation of the radiated EMI as a function of layer thickness and stitch spacing