A 14-ns 14-Mb CMOS DRAM with 300-mW active power

A 4-Mb high-speed DRAM (HSDRAM) has been developed and fabricated by using 0.7-μm L_eff CMOS technology with PMOS arrays inside n-type wells and p-type substrate plate trench cells. The 13.18-mm×6.38-mm chip, organized as either 512 K word×8 b or 1 M word×4 b, achieves a nominal random-access time of 14 ns and a nominal column-access time of 7 ns, with a 3.6-V V_cc and provision of address multiplexing. The high level of performance is achieved by using a short-signal-path architecture with center bonding pads and a pulsed sensing scheme with a limited bit-line swing. A fast word-line boosting scheme and a two-stage word-line delay monitor provide fast word-line transition and detection. A new data output circuit, which interfaces a 3.6-V V_cc to a 5-V bus with an NMOS-only driver, also contributes to the fast access speed by means of a preconditioning scheme and boosting scheme. Limiting the bit-line voltage swing for bit-line sensing results in a low power dissipation of 300 mW for a 60-ns cycle time     

Optimized sensing scheme of DRAMs

The half-V_cc sensing scheme of CMOS dynamic RAMs (DRAMs) has been analyzed. It has been found that fluctuations of the cell-plate bias must be taken into account since they can degrade the sense signal. An improvement is possible by connecting the bit lines to the cell plate and its half-V_cc generator during precharge. Optimum performance of the sense amplifier is achieved if the PMOS and NMOS latches are activated simultaneously. The advantages are: (1) the sensitivity is improved due to the elimination of the offset contribution caused by unmatched capacitive loads; (2) the sensing speed is enhanced due to faster sense signal amplification; and (3) the peak current is reduced since the NMOS latch does not lower the voltage level of both bit line and reference bit line     

Half-VCC sheath-plate capacitor DRAM cell withself-aligned buried plate wiring

A trench-capacitor DRAM cell called a half-V_CC sheath-plate capacitor (HSPC) cell has been developed using 0.6-μm-process technology. It is applicable to DRAMs with capacities of 16 Mb and over. The HSPC cell achieves a storage capacitance of 51 fF in a cell area of 4.2 μm² and excellent immunity (critical charge Q_c<35 fC) against alpha-particle injection. These advantages are achieved using a half-V_CC sheath-plate structure, a 5.5-nm SiO₂-equivalent Si ₃N₄-SiO₂ composite film, and three self-alignment technologies involving buried plate wiring, a sidewall contact and a pad for the bit-line contact. The device performance is evaluated using an experimental 2-kb array     

A variable precharge voltage sensing

A new DRAM sensing approach that uses variable precharge voltage has been developed and analyzed in simulations. It uses a voltage swing only on the bit-line connected to the accessed cell. The bit-line precharge voltage varies from one RAS cycle to the next, depending on the level of the data in the accessed cell. The reference voltage for bit-line sensing is given by a new reference-cell control circuit without using a reference-voltage generator. The current required for sensing decreases as the precharge voltage increases, resulting in reduced power without any reduction of the sensing signal. Detailed analysis shows that the sensing current is only 2/3 of that in 1/2 T_DD sensing, even in the worst case     

Low-power on-chip supply voltage conversion scheme forultrahigh-density DRAMs

In order to achieve 3.3-V 1-Gb DRAM and beyond, a new on-chip supply voltage conversion scheme that converts 3.3-V external supply voltage, V_ext, to lowered 1.5-V internal supply voltage, V_ent, without any power loss within the voltage converter is proposed. This scheme connects two identical DRAM circuits in series between V_ixt and V_ss. By operation of two DRAM circuits with the same clock timing, the voltage between two DRAMs, V_int, is automatically fixed to 1/2V_ext. Therefore, each upper and lower DRAM circuit can operate at lowered 1/2V_ext without use of the conventional voltage converter. This scheme was successfully verified by an experimental system using 4-Mb DRAMs. Utilizing the proposed scheme, power dissipation was reduced by as much as 50% and stable operation was achieved without access speed penalty     

A 64-Mb DRAM with meshed power line

A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t_RAS=50 ns (typical) at V_cc=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, a V_SS shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM was fabricated with 0.4-μm CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM     

Variable VCC design techniques forbattery-operated DRAMs

Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V_CC level; (2) compensation of DC generators, V_BB and V_PP, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V_CC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M×8) by simulation     

Production of uniform electrostatic fields by a slotted conductingspherical shell

A spherical structure that specifies electric potential on a spherical surface to produce a uniform electric field near the center of the sphere is considered. The surface is divided on lines of constant latitude (polar angle), and the resulting bands are constrained to have particular voltages. The particular case of three conducting surfaces with voltages V₁, 0, and -V₁ is considered in detail. Polar angles are determined that give the required uniformity of the field     

Internal chip ESD phenomena beyond the protection circuit

Input/output electrostatic discharge (ESD) circuit requirements call for good protection of the pin with respect to both the ground and the power bus pins. Although effective protection can be designed at the pin many cases of damage phenomena are known to occur internal to the chip beyond the protection circuit. Here, the issues of protection between V_DD and V_SS are discussed first. This is followed by examples of how protection circuit performance can be sensitive to internal chip layout, independent of its effective design. Several illustrative actual case studies are reported to emphasize the internal chip ESD phenomena and their adverse effects     

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with acharge-transfer presensing scheme

A charge-transfer presensing scheme (CTPS) for 0.8-V array operation with a 1/2 V_cc bit-line precharge achieves a five times larger readout voltage and 40% improvement in sensing speed compared with conventional sensing schemes. Operation over a 1.2- to 3.3-V range is achieved. A nonreset row block control scheme (NRBC) for power-consumption improvement in data-retention mode is proposed which decreases the charge/discharge number of the row block control circuit. By combining CTPS and NRBC, the data-retention current is reduced by 75%     

Junction degradation in bipolar transistors and the reliabilityimposed constraints to scaling and design

The stress-induced leakage current is predominantly a Shockley-Read-Hall-like generation-recombination current. As the stress progresses, the leakage current increases, eventually reaches a maximum and then decays. The leakage current lowers the current gain at low biases. It affects the narrow-emitter transistors more since it is proportional to the emitter edge length. But, its impact is less significant if the transistor is operated at a high V_be , as required by constant-current scaling. The loss of the current gain does not affect the circuit speed directly. Instead, it reduces the logic swing and thus the noise margin of the circuit. The design to absorb the degradation with a larger initial logic swing results in a speed penalty. The reverse-stress-induced junction degradation can be eliminated by properly designing the circuit There is no concern for emitter-coupled logic (ECL) circuits when the logic swing is less than the V_be of the transistors     

Electrical transport properties of crystalline siliconcarbide/silicon heterojunctions

The electrical transport properties of β-SiC/Si heterojunctions were investigated using current-voltage (I-V) and capacitance-voltage (C-V) characteristics. The heterojunctions were fabricated by growing n-type crystalline β-SiC films on p-type Si substrates by chemical vapor deposition (CVD). The I-V data measured at various temperatures indicate that at relatively high current, the heterojunction forward current is dominated by thermionic emission of carriers and can be expressed as exp(-qV_bi/kT ) exp(V/ηkT), where V_bi is the built-in voltage of the heterojunction and η(=1.3) is a constant independent of voltage and temperature. At lower current, defect-assisted multitunneling current dominates. The effective density of states and the density-of-states effective mass of electrons in the conduction band of SiC are estimated to be 1.7×10²¹ cm ^-3 and 0.78m₀, respectively. This study indicates that the β-SiC/Si heterojunction is a promising system for heterojunction (HJ) devices such as SiC-emitter heterojunction bipolar transistors (HBTs)     

A pseudomorphic AlGaAs/n+-InGaAs metal-insulator-dopedchannel FET for broad-band, large-signal applications

Molecular beam epitaxy (MBE)-grown L_g=1.7-μm pseudomorphic Al_0.38Ga_0.62As/n⁺-In_0.15Ga _0.85As metal-insulator-doped channel FETs (MIDFETs) are presented that display extremely broad plateaus in both f_T and f_max versus V_GS, with f_T sustaining 90% of its peak over a gate swing of 2.6 V. Drain current is highly linear with V_GS over this swing, reaching 514 mA/mm. No frequency dispersion in g _m up to 3 GHz was found, indicating the absence of electrically active traps in the undoped AlGaAs pseudoinsulator layer. These properties combine to make the pseudomorphic MIDFET highly suited to linear, large-signal, broadband applications     

An experimental 1.5-V 64-Mb DRAM

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V_CC voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 μm² crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 μm electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs     

A high-speed, small-area, threshold-voltage-mismatch compensationsense amplifier for gigabit-scale DRAM arrays

A high-speed small-area DRAM sense amplifier with a threshold-voltage (V_T) mismatch compensation function is proposed. This sense amplifier features a novel hierarchical data-line architecture with a direct sensing scheme that uses only NMOS transistors in the array, and simple V_T mismatch compensation circuitry using a pair of NMOS switching transistors. The layout area of the sense amplifier is reduced to 70% of that of a conventional CMOS common I/O sense amplifier due to the removal of PMOS transistors from the array. The readout time is improved to 35% of that of a conventional CMOS sense amplifier because of direct sensing and a 1/10 reduction in V_T mismatch. This sense amplifier eliminates the sensitivity degradation and the area overhead increase that are expected in gigabit-scale DRAM arrays     

New DRAM noise generation under half-Vccprecharge and its reduction using a transposed amplifier

Dynamic RAM (DRAM) data-line interface noise generated during amplification, the key problem in designing 16 Mbit and higher DRAMs, is investigated. It is reported that: (1) in the half-V_cc approach, specific combinations of signal types (high and low) and CMOS sense-amplifier operating sequences cause interference noise during amplification; (2) interference noise exists in sense amplifiers; and (3) the noise results in a detrimental effect on data holding time characteristics. The interference noise is overcome by a transposed amplifier structure combined with a transposed data-line structure     

Deep-submicrometer BiCMOS circuit technology for sub-10-ns ECL 4-MbDRAM's

A 0.3-μm sub-10-ns ECL 4-Mb BiCMOS DRAM design is described. The results obtained are: (1) a V_cc connection limiter with a BiCMOS output circuit is chosen due to ease of design, excellent device reliability and layout area; (2) a mostly CMOS periphery with a specific bipolar use provides better performances at high speed and low power; (3) the direct sensing scheme of a single-stage MOS preamplifier combined with a bipolar main amplifier offers high speed; and (4) the strict control of MOS transistor parameters has been proven to be more important in obtaining high speed DRAMs, based on the 4-Mb design     

A 1.544-Mb/s CMOS line driver for a 22.8-Ω load

A CMOS line driver for high-speed data communication according to the T1 and CEPT recommendations is presented. The differential output swing is 7.2 V_pp on a load of 22.8 Ω from a single 5-V supply. A novel quiescent current control scheme is used. The driver occupies an area of 6.5 mm² using a 2-μm p-well CMOS technology     

Ultrafast compact 32-bit CMOS adders in multiple-output dominologic

A dynamic CMOS logic style, called multioutput domino logic (MODL), has been developed. In this logic style, single logic gates produce multiple functions, and a circuit's device count can be reduced by a factor of more than 2, depending on the degree of recurrence in the circuit. In addition, MODL circuits are, by construction, considerably more stable than other dynamic circuits including conventional domino. A 32-bit carry lookahead (CLA) structure which reduces the adder's worst-case path by two logic stages has also been devised. This CLA structure has been developed to effectively utilize the advantages of MODL. Taken together, these developments have resulted in two 32-bit CMOS adders, providing area and speed improvements of 1.5× and 1.7× over the combination of the domino and conventional CLA techniques. Both adders have been fabricated in a standard 0.9-μm two-level metal CMOS technology, and measured results show that the straight adder has achieved 32-bit addition times of less than 3.1 ns at 25°C with V_DD+5.0 V     

A Low-Power SRAM Using Bit-Line Charge-Recycling

Low-power SRAM design is crucial since it takes a large fraction of total power and die area in high-performance processors. Reducing voltage swing of the bit-line is an effective way to save the power dissipation in write cycles. Voltage swing reduction of bit-lines is, however, limited due to possible write-failures. We propose a new low-power SRAM using bit-line charge recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obtained by recycled charge from its adjacent bit-line capacitance, instead of the power line. Applying such a charge recycling technique to the bit-line significantly reduces write power. A test chip with 32 Kbits (256 rows x 128 columns) is fabricated and measured in 0.13 mum CMOS to demonstrate operation of the proposed SRAM. Measurement results show 88% reduction in total power during write cycles compared to the conventional SRAM (CON-SRAM) at V_DD = 1.5 V and f = 100 MHz.