模块级可重构计算机HIT—FTC2的冗余管理

本文介绍了模块级可重构计算机ＨＩＴ－ＦＴＣ２的冗余管理技术、包括：故障检测，故障屏蔽，故障隔离，系统重构与故障恢复等技术。     

分布式系统的故障管理与应用动态重构

针对分布式系统故障检测困难以及容错性差的问题,提出一种分布式系统的故障管理与应用动态重构技术,对不同故障来源的问题进行分类处理,通过故障管理软件以及系统管理软件快速定位并处理故障信息,将重构处理进行记录并在之后快速复现重构解决过程,同时利用动态地址配置技术对重构的应用所需内存大小和地址进行映射管理,利用动态重构技术将故...     

多旋翼无人机执行机构故障重构技术研究

多旋翼无人机应用中一旦发生执行机构故障,将会危及无人机、地面人员与周围环境的安全。研究多旋翼无人机的执行机构故障重构技术有利于对其实施容错控制,提高运行的安全性和可靠性。首先对多旋翼无人机执行机构故障进行分类,建模分析了执行机构卡死和失效两类故障,建立了故障下六旋翼无人机的数学模型,然后分别设计基于自适应观测器的故障重构方法。通过选取合适的自适应律,自动调节非线性观测器的参数,实现对故障信息的精确重构。仿真结果证明了故障重构方法的准确性。     

基于功能重构的电路故障修复技术研究

电路故障存在定位和修复比较难的问题,基于功能重构的故障修复技术解决了这一问题.该方法是将测试过程中的响应值和实际电路的响应值进行比较,实现故障的精确定位.确定故障之后采用功能重构的原理对故障电路进行修复,从整体上降低了电路的修复难度.     

分布式多处理机交换系统重构的实现

分布式多处理机系统的容错性是它的一个基本特征。这方面的研究包括系统模块单元故障的检测和诊断技术及相应的自动修复和重构技术,以提高系统的强健性和可用性。本文阐述了分布式多处理机系统的重构所应解决的问题,如对故障的自动识别、故障隔离、故障修复等问题进行了分析,研究了实现方法。     

微小型MEMS惯性导航系统的六陀螺余度配置实现

为了有效提高捷联惯性导航系统的可靠性，本文对微小型MEMS-IMU系统的余度配置实现进行了研究。针对典型的非正交配置方案（六传感器正十二面体），进行了工程实现。并将余度系统和小型导航计算机相连，搭建成完整的微小型余度捷联惯性导航系统。研究了系统的故障检测、隔离以及系统的重构技术，并将直接比较测量法和最小二乘加权法分别作为故障检测和系统重构工程实现方案，实现了余度系统中LMU数据的采集、故障检测、识别、隔离、系统重构、解算导航参数等一系列功能。试验表明，实现了微型化的余度惯性导航系统，为进一步的研制与开发打下了坚实的基础。     

基于自适应PID技术的无尾飞机容错重构控制

无尾飞机是新型飞机的发展方向,与传统的飞机相比,其飞行控制系统更为复杂,故障出现的概率也更大,因此重构控制系统是无尾飞机安全飞行的保障.采用基于自适应PID技术的动态逆控制来研究无尾飞机的重构控制系统,并获得了相应的仿真结果,证实了基于自适应PID技术的动态逆控制对故障具有较好的重构能力,比单独使用动态逆控制更有效.     

开放式综合通信导航识别系统重构设计

本文介绍了开放式、模块化综合通信导航识别（CNI）系统的特征及基于功能分区的综合化设计方法,并针对典型综合CNI系统的构型开展系统重构设计,提取系统重构要素和可重构资源,最后对任务重构和故障重构开展了详细的流程设计。这些方法和技术已在实际工程中成功应用。     

可重构硬件芯片级故障定位与自主修复方法

 外部集中控制的可重构硬件容错系统,其重构控制算法复杂、重构时间开销大,且存在单点失效问题.本文研究芯片级分布式在线自主容错技术,提出了能够实现芯片级自修复的新型可重构硬件细胞阵列结构,阐述了互连资源的在线故障定位和自主修复方法.设计了功能细胞电路和容错开关块电路,采用分段定位法检测互连资源中多路器故障和连线开路故障,通过重配置布线和线移位操作分别实现多路器与连线故障自修复.以4位串并乘法器电路为例进行实验验证,分析了容错设计的硬件开销与时间开销,实验结果表明新方案的容错时间短、资源利用率高.     

飞行控制计算机余度管理策略研究

为满足系统可靠性指标的要求,采用了余度技术,研制了双通道余度飞行控制计算机.在该研究对象的基础上,进行了一种硬件冗余和软件管理的余度管理策略的研究和设计,提出了多余度信号监控表决算法、基于CAN总线的故障检测机制和系统重构与恢复的方法.故障注入实验表明,样例余度飞行控制计算机在遇到故障时能够实时检测出故障,诊断故障类型,并对故障进行处理,完成系统重构,提高了飞行控制系统的任务可靠性,保证无人机的飞行安全.     

Characterization, testing and reconfiguration of faults in mesh networks

Achieving fault-tolerance through incorporation of redundancy and reconfiguration is quite common. The distribution of faults can have several impacts on the effectiveness of any reconfiguration scheme; in fact, patterns of faults occurring at strategic locations may render an entire VLSI system unusable regardless of its component redundancy and its reconfiguration capabilities. Such fault patterns are called catastrophic fault patterns (CFPs). In this paper, we characterize catastrophic fault patterns in mesh networks when the links are bidirectional or unidirectional. We determine the minimum number of faults required for a fault pattern to be catastrophic. We consider the problem of testing whether a fault pattern is catastrophic. When a fault pattern is not catastrophic we study the problem of finding optimal reconfiguration strategies, where optimality is with respect to either the number of processing elements in the reconfigured network (the reconfiguration is optimal if such a number is maximized) or the number of bypass links to activate in order to reconfigure the array (the reconfiguration is optimal if such a number is minimized). The problem of finding a reconfiguration strategy that is optimal with respect to the size of the reconfigured network is NP-complete, when the links are bidirectional, while it can be solved in polynomial time, when the links are unidirectional. Considering optimality with respect to the number of bypass links to activate, we provide algorithms which efficiently find an optimal reconfiguration.     

一种有效的电路容错结构及其成品率分析

本文提出了一种有效的电路容错结构,给出了一种重组算法.按照这种重组算法,对该结构的成品率进行了分析,并给出了其成品率的表达式.最后,通过电路设计和分析说明了该容错结构的有效性.     

航空发动机传感器故障诊断与自适应重构控制

针对航空发动机控制系统中最易发生故障的传感器,提出了基于状态观测器的故障诊断与自适应重构控制方法.设计了多个状态观测器用于传感器的状态估计,采用阈值判别法对传感器进行实时故障监视与诊断,并用正常传感器测量值的加权均值代替故障传感器测量值反馈回闭环系统,实现了对发动机闭环系统的自适应重构控制.数字仿真结果表明,该方法能及时准确地定位故障,并进行有效的自适应重构控制,将其应用于航空发动机的故障诊断与自适应重构控制是可行、有效的.     

The distributed voting strategy for fault diagnosis and reconfiguration of linear processor arrays

A new strategy for fault diagnosis and reconfiguration of linear processor arrays is proposed. This strategy can be implemented in a distributed manner, suitable for arrays with a large number of processors such as those implemented by VLSI and WSI techniques. The proposed fault diagnosis is based on the distributed voting technique. Additional links are added for fault diagnosis. These links are also used, when there is a processor failure, for communication between the processors. Some reconfiguration schemes are also presented emphasizing the distributed approach.     

On the optimal reconfiguration of multipipeline arrays in thepresence of faulty processing and switching elements

The reconfiguration of multipipeline arrays in the presence of both faulty processing elements (PEs) and switching elements (SEs) is addressed. Different fault models are used for the PEs and SEs: a PE can be either fault free or faulty; a SE is modeled using a novel functional approach which relates its switching capabilities to its status. This permits a PE to retain a partial functionality in the presence of a fault. An appropriate transformation of the multipipeline array reconfiguration problem to a maximum flow problem is then presented. The conditions under which this transformation is possible, are fully analyzed. A reconfiguration algorithm based on the maximum flow algorithm is presented; the proposed algorithm is optimal as the number of reconfigured pipelines is maximized     

Dynamic reconfiguration schemes for megabit BiCMOS SRAMs and performance evaluation

In this paper two dynamic configuration schemes are discussed for megabit BiCMOS static random access memories (SRAMs). Dynamic reconfiguration schemes allows failure detection at the chip level and automatic reconfiguration to fault free memory cells within the chip. The first scheme is a standby system approach where the I/O lines of the memory can be dynamically switched to spare bit slices in the SRAM. This scheme is implemented through a switching network at the memory interface. Every memory access is controlled by a fault status table (FST) which memorizes the fault conditions of each memory block. This FST is implemented outside the memory system. A second dynamic reconfiguration scheme for BiCMOS SRAMs is addressed through a graceful degradation approach. Basic design considerations and performance evaluation of megabit BiCMOS SRAMs using dynamic reconfiguration schemes are presented. The basic properties of the proposed schemes and a prototype VLSI chip implementation details are discussed. BiCMOS SRAM access time improvement of about 35%, chip area of 25%, and chip yield of 10% are achieved, respectively, as compared to conventional methods. A comparison of reliability improvement of 1 Mb BiCMOS SRAMs using dynamic configuration schemes is presented. These two dynamic reconfiguration schemes have considerable importance in reliability improvement when compared to conventional methods. The major advantage is that the size of reconfiguration of the system can be considerably reduced.     

Schemes of dynamic redundancy for fault tolerance in random accessmemories

For large memory capacities, stand-by systems usually need a considerable amount of redundant hardware, not only because of the spare components, but for storing fault conditions and for carrying out the necessary reconfiguration. As alternatives, two methods of implementing fault tolerance by means of dynamic redundancy in random-access memories are proposed which allow the treatment of memory-chip faults at the interface of the memory. The memory reliability for both approaches is estimated by a simple model. These methods improve the reliability considerably compared to conventional memory fault tolerance methods, and the size of the units of reconfiguration can be tailored to the demands of the system user     

Fault Diagnosis and Reconfiguration for Multilevel Inverter Drive Using AI-Based Techniques

A fault diagnostic and reconfiguration method for a cascaded H-bridge multilevel inverter drive (MLID) using artificial-intelligence-based techniques is proposed in this paper. Output phase voltages of the MLID are used as diagnostic signals to detect faults and their locations. It is difficult to diagnose an MLID system using a mathematical model because MLID systems consist of many switching devices and their system complexity has a nonlinear factor. Therefore, a neural network (NN) classification is applied to the fault diagnosis of an MLID system. Multilayer perceptron networks are used to identify the type and location of occurring faults. The principal component analysis is utilized in the feature extraction process to reduce the NN input size. A lower dimensional input space will also usually reduce the time necessary to train an NN, and the reduced noise can improve the mapping performance. The genetic algorithm is also applied to select the valuable principal components. The proposed network is evaluated with simulation test set and experimental test set. The overall classification performance of the proposed network is more than 95%. A reconfiguration technique is also proposed. The proposed fault diagnostic system requires about six cycles to clear an open-circuit or short-circuit fault. The experimental results show that the proposed system performs satisfactorily to detect the fault type, fault location, and reconfiguration.     

On-Line Fault Resilience Through Gracefully Degradable ASICs

We present two novel reconfiguration schemes, L/U reconfiguration and its generalization, band reconfiguration, to achieve graceful degradation for general microarchitecture datapaths. Upon detection of a datapath fault, hardware and algorithmic reconfigurations are performed dynamically through operation rescheduling and hardware rebinding. Instead of a complete shuffling, the proposed scheme perturbs the original schedule and binding in a systematic fashion. This regularity of the scheme allows well-structured design planning for the controller and the datapath. The underlying microarchitecture supporting such reconfiguration schemes is briefly outlined. Experimental evidence indicates negligible performance and small hardware overheads.     

基于神经网络的单通道冗余VLSI/WSI阵列重构算法

本文提出了一个基于Hopfield网络的单通道冗余VLSI/WSI阵列重构算法,根据阵列中缺陷单元的分布情况,构造相应的矛盾图模型,将阵列的重构问题转化为求矛盾图的独立集且使得独立集的顶点数恰为缺陷单元的个数,有效地解决了阵列的重构问题.实验结果表明,与传统的启发式方法相比,基于本文所提出的图论模型而采用的神经网络方法是一种简单、快速、高效的算法.