采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路--complementary pass-transistor adiabatic logic(CPAL).电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MOSIS的0.25μm CMOS工艺,在50～200MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2N-2N2P电路的50%和35%.     

二种EPAL绝热开关电路

研究和设计了两种低功耗的EPAL(efficientPAL)绝热开关电路.这两种电路均采用逐级相位落后90°的四相正弦功率时钟.讨论了EPAL电路的设计方法,并在不同时钟频率和不同的负载条件下用1.2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟.模拟结果表明这两类电路均能完成正确的逻辑功能.两种EPAL的五级反相器/缓冲器电路在功率时钟频率为10MHz时都比相应的PAL-2N电路节省80%以上的功耗,在400MHz时功耗节省也分别可达23%和50%.EPAL电路可以工作于更高的时钟频率,有更强的驱动负载能力和更低的输出波形畸变     

二种EPAL绝热开关电路

研究和设计了两种低功耗的EPAL(efficient PAL)绝热开关电路.这两种电路均采用逐级相位落后90°的四相正弦功率时钟.讨论了EPAL电路的设计方法,并在不同时钟频率和不同的负载条件下用1.2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟.模拟结果表明这两类电路均能完成正确的逻辑功能.两种EPAL的五级反相器/缓冲器电路在功率时钟频率为10MHz时都比相应的PAL-2N电路节省80%以上的功耗,在400MHz时功耗节省也分别可达23%和50%.EPAL电路可以工作于更高的时钟频率,有更强的驱动负载能力和更低的输出波形畸变.     

采用三相电源的互补传输管绝热逻辑电路

提出了一种由三相电源驱动的新绝热逻辑电路——complementary pass- transistor adiabatic logic (CPAL ) .电路由CPL电路完成相应的逻辑运算,由互补传输门对输出负载进行绝热驱动,电路的整体功耗较小.指出选取合适的输出驱动管的器件尺寸可进一步减小CPAL电路的总能耗.设计了仅由一个电感和简单控制电路组成的三相功率时钟产生电路.为了验证提出的CPAL电路和时钟产生电路,设计了8bit全加器进行模拟试验.采用MO-SIS的0 .2 5μm CMOS工艺,在5 0～2 0 0 MHz频率范围内,CPAL全加器的功耗仅为PFAL电路和2 N - 2 N2 P电路的5 0 %和35 % .     

三种低压高速低耗BiCMOS三态逻辑门

采用0.35μm B iCM O S工艺技术,设计了三种高性能的B iCM O S三态逻辑门电路,并提出了改进三态门电路结构和优化器件参数的方法和措施。仿真和实验结果表明,所优化设计的B iCM O S三态门的电源电压均小于3.3 V,工作速度比常用的CM O S三态门快约5倍,功耗在60 MH z下仅高出约2.2~3.7 mW,而延迟-功耗积却比该常用的CM O S三态门平均降低了38.1%,因此它们特别适用于低压、高速、低功耗的数字系统。     

绝热无比型动态触发器和同步时序电路综合

该文从电路三要素理论出发研究低功耗电路，定量描述绝热无比型动态记忆电路。绝热无比型动态触发器利用电容接收和保存信息，避免目前绝热电路中电容上的信息得而复失的现象，其中绝热D和T'触发器只用6管，带‘与或非’输入的绝热D触发器只用9管。在上述理论基础上该文提出绝热无比型动态同步时序电路综合方法，用此法设计出绝热5421BCD码十进制计数器，仅用32管，总功耗小于一个PAL－2N四位二进制计数器的功耗，计算机模拟验证该文方法正确。     

具有预计算功能的新型绝热数值比较器设计

该文通过对钟控传输门绝热逻辑(Clocked Transmission Gate Adiabatic Logic,CTGAL)电路和数值比较器电路工作原理及结构的研究,提出了一种基于CTGAL电路的具有预计算功能的新型绝热数值比较器设计方案。该方案具有冗余抑制作用,将其与利用PAL-2N电路设计的低功耗绝热数值比较器相比,功耗节省平均约60%。PSPCIE模拟结果表明,此数值比较器逻辑功能正确,低功耗特性明显。     

具有反馈结构的PAL-2NF电路

在分析PAL-2N电路缺陷产生原因的基础上,提出了一种低功耗,具有反馈结构的PAL-2NF电路,它采用逐级相位落后90°的四相正弦功率时钟.讨论了PAL-2NF电路的设计方法,并在不同时钟频率下用1.2μm的CMOS工艺参数对所设计的电路进行PSPICE模拟,电路能完成正确的逻辑功能.五级级联的PAL-2NF反相器/缓冲器电路在功率时钟频率10MHz时都比相应的PAL-2N电路节省93%以上的功耗,在400MHz时功耗节省也可达40%.由于几乎完全消除了输出端的悬空现象和逻辑0的"第三态"现象,PAL-2NF电路可以工作于更高的时钟频率和更低的输出波形畸变.     

一个利用线性区MOS管补偿的射频放大器

研究了一种采用线性化技术的低电压CM O S射频放大器。电路中,并联一个工作在线性区的M O S管来提高其线性。采用SM IC的0.18μm工艺,流片测试结果显示,该电路用很小的功耗代价将放大器的输入三阶交截点功率提高了大约5 dB。     

低功耗0.35μm CMOS 2.5Gb/s 16∶1复接器设计

采用0.35μm CM O S工艺设计了用于光纤传输系统的低功耗16∶1复接器,实现了将16路155.52M b/s数据复接成一路2.5G b/s的数据输出的功能。该复接器以混合结构形式实现:低速部分采用串行结构,高速部分采用树型结构。具体电路由锁存器、选择器及分频器组成,以CM O S逻辑和源极耦合逻辑(SCL)实现。用Sm art SP ICE软件进行仿真的结果显示:在3.3V供电时,整体电路的复接输出最高工作速度可达3.5G b/s,功耗小于300mW。     

nMOS reversible energy recovery logic for ultra-low-energyapplications

We propose a new fully reversible adiabatic logic, nMOS reversible energy recovery logic (nRERL), which uses nMOS transistors only and a simpler 6-phase clocked power. Its area overhead and energy consumption are smaller, compared with the other fully adiabatic logics. We employed bootstrapped nMOS switches to simplify the nRERL circuits. With the simulation results for a full adder, we confirmed that the nRERL circuit consumed substantially less energy than the other adiabatic logic circuits at low-speed operation. We evaluated a test chip implemented with 0.8-μm CMOS technology, which included a chain of nRERL inverters integrated with a clocked power generator. The nRERL inverter chain of 2400 stages consumed the minimum energy at V_dd=3.5 V at 55 kHz, where the adiabatic and leakage losses are about equal, which is only 4.50% of the dissipated energy of its corresponding CMOS circuit at V_dd=0.9 V. In conclusion, nRERL is more suitable than the other adiabatic logic circuits for the applications that do not require high performance but low energy consumption     

A Low Power High-Speed 8-Bit Pipelining CLA Design Using Dual-Threshold Voltage Domino Logic

A high speed and low power 8-bit carry-lookahead adder using two-phase modified dual-threshold voltage (dual-V_t) domino logic blocks which are arranged in a programmable logical array-like design style with pipelining is presented. The modified domino logic circuits employ dual-transistors and reversed bulk-source biases for reducing subthreshold leakage current when advanced deep submicrometer process is used. Moreover, an nMOS transistor is inserted in the discharging path of the output inverter such that the modified domino logic can be properly applied in a pipeline structure to reduce the power consumption. The addition of two 8-bit binary operands is executed in two cycles. Not only is it proven to be also suitable for long adders, the dynamic power consumption is also drastically reduced by more than 10% by the measurement results on silicon.     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

A 3.8-ns CMOS 16×16-b multiplier using complementarypass-transistor logic

A 3.8-ns, 257-mW, 16×16-b CMOS multiplier with a supply voltage of 4 V is described. A complementary pass-transistor logic (CPL) is proposed and applied to almost the entire critical path. The CPL consists of complementary inputs/outputs, an nMOS pass-transistor logic network, and CMOS output inverters. The CPL is twice as fast as conventional CMOS due to lower input capacitance and high logic functionality. Its multiplication time is the fastest ever reported, even for bipolar and GaAs ICs, and it can be enhanced further to 2.6 ns with 60 mW at 77 K     

准静态单相能量回收逻辑

提出了一种新的准静态单相能量回收逻辑,其不同于以往的能量回收逻辑,真正实现了单相功率时钟,且不需要任何额外的辅助控制时钟,不但降低了能耗,更大大简化了时钟树的设计.该逻辑还可以达到两相能量回收逻辑所具有的速度.设计了一个8位对数超前进位加法器,并分别用传统的静态CMOS逻辑、钟控CMOS绝热逻辑(典型的单相能量回收逻辑)和准静态单相能量回收逻辑实现.采用128组随机产生的输入测试向量的仿真结果表明:输入频率为10MHz时,准静态能量回收逻辑的能耗仅仅是传统静态CMOS逻辑的45%;当输入频率大于2MHz时,可以获得比时钟控CMOS绝热逻辑更低的能耗.     

Low-power logic styles: CMOS versus pass-transistor logic

Recently reported logic style comparisons based on full-adder circuits claimed complementary pass-transistor logic (CPL) to be much more power-efficient than complementary CMOS. However, new comparisons performed on more efficient CMOS circuit realizations and a wider range of different logic cells, as well as the use of realistic circuit arrangements demonstrate CMOS to be superior to CPL in most cases with respect to speed, area, power dissipation, and power-delay products. An implemented 32-b adder using complementary CMOS has a power-delay product of less than half that of the CPL version. Robustness with respect to voltage scaling and transistor sizing, as well as generality and ease-of-use, are additional advantages of CMOS logic gates, especially when cell-based design and logic synthesis are targeted. This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern     

Circuit techniques for CMOS low-power high-performance multipliers

In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-μm CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16×16)-b multiplier using the Booth algorithm, a (6×6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6×6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS     

A 4.4 ns CMOS 54×54-b multiplier using pass-transistormultiplexer

A 54×54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 μm CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54×54-b multiplier is 3.77×3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply     

Low-power design techniques for high-performance CMOS adders

A high-performance adder is one of the most critical components of a processor which determines its throughput, as it is used in the ALU, the floating-point unit, and for address generation in case of cache or memory access. In this paper, low-power design techniques for various digital circuit families are studied for implementing high-performance adders, with the objective to optimize performance per watt or energy efficiency as well as silicon area efficiency. While the investigation is done using 100 MHz, 32 b carry lookahead (CLA) adders in a 0.6 μm CMOS technology, most techniques presented here can also be applied to other parallel adder algorithms such as carry-select adders (CSA) and other energy efficient CMOS circuits. Among the techniques presented here, the double pass-transistor logic (DPL) is found to be the most energy efficient while the single-rail domino and complementary pass-transistor logic (CPL) result in the best performance and the most area efficient adders, respectively. The impact of transistor threshold voltage scaling on energy efficiency is also examined when the supply voltage is scaled from 3.5 V down to 1.0 V