Mobile satellite reception with a virtual satellite dish based on a reconfigurable multi-processor architecture

Traditionally, mechanically steered dishes or analog phased array beamforming systems have been used for radio frequency receivers, where strong directivity and high performance were much more important than low-cost requirements. Real-time controlled digital phased array beamforming could not be realized due to the high computational requirements and the implementation costs. Today, digital hardware has become powerful enough to perform the massive number of operations required for real-time digital beamforming. With the continuously decreasing price per transistor, high performance signal processing has become available by using multi-processor architectures. More and more applications are using beamforming to improve the spatial utilization of communication channels, resulting in many dedicated digital architectures for specific applications. By using a reconfigurable architecture, a single hardware platform can be used for different applications with different processing needs.In this article, we show how a reconfigurable multi-processor system-on-chip based architecture can be used for phased array processing, including an advanced tracking mechanism to continuously receive signals with a mobile satellite receiver. An adaptive beamformer for DVB-S satellite reception is presented that uses an Extended Constant Modulus Algorithm to track satellites. The receiver consists of 8 antennas and is mapped on three reconfigurable Montium TP processors. With a scenario based on a phased array antenna mounted on the roof of a car, we show that the adaptive steering algorithm is robust in dynamic scenarios and correctly demodulates the received signal.     

基于SoPC的嵌入式文字识别系统设计

设计了一种基于SoPC的嵌入式文字识别系统。在FPGA平台下,基于SoPC框架搭建软硬件协同系统,设计硬件电路完成文字图像的采集和预处理,嵌入Linux系统,使用其下的识别引擎完成文字图像的识别。采用Altera公司的SoPC builder构建系统框架,Quartus II完成硬件电路的设计,在宿主机Linux环境下完成了软件部分的交叉编译并嵌入到FPGA平台。整体设计在DE2-70开发板上完成了系统验证。     

Exploiting IEEE 1355 Routable Serial Links in a Real-Time Vision Architecture

A multi-processor machine vision system typically uses several different interconnection technologies to satisfy its various communication needs. This paper describes a machine vision architecture which uses high-speed packet-switched serial links (based on Inmos DS-links and conforming to the IEEE 1355 standard) as itssolecommunication technology. This technology offers significant advantages in terms of configurability, modularity, and scalability. It leads to an efficient ‘building block’ approach to constructing tightly coupled vision machines for specific applications from a general purpose set of modules. We are building a demonstrator system combining T9000 transputers with our own hardware modules which perform image I/O, correlation, and convolution; and message multi-casting modules. All modules conform to the industry standard HTRAM format. The paper discusses the implementation issues surrounding the use of the T9000, C104, and C101 DS-link components, and shows how they may be used to integrate hardware and software processing modules into a single conceptual model.     

CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications

Future embedded systems demand multi-processor designs to meet real-time deadlines. The large number of applications in these systems generates an exponential number of use-cases. The key design automation challenges are designing systems for these use-cases and fast exploration of software and hardware implementation alternatives with accurate performance evaluation of these use-cases. These challenges cannot be overcome by current design methodologies which are semi-automated, time consuming and error prone.In this paper, we present a fully automated design flow to generate communication assist (CA) based multi-processor systems (CA-MPSoC). A worst-case performance model of our CA is proposed so that the performance of the CA-based platform can be analyzed before its implementation. The design flow provides performance estimates and timing guarantees for both hard real-time and soft real-time applications, provided the task to processor mappings are given by the user. The flow automatically generates a super-set hardware that can be used in all use-cases of the applications. The software for each of these use-cases is also generated including the configuration of communication architecture and interfacing with application tasks.CA-MPSoC has been implemented on Xilinx FPGAs for evaluation. Further, it is made available on-line for the benefit of the research community and in this paper, it is used for performance analysis of two real life applications, Sobel and JPEG encoder executing concurrently. The CA-based platform generated by our design flow records a maximum error of 3.4% between analyzed and measured periods. Our tool can also merge use-cases to generate a super-set hardware which accelerates the evaluation of these use-cases. In a case study with six applications, the use-case merging results in a speed up of 18 when compared to the case where each use-case is evaluated individually.     

基于SoPC的前端RapidIO接口设计

针对现代高性能嵌入式系统高速RapidIO信号接入的应用需求,提出一种基于可编程片上系统(SoPC)的前端RapidIO接口设计方案,以VirtexII Pro现场可编程门阵列芯片为核心,利用RapidIO IP核等库资源及硬件编程实现RapidIO接口、低压差分信号图像接口、RS422控制接口间的信息转发逻辑。该方案能够提高信息采集和输出的时效性。     

基于深度学习的实时图像目标检测系统设计

针对图像目标检测的嵌入式实时应用需求,采用合并计算层的方法对基于MobileNet和单发多框检测器(SSD)的深度学习目标检测算法进行了优化,并采用软硬件结合的设计方法,基于ZYNQ可扩展处理平台设计了实时图像目标检测系统。在系统中,根据优化后的算法设计了一款多处理器核的深度学习算法加速器,并采用PYTHON语言设计了系统的软件。经过多个实验测试,深度学习目标检测系统处理速度可以达到45FPS,是深度学习软件框架在CPU上运行速度的4.9倍,在GPU上的1.7倍,完全满足实时图像目标检测的需求。     

基于帧间差分法的目标检测研究与FPGA实现

针对以往帧间差分算法的硬件实现架构中数据同步信号设计复杂,调试周期较长的特点,设计了一种新型的硬件算法架构。整个系统基于Altera的Cyclone Ⅳ E系列进行开发,采用镁光的SDRAM作为高速储存器件,豪威科技的OV5640作为图像采集器件。该系统对采集到的原始图像数据进行灰度化处理,利用硬件差分算法模块对灰度图像进行差分处理与二值化,实现对视频图像中动态目标的捕捉。基于Quratus Ⅱ与Modelsim联合开发平台对系统进行硬件设计和功能模块仿真。硬件测试结果表明,系统能够清晰地检测出视频中的动态目标,且具备较好的实时性。     

可进化芯片的FPGA接口设计与实现

针对FPGA IP核在可进化可编程系统芯片(SoPC)中嵌入时存在FPGA IP核端口时序控制和位流下载的问题,实现一种适用于可进化SoPC芯片的FPGA接口。该FPGA接口使用异步FIFO、双口RAM的结构和可扩展的读/写命令传输方式来实现FPGA IP核与系统的异步通信。嵌入式CPU可以通过FPGA接口实现FPGA IP核的片内位流配置。FPGA接口中的硬件随机数发生器实现进化算法的硬件加速。使用自动验证平台与FPGA原型验证平台对FPGA接口进行验证来实现验证的收敛。测试结果表明,FPGA接口成功实现了嵌入式CPU与FPGA IP核的通信,完成芯片内的进化。     

基于FPGA的实时视频处理平台设计

为了能够实时地采集、处理、显示视频,设计并实现了一种基于双PowerPC硬核架构的实时视频处理平台;用硬件实现视频的预处理算法,并以用户IP核的形式添加到硬件系统中,上层的视频处理软件程序则直接从存储器中调用预处理后的图像数据;重点介绍了在FPGA上构建双PowerPC硬核架构的硬件系统;采用乒乓控制算法缓存一行图像数据;用DMA的方式将图像数据保存在存储器中;以边缘检测作为视频预处理算法的一个实例,在平台上实现,实验结果表明,用本平台实现仅需40ms;本平台能够实时处理视频,具有较高的实用价值。     

A multi-processor NoC-based architecture for real-time image/video enhancement

The paper presents a multi-processor architecture for real-time and low-power image and video enhancement applications. Differently from other state-of-the-art parallel architectures the proposed solution is composed of heterogeneous tiles. The tiles have computational and memory capabilities, support different algorithmic classes and are connected by a novel Network-on-Chip (NoC) infrastructure. The proposed packet-switched data transfer scheme avoids communication bottlenecks when more tiles are working concurrently. The functional performances of the NoC-based multi-processor architecture are assessed by presenting the achieved results when the platform is programmed to support different enhancement algorithms for still images or videos. The implementation complexity of the NoC-based multi-tile platform, integrated in 65 nm CMOS technology, is reported and discussed.     

基于DSP的指纹识别系统硬件平台设计

目前传统指纹识别平台通用CPU实现识别算法 ,此类平台在功耗和可移动性方面已不能满足市场需要。随着标准CMOS工艺制造 ,并且集成SPI,USB ,并行数据接口的指纹传感芯片的出现 ,以及DSP芯片在图像处理领域的广泛应用 ,采用基于DSP指纹识别系统结构是今后指纹识别技术的发展方向。文章详细介绍了如何搭建基于DSP的指纹识别系统的硬件平台。针对嵌入式系统的特点 ,重点讨论了传感器的控制方法和指纹图像的读取 ,分析了DSP的性能优点。最后讨论了最佳指纹图像的获取方法。该系统灵活性强 ,除了为进一步实现指纹识别软件提供了功能强大的硬件基础外 ,对研究和开发速度快、性价比高、识别率高的嵌入式指纹识别平台有着很大的参考价值     

基于龙芯2E多处理器平台的虚拟机群系统

机群系统已成为高性能计算的主流体系结构,机群模拟环境是学习机群操作的重要工具。该文提出一种基于龙芯2E多处理器硬件平台的机群模拟方案——虚拟机群系统(VCS)。该系统在共享内存的多处理器上同时运行多个操作系统并使用内存操作模拟网络通信,实现机群环境的模拟。     

A novel architecture design for VLSI implementation of integer DCT in HEVC standard

This paper presents novel hardware of a unified architecture to compute the 4?×?4, 8?×?8, 16?×?16 and 32?×?32 efficient two dimensional (2-D) integer DCT using one block 1-D DCT for the HEVC standard with less complexity and material design. As HEVC large transforms suffer from the huge number of computations especially multiplications, this paper presents a proposition of a modified algorithm reducing the computational complexity. The goal is to ensure the maximum circuit reuse during the computation while keeping the same quality of encoded videos. The hardware architecture is described in VHDL language and synthesized on Altera FPGA. The hardware architecture throughput reaches a processing rate up to 52 million of pixels per second at 90 MHz frequency clock. An IP core is presented using the embedded video system on a programmable chip (SoPC) for implementation and validation of the proposed design. Finally, the proposed architecture has significant advantages in terms of hardware cost and improved performance compared to related work existing in the literature. This architecture can be used in ultra-high definition real-time TV coding (UHD) applications.

     

A polymorphous computing fabric

We propose a polymorphous computing fabric-based system (FBS) well suited to digital signal processing (DSP) and image processing applications. We have implemented our design on a system on a programmable chip (SoPC). The fabric's highly parameterized cellular architecture enables customized synthesis of fabric instances to achieve high performance for different classes of applications. The system's innovative global memory provides a host control processor with random access to all the variables and instructions on the fabric. The fabric supports several computing models including multiple instruction, multiple data (MIMD); single program, multiple data (SPMD); and systolic flow and permits dynamic reconfiguration of communication patterns. To illustrate the capabilities of our approach, we present two fabric instances with implementations of representative applications including a k-means clustering algorithm, a bank of finite impulse response (FIR) filters, an N-tap FIR filter (N is the number of taps of the filter), and a vector-by-matrix multiplication. Each fabric instance holds 52 cells on the Altera Excalibur ARM embedded processor system     

多处理器嵌入式系统的软/硬件协同模拟验证方法

介绍一种软硬件协同模拟验证方法，该疗法以指令集模拟器和事件驱动硬件模拟器为基本框架，透明地将多个不同类型的指令集模拟器和硬件模拟器连接起来，实现面向混合多处理器嵌入式系统的软硬件协同模拟验证。介绍了多处理器间通信机制的模拟实现及优化方法，重点讨论了以硬件模拟器为控制核心的协同模拟同步方法。     

免疫算法求解函数优化问题及其SoPC实现

SoPC是Altera公司近年来提出的一种灵活、高效的软硬件协同设计可编程片上系统。本文首先搭建硬件平台,在此平台上进行软件开发,运用改进免疫克隆选择算法解决函数优化问题。仿真结果表明,在SoPC上处理函数问题是可行的,并且算法具有优良的收敛速度及实时处理和抗退化能力。     

基于TMS320DM6467的监控视频去雾算法实现

有雾天气情况下拍摄的视频成像质量退化严重,极大地影响了安防监控、视觉导航等系统的整体性能.面向DSP嵌入式平台,提出一种实时监控视频去雾系统实现方案.首先在暗通道先验单幅图像去雾的基础上,提出了一种监控视频去雾算法;其次,基于TMS320DM6467处理器的硬件资源,对视频格式转换、除法运算、透射率计算、数据搬移等环节进行代码优化,最终在硬件平台上实现了整体系统.实测结果表明,对于D1格式的视频,在兼顾去雾质量的同时,达到了实时处理要求.     

Real-time hardware–software embedded vision system for ITS smart camera implemented in Zynq SoC

The article demonstrates the usefulness of heterogeneous System on Chip (SoC) devices in smart cameras used in intelligent transportation systems (ITS). In a compact, energy efficient system the following exemplary algorithms were implemented: vehicle queue length estimation, vehicle detection, vehicle counting and speed estimation (using multiple virtual detection lines), as well as vehicle type (local binary features and SVM classifier) and colour (k-means classifier and YCbCr colourspace analysis) recognition. The solution exploits the hardware–software architecture, i.e. the combination of reconfigurable resources and the efficient ARM processor. Most of the modules were implemented in hardware, using Verilog HDL, taking full advantage of the possible parallelization and pipeline, which allowed to obtain real-time image processing. The ARM processor is responsible for executing some parts of the algorithm, i.e. high-level image processing and analysis, as well as for communication with the external systems (e.g. traffic lights controllers). The demonstrated results indicate that modern SoC systems are a very interesting platform for advanced ITS systems and other advanced embedded image processing, analysis and recognition applications.     

Scalable communication architectures for massively parallel hardware multi-processors

Modern complex embedded applications in multiple application fields impose stringent and continuously increasing functional and parametric demands. To adequately serve these applications, massively parallel multi-processor systems on a single chip (MPSoCs) are required. This paper is devoted to the design of scalable communication architectures of massively parallel hardware multi-processors for highly-demanding applications. We demonstrated that in the massively parallel hardware multi-processors the communication network influence on both the throughput and circuit area dominates the processors influence, while the traditionally used flat communication architectures do not scale well with the increase of parallelism. Therefore, we propose to design highly optimized application-specific partitioned hierarchical organizations of the communication architectures through exploiting the regularity and hierarchy of the actual information flows of a given application. We developed related communication architecture synthesis strategies and incorporated them into our quality-driven model-based multi-processor design methodology and related automated architecture exploration framework. Using this framework we performed a large series of architecture synthesis experiments. Some of the results of the experiments are presented in this paper. They demonstrate many features of the synthesized communication architectures and show that our method and related framework are able to efficiently synthesize well scalable communication architectures even for the high-end massively parallel multi-processors that have to satisfy extremely stringent computation demands.     

A real-time versatile roadway path extraction and tracking on an FPGA platform

This paper presents an algorithm for roadway path extraction and tracking and its implementation in a Field Programmable Gate Array (FPGA) device. The implementation is particularly suitable for use as a core component of a Lane Departure Warning (LDW) system, which requires high-performance digital image processing as well as low-cost semiconductor devices, appropriate for the high volume production of the automotive market. The FPGA technology proved to be a proper platform to meet these two contrasting requirements. The proposed algorithm is specifically designed to be completely embedded in FPGA hardware to process wide VGA resolution video sequences at 30 frames per second. The main contributions of this work lie in (i) the proper selection, customization and integration of the main functions for road extraction and tracking to cope with the addressed application, and (ii) the subsequent FPGA hardware implementation as a modular architecture of specialized blocks. Experiments on real road scenario video sequences running on the FPGA device illustrate the good performance of the proposed system prototype and its ability to adapt to varying common roadway conditions, without the need for a per-installation calibration procedure.