Characterization of phosphorus implanted low pressure chemical vapor deposited polycrystalline silicon

Thin (3000–5000Å) low pressure chemically vapor deposited (LPCVD) films of polycrystalline silicon suitable for microelectronics applications have been deposited from silane at 600°C and at a pressure of 0.25 Torr. The films were phosphorus implanted at 150 KeV and electrically characterized with the annealing conditions and film thickness as parameters, over a resistivity range of four orders of magnitude (10³–10⁷Ω/□). Annealing during silox deposition was found to result in a lower film resistivity than annealing done in nitrogen atmosphere. Resistivity measurements as a function of temperature indicate that the electrical activation energy is a linear function of 1/N(N is the doping concentration), changing from 0.056 eV for a doping concentration of 8.9 × 10¹⁸ cm⁻³ to 0.310 eV for doping concentration of 3.3 × 10¹⁸ cm⁻³. The grain boundary trap density was found to have a logarithmically decreasing dependence on the polysilicon thickness, decreasing from 1.3 × 10¹³ cm⁻² for 2850Å polysilicon film to 8.3 × 10¹² cm⁻² for 4500Å polysilicon film.     

Schottky barrier height of a new ohmic contact NiSi2 to n-type 6H-SiC

We present a new ohmic contact material NiSi₂ to n-type 6H-SiC with a low specific contact resistance. NiSi₂ films are prepared by annealing the Ni and Si films separately deposited on (0 0 0 1)-oriented 6H-SiC substrates with carrier concentrations (n) ranging from 5.8×10¹⁶ to 2.5×10¹⁹ cm⁻³. The deposited films are annealed at 900 °C for 10 min in a flow of Ar gas containing 5 vol.% H₂ gas. The specific contact resistance of NiSi₂ contact exponentially decreases with increasing carrier concentrations of substrates. NiSi₂ contacts formed on the substrates with n=2.5×10¹⁹ cm⁻³ show a relatively low specific contact resistance with 3.6×10⁻⁶ Ω cm². Schottky barrier height of NiSi₂ to n-type 6H-SiC is estimated to be 0.40±0.02 eV using a theoretical relationship for the carrier concentration dependence of the specific contact resistance.     

Selenium doped high-index GaAs epilayers grown by molecular beam epitaxy

Using elementary Se we grew Se-doped GaAs films on GaAs (111), (411), (711) and (100) substrates by molecular beam epitaxy. The films grown on all the high-index substrates showed n-type conduction and the maximum carrier concentration reached 2.1 × 10¹⁹ cm⁻³ for the film grown on the (411)B substrate. The carrier concentration began to saturate at a Se concentration near 10¹⁹ cm⁻³ but continued to increase up to a Se concentration of 2 × 10²⁰ cm⁻³. Above 2 × 10²⁰ cm⁻³ Se concentration, slow reduction of the carrier concentration was observed. We obtained excellent surface morphology when n-type GaAs films were grown on (411)A and (711)B substrates even at a Se concentration of 7 × 10²⁰ cm⁻³.     

Theoretical calculation and experimental evidence of the real and apparent bandgap narrowing due to heavy doping in p-type Si and strained Si1−xGex layers

Based on an analytical approach developed by Jain and Roulston, the different contributions to the bandgap narrowing at T = 0 K due to heavy doping in highly p-type doped Si and strained Si_1-xGe_x-layers are calculated for x < 0.3. The valence band in Si and in strained Si_1-xGe_x layers is not parabolic, it is highly distorted. To take the non-parabolicity into account a dopant concentration-dependent density of states effective mass is defined. within the framework of this formalism we find that the bandgap narrowing (BGN) in Si is not appreciably affected due to the band distortion. The situation for strained Si_1-xGe_x layers is quite different, in that the BGN increases significantly at doping levels exceeding 10¹⁹ cm⁻³. In the earlier published work, BGN of the Si_1−xGe_x layers was either slightly smaller or about the same as in Si. Now at high doping levels, BGN becomes considerably higher than in Si. We will show that the effect of the strain on the Fermi energy is much larger than on the BGN, which will cause a large change in the effective valence band offset. Comparison will be made then between our theoretical calculations and experimental results obtained on two different device structures. The modified effective valence band offset that we have calculated is in very good agreement with the experimental value derived from the published work on long-wavelength optical detectors. The apparent bandgap narrowing in strained p-type Si_1-xGe_x-layers is also calculated and compared with the experimental results on Heterojunction Bipolar Transistors fabricated in our laboratory.     

Avalanche breakdown voltage of GaAs hyperabrupt junctions

The avalanche breakdown voltage of a GaAs hyperabrupt junction diode is calculated by using unequal ionization rates for electrons and holes, and shown graphically as a function of the parameters which characterize the impurity profile of the diode. The breakdown voltage decreases abruptly at the critical point of the characteristic length L_c which varies in accordance with the impurity concentration N₀ at X = 0. For example, the critical length L_c is 7.7 × 10⁻⁶ cm and 3.3 × 10⁻⁵ cm for N₀ = 1 × 10¹⁸ cm⁻³ and 1 × 10¹⁷ cm⁻³, respectively. The breakdown voltage of a diode with extremely short or long characteristic length can be estimated from the results for corresponding abrupt junctions. The experimental results agree well with the calculated ones.     

Estimation for the capture cross-sections of surface state on p-Si surface by photovoltaic method

A new method which can nondestructively measure the surface-state density (SSD) D_s and estimate the capture cross-sections (CCS) of surface state σ⁰_n and σ⁻_p on surface of p-type semiconductor crystals is proposed. This method is based on the photovoltage measurements at various temperatures. The photovoltage experiment was carried out with a (1 1 1) p-type Si single crystal (N_A=4.8×10¹⁴ cm ⁻³). Owing to that the surface barrier height φ_BP=0.6421 V and the surface-recombination velocity s_n=9.6×10³ cm s⁻¹ of this sample can be determined, the SSD D_s=1.2×10¹¹ cm⁻² eV⁻¹ can therefore be obtained, furthermore CCS σ⁰_n≈5×10⁻¹⁴ cm² and σ⁻_p≈2×10⁻¹⁰ cm² can also be estimated. These results are consistent with that of related reports obtained by other methods.     

GaN p–n junction diode formed by Si ion implantation into p-GaN

²⁸Si⁺ implantation into Mg-doped GaN, followed by thermal annealing in N₂ was performed to achieve n⁺-GaN layers. The carrier concentrations of the films changed from 3×10¹⁷ (p-type) to 5×10¹⁹ cm⁻³ (n-type) when the Si-implanted p-type GaN was properly annealed. Specific contact resistance (ρ_c) of Ti/Al/Pt/Au Ohmic contact to n-GaN, formed by ²⁸Si⁺ implantation into p-type GaN, was also evaluated by transmission line model. It was found that we could achieve a ρ_c value as low as 1.5×10⁻⁶ Ω cm² when the metal contact was alloyed in N₂ ambience at 600 °C. Si-implanted GaN p–n junction light-emitting diodes were also fabricated. Electroluminescence measurements showed that two emission peaks at around 385 and 420 nm were observed, which could be attributed to the near band-edge transition and donor-to-acceptor transition, respectively.     

Interface characteristics of Ge3N4-(n-type) GaAs MIS devices

Passivation of GaAs surfaces was achieved by the deposition of Ge₃N₄ dielectric films at low temperatures. Electrical characteristics of MIS devices were measured to determine the interface parameters. From C-V-f and G-V-f measurements, density of interface states has been obtained as (4–6)×10¹¹ cm⁻² eV⁻¹ at the semiconductor mid-gap. Some inversion charge buildup was seen in the C-V plot although the strong inversion regime is absent. Thermally stimulated current measurements indicate a trap density of 5×10¹⁸−10¹⁹ cm⁻³ in the dielectric film, with their energy level at 0.59 eV.     

The physics and fabrication of in situ back-gated (311)A hole gas heterojunctions

This paper reports the fabrication of an in situ back-gated hole gas on the (311)A surface of GaAs. The hole density can be varied from fully depleted to p_s = 2.1 × 10¹¹ cm⁻² with mobilities of up to μ = 1.1 × 10⁶ cm²V⁻¹ s⁻¹. It is seen that for carrier densities down to p_s = 4 × 10¹⁰ cm⁻² the mobility in the [ ] direction is greater than that in the [ ] direction. Using a combination of front- and back-gates we are able to keep the carrier density constant and deform the hole gas wavefunction such that the holes are pushed up against or moved further away from the heterointerface. Thus we are able to separately investigate the various scattering mechanisms that determine the mobility, and compare the experimental data with theoretical calculations based on the shape of the wavefunction.     

Intersubband lifetimes in Si/SiGe quantum wells

In the present work we report the first measurement of intersubband lifetimes in Si/Si_1−xGe_x quantum well samples. We have determined T₁ by a time resolved pump and probe experiment using the far infrared picosecond free electron laser source FELIX at Rijnhuizen, the Netherlands. In a sample with a well width of 50 Å and a sheet density of 2.1 × 10¹² cm⁻² we find a lifetime of 30 ps while 20 ps is observed for a density of 1.1 × 10¹² cm⁻² and a well width of 75 Å. We discuss acoustic phonon, as well as optical phonon intersubband scattering as possible limiting processes for the observed lifetimes in Si/SiGe and GaAs/AlGaAs quantum wells.     

Measurement of low densities of surface states at the Si---SiO2-interface

By a careful process Si---SiO₂-interfaces can be made with a low oxide charge Q_ox and with a low surface states density N_ss. For dry oxides on (100) N_ss-values as low as a few 10⁹ cm⁻² eV⁻¹ are found on samples with an oxide charge density of 3·0 × 10¹⁰ cm⁻². Only the Nicollian-Goetzberger conductance method is proved to give reasonable results on these structures. The quasi-static low frequency C-V-technique is in good agreement with the conductance technique for samples with N_ss-values higher than 1·0 × 10¹⁰ cm⁻² eV⁻¹. The spatial fluctuation of surface potential, mainly caused by oxide charge fluctuations, is an important parameter when studying the high or low frequency C-V-characteristics. Some irregularities in the experimental N_ss-φ_s-curves are explained.     

Process and device characterization of high voltage gallium arsenide P-i-N layers grown by an improved liquid phase epitaxy method

GaAs P-i-N layers with an i-region net doping of less than 10¹² cm⁻³ were grown on P⁺ and N⁺ substrates by a modified liquid phase epitaxy (LPE) method. Doping profiles and structural data obtained by varius characterization techniques are presented and discussed. A P⁺-P-i-N-N⁺ diode with a 25 μm-wide i-region exhibits a breakdown voltage of 1000 V, a t_rr of 50 ns, and reverse current densities (at V_R = 800 V) of − 3 × 10⁻⁶ A/cm² at 25°C and 10⁻² A/cm² at 260° C.     

Metal-germanium Schottky barriers

A systematic study has been made of the electrical characteristics of Schottky barriers fabricated by evaporating various metal films on n-type chemically cleaned germanium substrates. The diodes, with the exception of Al---Ge contacts, exhibit near-ideal electrical characteristics and age only slightly towards lower barrier height values. Al---Ge contacts exhibit very pronounced ageing towards higher barrier height values, due to formation of an extra aluminium oxide interfacial layer. Because of this, the barrier height values of aged Al---Ge contacts derived from I-V and C-V characteristics differ significantly. The dependence of the barrier height, (φ_b) on the metal work function, φ_m, for different metal-germanium contacts shows that surface states play an important role in the formation of the barrier. The density of germanium surface states is estimated to be D_s = 2 × 10¹³ eV⁻¹ cm⁻².     

Hole mobility enhancement and Si cap optimization in nanoscale strained Si1−xGex PMOSFETs

P-channel metal-oxide-semiconductor field-effect-transistors (PMOSFETs) with a Si_1−xGe_x/Si heterostructure channel were fabricated. Peak mobility enhancement of about 41% in Si_1−xGe_x channel PMOSFETs was observed compared to Si channel PMOSFETs. Drive current enhancement of about 17% was achieved for 70 nm channel length (L_G) Si_0.9Ge_0.1 PMOSFETs with SiO₂ gate dielectric. This shows the impact of increased hole mobility even for ultra-small geometry of MOSFETs and modest Ge mole fractions. Comparable short channel effects were achieved for the buried channel Si_1−xGe_x devices with L_G=70 nm, by Si cap optimization, compared to the Si channel devices. Drive current enhancement without significant short channel effects (SCE) and leakage current degradation was observed in this work.     

n-Channel AlSb/GaSb modulation-doped field-effect transistors

We report the first fabrication of a GaSb n-channel modulation-doped field-effect transistor (MODFET) grown by molecular beam epitaxy. The modulation-doped structure exhibits a room temperature Hall mobility of 3140 cm² V⁻¹ s⁻¹ and 77 K value of 16000 cm² V⁻¹ s⁻¹, with corresponding sheet carrier densities of 1.3 × 10¹² cm⁻² and 1.2 × 10¹² cm⁻². Devices with 1 μm gate length yield transconductances of 180 mS mm⁻¹ and output of 5 mS mm⁻¹ at 85 K. The device characteristics indicate that electron transport in the channel occurs primarily via the L-valley of GaSb above 85 K. The effective electron saturation velocity is estimated to be 0.9 × 10⁷ cm s⁻¹. Calculations show that a complementary circuit consisting of GaSb n- and p-channel MODFETs can provide at least two times improvement in performance over AlGaAs/GaAs complementary circuits.     

Optoelectronic properties of Zn0.52Se0.48/Si Schottky diodes

Zn_0.52Se_0.48/Si Schottky diodes are fabricated by depositing zinc selenide (Zn_0.52Se_0.48) thin films onto Si(1 0 0) substrates by vacuum evaporation technique. Rutherford backscattering spectrometry (RBS) analysis shows that the deposited films are nearly stoichiometric in nature. X-ray diffractogram of the films reveals the preferential orientation of the films along (1 1 1) direction. Structural parameters such as crystallite size (D), dislocation density (δ), strain (ε), and the lattice parameter are calculated as 29.13 nm, 1.187 × 10⁻¹⁵ lin/m², 1.354 × 10⁻³ lin⁻² m⁻⁴ and 5.676 × 10⁻¹⁰ m respectively. From the I–V measurements on the Zn_0.52Se_0.48/p-Si Schottky diodes, ideality and diode rectification factors are evaluated, as 1.749 (305 K) and 1.04 × 10⁴ (305 K) respectively. The built-in potential, effective carrier concentration (N_A) and barrier height were also evaluated from C–V measurement, which are found to be 1.02 V, 5.907 × 10¹⁵ cm⁻³ and 1.359 eV respectively.     

Low-frequency noise analysis of Si/SiGe channel pMOSFETs

Low-frequency noise characteristics of 0.1 μm Si_1−xGe_x channel pMOSFETs were studied by numerical simulations in the framework of the carrier number fluctuation model as well as the correlated fluctuation in the mobility model. Simulation results predict that Si_1−xGe_x channel pMOSFETs could offer improved low-frequency noise performance as compared to the conventional bulk Si devices. This improvement in Si_1−xGe_x channel pMOSFETs could be attributed to less effective oxide trap density for noise generation due to the increasing separation of quasi-Fermi level and valence band edge at Si–SiO₂ interface by Ge-induced band offset.     

Electrical, structural, and optical characterization of free-standing GaN template grown by hydride vapor phase epitaxy

Electrical, structural, and optical properties of a free-standing 200 μm thick n-type GaN template grown by hydride vapor phase epitaxy have been investigated. Hall mobilities of 1100 and 6800 cm²/V s have been obtained at room temperature and 50 K, respectively. Quantitative analysis of acceptor concentration, donor concentration and donor activation energy has been conducted through simultaneous fitting of the temperature dependent Hall mobility and carrier concentration data which led to a donor concentration of 2.10×10¹⁶ cm⁻³ and an acceptor concentration of 4.9×10¹⁵ cm⁻³. The resultant donor activation energy is 18 meV. The analysis indicates that the dominant scattering mechanism at low temperatures is by ionized impurities. The extended defect concentrations on Ga- and N-faces were about 5×10⁵ cm⁻² for the former and about 1×10⁷ cm⁻² for the latter, as revealed by a chemical etch. The full width at half maximum of the symmetric (0 0 0 2) X-ray diffraction peak was 69″ and 160″ for the Ga- and N-faces, respectively. That for the asymmetric (10–14) peak was 103″ and 140″ for Ga- and N-faces, respectively. The donor bound exciton linewidth as measured on the Ga- and N-face (after a chemical etch to remove the damage) is about 1 meV each at 10 K. Instead of the commonly observed yellow band, this sample displayed a green band, which is centered at about 2.45 eV.     

Nickel-based contact metallization for SiGe MOSFETs: progress and challenges

The Ni-based self-aligned silicide process has attracted a rapidly growing interest for contact metallization in Si technology, as the device dimensions are scaled down into the sub-100 nm regime. Incorporation of Ge in the electrodes of a MOSFET, i.e. gate and source/drain, in order to further enhance device performance, has made the study of Ni–Si_1−xGe_x interactions a scientifically and technologically important issue. Among the different germanosilicides of Ni, NiSi_1−uGe_u (i.e. mono-germanosilicide, with u possibly different from x in the Si_1−xGe_x) is the most desirable phase due to its low specific resistivity of 12–25 μΩcm. The focus of the present work is placed on issues concerning the phase and morphology stability of NiSi_1−uGe_u on single-crystal and polycrystalline Si_1−xGe_x substrates. The related experimental data from our recent work are analysed with reference to two classics on the formation of silicides by d’Heurle [J. Mater. Res. 3 (1988) 167] and by d’Heurle and Gas [J. Mater. Res. 1 (1986) 205]. Influences of C and Pt on the stability of NiSi_1−uGe_u are also covered. The electrical properties of the NiSi_1−uGe_u–Si_1−xGe_x contact are discussed referring to our latest experimental results.     

Thin oxide grown on heavily channel-implanted substrate by using a low temperature wafer loading and N2 pre-annealing process

In this paper, we present high integrity thin oxides grown on the channel implanted substrate (3 × 10¹⁷ cm⁻³) and heavily doped substrate (1 × 10²⁰ cm⁻³) by using a low-temperature wafer loading and N₂ pre-annealing process. The presented thin oxide grown on the channel implanted substrate exhibits a very low interface state density (1 × 10¹⁰ cm⁻² eV⁻¹) and a very high intrinsic dielectric breakdown field (15 MV/cm). It also shows a lower charge trapping rate and interface state generation rate than the conventional thermal oxide. For the thin oxide grown on the heavily-doped substrate by using the proposed recipe, the implantation-induced damage close to the silicon surface can be almost annealed out. The presented heavily-doped oxide shows much better dielectric characteristics, such as the dielectric breakdown field and the charge-to-breakdown, as compared to the conventional heavily-doped oxide.