高k栅介质薄膜材料研究进展

金属-氧化物-半导体场效应晶体管(MOSFET),要求其器件特征尺寸越来越小,当光刻线宽小于100nm尺度范围后,栅介质氧化物层厚度开始逐渐接近(1～1.5)nm,这时电子的直接隧穿而导致栅极漏电流随栅氧化层厚度的下降而指数上升,此外,当栅氧化层薄到一定程度后,其可靠性问题,尤其是与时间相关的击穿及栅电极中的杂质向衬底的扩散等问题,将严重影响器件的稳定性和可靠性.因此需要寻找一种具有高介电常数的新型栅介质材料来替代SiO2,在对沟道具有相同控制能力的条件下(栅极电容相等),利用具有高介电常数的介质材料(一般称为高k材料)作为栅介质层可以增加介质层的物理厚度,这将有效减少穿过栅介质层的直接隧穿电流,并提高栅介质的可靠性.本文介绍了高k栅介质薄膜材料的制备方法,综述了高k栅介质薄膜材料研究的应用要求及其研究发展动态.     

高介电常数栅极电介质材料的研究进展

随着半导体技术的飞速发展,作为硅基集成电路核心器件的MOSFET的特征尺寸正以摩尔定律的速度缩小.然而,当传统栅介质层SiO2的厚度减小到原子尺寸时,由于量子隧穿效应的影响,SiO2将失去介电性能,致使器件无法正常工作.因此,必须寻找新的高介电常数材料来替代它.目前,高介电常数材料是微电子行业最热门的研究课题之一.主要介绍了栅介质层厚度减小所带来的问题(即研究高介电常数材料的必要性)、新型栅电介质材料的性能要求,并简要介绍和评述了近期主要高介电常数栅介质材料的研究状况及其应用前景.     

高k栅介质的研究进展

随着集成电路的飞速发展,半导体器件特征尺寸按摩尔定律不断缩小.SiO2栅介质将无法满足Metal-oxide-semniconductor field-effect transistor(MOSFET)器件高集成度的需求.因此,应用于新一代MOSFET的高介电常数(k)栅介质材料成为微电子材料研究热点.介绍了不断变薄的SiO2栅介质层带来的问题、对MOSFET栅介质材料的要求、制备高k薄膜的主要方法,总结了高k材料的研究现状及有待解决的问题.     

SrHfON高κ栅介质薄膜的漏电特性研究

采用射频反应磁控溅射法在p-Si(100)衬底上成功制备出SrHfON高k栅介质薄膜,并研究了Au/SrHfON/Si MOS电容的漏电流机制及应力感应漏电流(SILC)效应.结果表明,MOS电容的漏电流密度随N2流量的增加而减小.在正栅压下,漏电流主要由Schottky发射机制引起;在负栅压下,漏电流机制在低、中、高栅电场区时分别为Schottky发射、F-P发射和F-N隧穿机制.同时,Au/SrHfON/Si MOS电容表现出明显的SILC效应,经恒压应力后薄膜在正栅压下的漏电流由Schouky发射和F-P发射机制共同作用,且后者占主导地位.     

多晶硅/氧化硅/多晶硅非平面结构中Fowler-Nordheim隧穿及氧化层退化研究(英文)

Fowler-Nordheim隧穿被广泛应用于EEPROM和闪存中的擦除操作。多晶硅到多晶硅的F-N隧穿具有较高的隧穿效率。本论文基于分栅闪存存储器的结构,对于多晶硅/隧穿氧化层/多晶硅非平面结构的F-N隧穿及其引起的氧化层退化进行了研究。相比于平面结构,非平面结构显示出更高的F-N隧穿效率,且隧穿效率还可通过降低氧化层厚度或者增加预热氧化处理的方法进一步提高。较低的F-N隧穿电流密度显示出较慢的隧穿氧化层退化速率。降低氧化层厚度或者增加热氧化处理也可减缓隧穿氧化层的退化。另外,论文还讨论了研究结果对于改善分栅闪存擦除特性以及耐久性的意义。     

Hf基高K栅介质材料研究进展

随着微电子技术的不断发展,MOSFET的特征尺寸已缩小至100nm以下,SiO2作为栅介质材料已不能满足技术发展的需求,因此必须寻求一种新型高K的介质材料来取代SiO2.当今普遍认为Hf基栅介质材料是最有希望取代SiO2而成为下一代MOSFET的栅介质材料.综述了高K栅介质材料的意义、Hf基高K栅介质材料的最新研究进展和Hf基高K栅介质材料在克服自身缺陷时使用的一些技术;介绍了一款由Hf基高K介质材料作为栅绝缘层制作的MOSFET.     

高k值HfO2栅介质材料电学特性的研究进展

随着Si-MOS集成电路的迅速发展,高k值栅介质材料将成为下一代MOS器件绝缘栅最有希望的候选材料.介绍了近年来HfO2栅介质材料在制备方法和电学特性方面的研究进展,提出了改善其电学特性的主要途径,其中包括非金属元素掺杂、构建组分渐变界面、设计准二元合金系统、制备堆垛积层结构、抑制界面层生长和选择适宜的电极材料等.     

固-固结构声子晶体中SH波的色散关系及其全反射隧穿

利用边界条件推导出SH波在多层介质系统中的转移矩阵,得出了SH波在一维固-固结构声子晶体中的色散函数。利用色散函数研究了SH波在一维固-固结构声子晶体中的全反射隧穿效应,得出SH波的全反射隧穿导带的特征:全反射隧穿导带的频率中心随入射角的增加而向高频方向移动,全反射隧穿导带的频率宽度随入射角的增加而减小;全反射隧穿导带的频率中心和频率宽度都随周期厚度的增加而减小。     

福建物构所金属-有机框架薄膜的组装及性能研究取得新进展

正开发和研究具有高介电常数、低漏流和高击穿电压的功能器件对栅极介电薄膜材料和高电子传输二极管等电子器件材料具有重要的意义。当前,大部分栅极介电薄膜材料都是基于传统的硅基电子元件材料。然而,传统的硅基材料在实际应用中常常会面临高介电损耗以及由于厚度引起的隧穿效应等问题。为此,开发高介电常数薄膜材料有利于增加栅极     

铁电隧道结的研究进展

铁电隧道结是一种具有量子隧穿效应和电致电阻效应的新型隧道结.从铁电隧道结的基本理论出发,针对势垒层和电极材料选取的角度详细介绍了铁电隧道结的研究成果,揭示了材料选取对隧道结中铁电性保持的重要影响,含铅的钙钛矿型氧化物作为铁电势垒层是目前研究的重点.铁电隧道结的研究正向着无铅材料及多铁隧道结方向发展.最后讨论了铁电隧道作为存储器单元应用的可能性与优点.     

Tunneling currents through ultra thin HfO2/Al2O3/HfO2 triple layer gate dielectrics for advanced MIS devices

The dramatic scaling down of silicon integrated circuits has led to an intensive study of high dielectric constant materials as an alternative to the conventional insulators currently employed in microelectronics, i.e., silicon dioxide, silicon nitride, or oxynitride, which seem to have reached their physical limit in terms of reduction of thickness due to large leakage gate current. Introducing a physically thicker high-K material can reduce the leakage current to the acceptable limit. There are many potential candidates for high-K gate dielectrics with the K-valves ranging from 9 to 80. These are Al₂O₃, Y₂O₃, La₂O₃, Ta₂O₅, TiO₂, ZrO₂ and HfO₂. It is important to study the various leakage mechanisms in these films with the aim of improving their leakage current characteristics for use in advanced microelectronics devices. A procedure for calculating the tunneling current for stacked dielectrics is developed and subsequently applied to ultra thin films with equivalent oxide thickness (EOT) of 3.0 nm. Tunneling currents have been calculated as a function of gate voltage for different structures. Direct and Fowler-Nordheim tunneling currents through triple layer dielectrics are investigated for substrate injection. Using exact tunneling transmission calculations, current density–gate voltage (J _g?V _g) characteristics for ultra thin single layer gate dielectrics with different thicknesses have been shown to agree well with recently reported experiments. Extensions of this approach demonstrate that tunneling currents in HfO₂/Al₂O₃/HfO₂ structure with equivalent oxide thickness of 3.0 nm can be significantly lower than that through single layer oxides of the same thickness.     

High-κ dielectrics and advanced channel concepts for Si MOSFET

With scaling of the gate length downward to increase speed and density, the gate dielectric thickness must also be reduced. However, this practice which has been in effect for many decades has reached a fundamental limitation because gate dielectric thicknesses in the range of tunneling have been reached with the SiO₂ dielectric layer for MOSFETs. Consequently, the gate dielectrics with higher dielectric constants, dubbed the “high-κ”, which allow scaling with much larger thicknesses have become active research and development topics. In this review technological issues associated with the likely high-κ materials which are under consideration as well as challenges, and solution to them, they bring about in the fabrication of Si MOSFET are discussed. Moreover, in order to squeeze more speed out of CMOS, channels for both n- and p-type MOSFET enhanced with appropriate strain and the concepts behind them are discussed succinctly. Finally, the longer term approach of replacing Si with other channel materials such as GaAs (InGaAs) for n-channel and Ge for p-channel along with technological developments of their preparation on Si and likely gate oxide developments are treated in some detail.     

WSe2 Homojunction Devices: Electrostatically Configurable as Diodes,MOSFETs, and Tunnel FETs for Reconfigurable Computing

In this paper, electrostatically configurable 2D tungsten diselenide (WSe₂) electronic devices are demonstrated. Utilizing a novel triple‐gate design, a WSe₂ device is able to operate as a tunneling field‐effect transistor (TFET), a metal–oxide–semiconductor field‐effect transistor (MOSFET) as well as a diode, by electrostatically tuning the channel doping to the desired profile. The implementation of scaled gate dielectric and gate electrode spacing enables higher band‐to‐band tunneling transmission with the best observed subthreshold swing (SS) among all reported homojunction TFETs on 2D materials. Self‐consistent full‐band atomistic quantum transport simulations quantitatively agree with electrical measurements of both the MOSFET and TFET and suggest that scaling gate oxide below 3 nm is necessary to achieve sub‐60 mV dec^?1 SS, while further improvement can be obtained by optimizing the spacers. Diode operation is also demonstrated with the best ideality factor of 1.5, owing to the enhanced electrostatic control compared to previous reports. This research sheds light on the potential of utilizing electrostatic doping scheme for low‐power electronics and opens a path toward novel designs of field programmable mixed analog/digital circuitry for reconfigurable computing.     

Development of hafnium based high-k materials—A review

The move to implement metal oxide based gate dielectrics in a metal-oxide-semiconductor field effect transistor is considered one of the most dramatic advances in materials science since the invention of silicon based transistors. Metal oxides are superior to SiO₂ in terms of their higher dielectric constants that enable the required continuous down-scaling of the electrical thickness of the dielectric layer while providing a physically thicker layer to suppress the quantum mechanical tunneling through the dielectric layer. Over the last decade, hafnium based materials have emerged as the designated dielectrics for future generation of nano-electronics with a gate length less than 45 nm, though there exists no consensus on the exact composition of these materials, as evolving device architectures dictate different considerations when optimizing a gate dielectric material. In addition, the implementation of a non-silicon based gate dielectric means a paradigm shift from diffusion based thermal processes to atomic layer deposition processes. In this report, we review how HfO₂ emerges from all likely candidates to become the new gold standard in the microelectronics industry, its different phases, reported electrical properties, and materials processing techniques. Then we use specific examples to discuss the evolution in designing hafnium based materials, from binary to complex oxides and to non-oxide forms as gate dielectric, metal gates and diffusion barriers. To address the impact of these hafnium based materials, their interfaces with silicon as well as a variety of semiconductors are discussed. Finally, the integration issues are highlighted, including carrier scattering, interface state passivation, phonon engineering, and nano-scale patterning, which are essential to realize future generations of devices using hafnium-based high-k materials.     

Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

The decreasing feature sizes in complementary metal-oxide semiconductor (CMOS) transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k) because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability.In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology.Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties.It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling.In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices.Therefore, detailed atomicscale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks,are highly required.In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed.Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy (HRTEM) and the related techniques based on scanning transmission electron microscopy (STEM), including high-angle annular darkfield (HAADF) imaging (also known as Z-contrast imaging), electron energy-loss spectroscopy (EELS), and energy dispersive X-ray spectroscopy (EDS), due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices.In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics.In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed.The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4.Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.     

Analysis of Scaling Strategies for Sub-30 nm Double-Gate SOI N-MOSFETs

State-of-the-art device simulation is applied to the analysis of possible scaling strategies for the future CMOS technology, adopting the ultrathin silicon body (UTB) double-gate (DG) MOSFET and considering the main figures of merit (FOM) for the high-performance N-MOS transistor. The results of our analysis confirm the potentials of UTB-DG MOSFETs. In particular, the possibility to control the short-channel effects by thinning the silicon layer is fully exploited allowing to adopt almost undoped silicon channel, leading to reduced transversal field. As a consequence, the impact of surface roughness at the Si-oxide interface and the gate tunneling leakage current are substantially reduced compared to the case of highly doped bulk MOSFETs. According to our results, thanks to the suppression of gate leakage current, scaling of the UTB-DG MOSFET down to the 32 nm technology node appears possible adopting -based gate dielectrics. In spite of the improved mobility at given inversion charge density, the simulated on-currents are substantially lower than those required by the 2005 ITRS for the 45 and 32 nm nodes . Nonetheless, thanks to relaxed scaling of the oxide thickness, hence to reduced gate capacitance, the requirements in terms of intrinsic delay and power-delay product can be satisfied. The issue of variability is analyzed by evaluating the dependence of the key FOM on the variation of critical dimensions such as the thickness of the gate oxide and of the silicon layer.     

Conventional Technological Boosters for Injection Velocity in Ultrathin-Body MOSFETs

To meet ITRS requirements, highly scaled MOSFETs will have to operate close to the quasi-ballistic regime and to exhibit enhanced injection velocity. Good performances may be achieved thanks to high transport materials such as germanium or III-V semiconductors. However their integration is still very challenging. Following a different approach, this paper proposes to examine how to improve the injection in conventional (100) silicon ultrathin-body (UTB) MOSFETs. A systematic investigation of the impact of the different usual technological parameters highlights that SG and DG exhibit comparable performances and that no improvement in the injection velocity is expected with the silicon thickness thinning down to 4 nm. Moreover the degradation of the injection velocity with the integration of high- dielectrics is shown. Finally, a significant improvement of the injection velocity due to a higher confinement in asymmetrical double gate MOSFET has been found. Similarly, it is shown that, single gate UTB MOSFETs with thin buried oxide (BOX) exhibit an enhanced injection velocity. In conclusion, only the reduction of the BOX thickness and the integration of strained channel have been found to be realistic and significant boosters of the injection velocity in silicon (100) MOSFETs. Prediction of the evolution of the injection velocity along the roadmap, using a pragmatic strategy of scaling, confirms that these two parameters will play a significant role in improving highly scaled (100) silicon devices performances.     

原子层淀积制备金属氧化物薄膜研究进展

原子层淀积(ALD)技术作为一种先进的薄膜制备方法近年来越来越得到重视,它能精确地控制薄膜的厚度和组分,实现原子层级的生长,生长的薄膜具有很好的均匀性和保形性,因而在微电子和光电子等领域有广泛的应用前景。本文综述了ALD技术的基本原理,及其在金属氧化物薄膜制备上的研究进展。