Deficit round-robin scheduling for input-queued switches

We address the problem of fair scheduling of packets in Internet routers with input-queued switches. The goal is to ensure that packets of different flows leave a router in proportion to their reservations under heavy traffic. First, we examine the problem when fair queuing is applied only at output link of a router, and verify that this approach is ineffective. Second, we propose a flow-based iterative deficit-round-robin (iDRR) fair scheduling algorithm for the crossbar switch that supports fair bandwidth distribution among flows, and achieves asymptotically 100% throughput under uniform traffic. Since the flow-based algorithm is hard to implement in hardware, we finally propose a port-based version of iDRR (called iPDRR) and describe its hardware implementation.     

支持优先级与公平策略的队列规程

首先介绍了队列调度算法在流量控制中的关键地位,然后讨论了现有队列调度算法,如基于优先级的调度算法、轮询调度算法与公平队列调度算法,最后提出了一种新的队列规程,该队列规程融合了优先级调度算法与DRR调度算法。在网络正常情况下,不同业务流公平地共享网络带宽,在网络出现拥塞的情况下,高优先级业务流能够抢占带宽,保证其较低的丢包率,并能够实现两种调度算法的快速切换。     

Efficient fair queuing using deficit round-robin

Fair queuing is a technique that allows each flow passing through a network device to have a fair share of network resources. Previous schemes for fair queuing that achieved nearly perfect fairness were expensive to implement; specifically, the work required to process a packet in these schemes was O(log(n)), where n is the number of active flows. This is expensive at high speeds. On the other hand, cheaper approximations of fair queuing reported in the literature exhibit unfair behavior. In this paper, we describe a new approximation of fair queuing, that we call deficit round-robin. Our scheme achieves nearly perfect fairness in terms of throughput, requires only O(1) work to process a packet, and is simple enough to implement in hardware. Deficit round-robin is also applicable to other scheduling problems where servicing cannot be broken up into smaller units (such as load balancing) and to distributed queues     

Analysis of Distributed DDQ for QoS Router

In a packet switching network, congestion is unavoidable and affects the quality of real‐time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well‐known solutions for quality‐of‐service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.     

Virtual spacing for flexible traffic control

Weighted fair queuing emerges as an elegant and effective solution to the problem of integrating real time services with strict delay constraints and high-speed data services for which significant delays cannot always be avoided. Virtual spacing is a weighted fair queuing scheduling algorithm intended to be applied in the context of the ATM based BISDN. After discussing how virtual spacing allows flexible traffic control for a variety of service types, we discuss the issue of its implementation in switching nodes. The aim of the paper is to highlight the advantages of weighted fair queuing in enabling a truly integrated services network and to propose a technologically feasible implementation.     

一类基于调度表的公平轮循调度算法

本文研究了一类利用时标在调度表中安排信元发送时隙的公平轮循(Fair Round Robin,FRR)调度算法.对其中三种算法的性能进行了分析比较.FRR能够保证连接的带宽和时延,同时实现复杂性低于一些分组公平排队算法,例如WF²Q+.     

A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm

The use of online arithmetic was often proposed for hardware implementations of complex digital-signal processing (DSP) algorithms. However, several important issues in the design process of such algorithms using online arithmetic are rarely discussed in the literature. This paper presents these issues and provides a methodology to analyze the behavior of networks of online arithmetic modules performing serial computation over fixed-point numbers. The methodology is presented, applied in several examples, and finally used to design an efficient field programmable gate arrays implementation of the Levinson-Durbin algorithm in an application of the Yule-Walker power spectrum estimation. The methodology can be applied to other algorithms as well and it simplifies the task of designing and verifying a network of online modules. The experimental results show the advantages of online arithmetic in the design of complex DSP algorithms.     

Ordonnancement de paquets équitable par les disciplinesgps etdgps

Providing efficient and flexible quality of service guarantees within interogated services packet networks requires the deployment of advanced scheduling disciplines. This paper concentrates on the class of so-called fair queuing algorithms, firstly reviewing the general principle and its known approximations, then focusing on the service of adaptive applications, shedding light on the need to introduce a new scheduling paradigm, named dgps for decoupled generalized processor sharing; for the latter scheme an approximation technique is introduced and evaluated.     

A New Starting Potential Fair Queuing Algorithm with O(1) Virtual Time Computation Complexity

In this paper, we propose an efficient and simple fair queuing algorithm, called new starting potential fair queuing (NSPFQ), which has O(1) complexity for virtual time computation and also has good delay and fairness properties. NSPFQ introduces a simpler virtual time recalibration method as it follows a rate‐proportional property. The NSPFQ algorithm recalibrates the system virtual time to the minimum virtual start time among all possible virtual start times for head‐of‐line packets in backlogged sessions. Through analysis and simulation, we show that the proposed algorithm has good delay and fairness properties. We also propose a hardware implementation framework for the scheduling algorithm.     

分组交换网络调度算法概述

为了合理利用网络资源,提高网络吞吐率,降低通信时延,需要采取有效的调度算法实现输入端和输出端的匹配.基于VOQ的输入排队交换结构是当前分组交换网络最常用的结构.本文介绍了几种基于VOQ的调度算法:用于单级crossbar的PIM、iRRM和iSLIP算法,以及适用于三级Clos网络的RD和CDDR算法.对每种算法,介绍其基本原理和性能,以及与其他算法的区别.     

Virtual time reference system: a unifying scheduling framework forscalable support of guaranteed services

We propose and develop a novel virtual time reference system as a unifying scheduling framework to provide scalable support for guaranteed services. This virtual time reference system is designed as a conceptual framework upon which guaranteed services can be implemented in a scalable manner using the DiffServ paradigm. The key construct in the proposed virtual time reference system is the notion of packet virtual time stamps, whose computation is core stateless, i.e., no per-flow states are required for its computation. We lay the theoretical foundation for the definition and construction of packet virtual time stamps. We describe how per-hop behavior of a core router (or rather its scheduling mechanism) can be characterized via packet virtual time stamps, and based on this characterization establish end-to-end per-flow delay bounds. Consequently, we demonstrate that, in terms of its ability to support guaranteed services, the proposed virtual time reference system has the same expressive power and generality as the IntServ model. Furthermore, we show that the notion of packet virtual time stamps leads to the design of new core stateless scheduling algorithms, especially work-conserving ones. In addition, our framework does not exclude the use of existing scheduling algorithms such as stateful fair queuing algorithms to support guaranteed services     

RPA: a simple, efficient, and flexible policy for input bufferedATM switches

Reservation with Preemption and Acknowledgment (RPA) is a simple, efficient, and flexible queuing discipline and scheduling algorithm for input buffered asynchronous transfer-mode (ATM) switches. This letter describes the RPA algorithms, and presents simulation results to demonstrate the effectiveness of the proposed approach     

On the provision of quality-of-service guarantees for input queued switches

While the Internet has quietly served as a research and education vehicle for more than two decades, the last few years have witnessed its tremendous growth and its great potential for providing a wide variety of services. As a result, input-queued switching architectures, because of their distinguished advantage in building scalable switches, are currently receiving a lot of attention from both academia and industry as an attractive alternative for developing future-generation ATM/IP switches/routers. However, the problem of designing scheduling algorithms with QoS guarantees for input-queued switches has always been known to be a very challenging problem. We give an overview of the efforts in designing scheduling algorithms capable of providing QoS guarantees for input-queued switches. These algorithms are classified under three categories: those based on slot time assignment, those based on maximal matching, and those based on stable matching. We also present some open problems on this topic as future research directions in this area.     

Core‐stateless fair rate estimation fair queuing

Core‐stateless mechanisms, such as core‐stateless fair queuing (CSFQ), reduce the complexity of fair queuing, which usually need to maintain states, manage buffers, and perform flow scheduling on a per‐flow basis. However, they require executing label rewriting and dropping decision on a per‐packet basis, thus preventing them from being widely deployed. In this paper, we propose a novel architecture based on CSFQ without per‐packet labelling. Similarly, we distinguish between edge routers and core routers. Edge routers maintain the per‐flow state by employing a fair queuing mechanism to allocate each flow a fair bandwidth share locally and a token bucket mechanism to regulate those flows with feedback packets sent from egress edge routers. Core routers do not maintain per‐flow state; they use FIFO packet scheduling extended by a fare rate alarm mechanism by estimating the arrival rate and the number of flows using a matching–mismatching algorithm. The novel scheme is called core‐stateless fair rate estimation fair queuing (CSFREFQ). CSFREFQ is proven to be capable of achieving max–min fairness. Furthermore, we present and discuss simulations and experiments on the performance under different traffic scenarios. Copyright © 2005 John Wiley & Sons, Ltd.     

Cost-based scheduling and dropping algorithms to support integratedservices

Applications with diverse performance objectives must be supported on a single packet-switched network. The efficiency of such networks can be greatly improved through the use of sophisticated scheduling and dropping algorithms within the queues that form at the network access points and in switches throughout the network. In the present approach, arbitrary performance objectives are expressed in the form of cost functions, which map the queueing delay experienced by each packet to a cost incurred. The heuristic algorithms, cost-based scheduling (CBS) and cost-based dropping (CBD), then attempt to optimize network performance as perceived by the applications by minimizing the total cost incurred by all packets. Appropriate cost functions are presented for common applications. Scheduling and dropping algorithms are defined from these cost functions. It is demonstrated that network performance is better when these algorithms are used as opposed to the common alternatives. Also, contrary to conventional wisdom, some evidence is presented indicating that sophisticated scheduling may be preferable to sophisticated dropping as a means of adjusting loss rates     

Keeping the packet sequence in optical packet-switched networks

This paper deals with optical packet switches with limited buffer capabilities, subject to asynchronous, variable-length packets and connection-oriented operation. The focus is put on buffer scheduling policies and queuing performance evaluation. In particular a combined use of the wavelength and time domain is exploited in order to obtain contention resolution algorithms that guarantee the sequence preservation of packets belonging to the same connection. Four simple algorithms for strict and loose packet sequence preservation are proposed. Their performance is studied and compared with previously proposed algorithms. Simulation results suggest that by accepting some additional processing effort it is possible to guarantee very low packet loss probabilities while avoiding the out-of-sequence delivery.     

Rate-proportional servers: a design methodology for fair queueingalgorithms

Generalized processor sharing (GPS) has been considered as an ideal scheduling discipline based on its end-to-end delay bounds and fairness properties. Until recently, emulation of GPS in a packet server has been regarded as the ideal means of designing a packet-level scheduling algorithm to obtain low delay bounds and bounded unfairness. Strict emulation of GPS, as required in the weighted fair queueing (WFQ) scheduler, however, incurs a time-complexity of O(N) where N is the number of sessions sharing the link. Efforts in the past to simplify the implementation of WFQ, such as self-clocked fair queueing (SCFQ), have resulted in degrading its isolation properties, thus affecting the delay bound. We present a methodology for the design of scheduling algorithms that provide the same end-to-end delay bound as that of WFQ and bounded unfairness without the complexity of GPS emulation. The resulting class of algorithms, called rate-proportional servers (RPSs), are based on isolating scheduler properties that give rise to ideal delay and fairness behavior. Network designers can use this methodology to construct efficient fair-queueing algorithms, balancing their fairness with implementation complexity     

The iSLIP scheduling algorithm for input-queued switches

An increasing number of high performance internetworking protocol routers, LAN and asynchronous transfer mode (ATM) switches use a switched backplane based on a crossbar switch. Most often, these systems use input queues to hold packets waiting to traverse the switching fabric. It is well known that if simple first in first out (FIFO) input queues are used to hold packets then, even under benign conditions, head-of-line (HOL) blocking limits the achievable bandwidth to approximately 58.6% of the maximum. HOL blocking can be overcome by the use of virtual output queueing, which is described in this paper. A scheduling algorithm is used to configure the crossbar switch, deciding the order in which packets will be served. Previous results have shown that with a suitable scheduling algorithm, 100% throughput can be achieved. In this paper, we present a scheduling algorithm called iSLIP. An iterative, round-robin algorithm, iSLIP can achieve 100% throughput for uniform traffic, yet is simple to implement in hardware. Iterative and noniterative versions of the algorithms are presented, along with modified versions for prioritized traffic. Simulation results are presented to indicate the performance of iSLIP under benign and bursty traffic conditions. Prototype and commercial implementations of iSLIP exist in systems with aggregate bandwidths ranging from 50 to 500 Gb/s. When the traffic is nonuniform, iSLIP quickly adapts to a fair scheduling policy that is guaranteed never to starve an input queue. Finally, we describe the implementation complexity of iSLIP. Based on a two-dimensional (2-D) array of priority encoders, single-chip schedulers have been built supporting up to 32 ports, and making approximately 100 million scheduling decisions per second     

Improved proportional fair dynamic subcarrier allocation with frugality constraint for SC-FDMA system

With the objective of taking full use of channel resource, we proposed two utility based dynamic subcarrier allocation (DSA) algorithms for the single carrier frequency division multiple access (SC-FDMA) system, which are the proportional fair frugality constrained (PF-FC) algorithm and the weighted proportional fair frugality constrained (WPF-FC) algorithm. The two proposed algorithms are designed under the frugality constraint (FC) control consideration so as to avoid service rate waste and improve the spectrum efficiency. Moreover, the queuing buffer model in this paper is established on a finite size structure rather than the traditional infinite queuing manner, which is more consistent with the practical transmission condition. Simulation results indicate that the two proposed algorithms can both achieve significantly better system rate-sum capacity and quality of service (QoS) performance than their primary algorithms, and are more applicable for the heterogeneous traffic.