MQ编码算法优化及高速VLSI结构设计与实现

传统的JPEG2000MQ编码器串行编码效率低下,同时现有的多上下文并行编码的MQ编码器占用资源过大.本文对MQ编码算法中的运算流程,索引值和概率估计值的求解函数,条件交换和重归一化算法等四个方面进行了优化,减弱了上下文之间的依赖性,简化了条件交换和重归一化算法的复杂度.依据该算法,本文提出了一种高速的MQ编码器VLSI结构,实验结果表明,本文提出的MQ编码器VLSI结构能够工作在532.91MHz,吞吐率为532.91 Msymbols/sec,相比Dyer提出的Brute force with modified结构,工作频率提高1倍,吞吐量提高近27%,且面积仅为其四分之一.     

JPEG2000标准中MQ编码器的VLSI结构设计

MQ编码器是JPEG 2000标准中重要的无损压缩算法,可获得很高的压缩效率.但因其算法复杂度高,执行速度慢,使其应用受到很大限制.为了获得高速处理能力,设计一种高速MQ编码器的VLSI结构,采用三级流水线结构,对算法进行优化,并改进概率估计表内容.设计使用Verilog进行编程,最后通过Modelsim 6.1进行仿真.实验结果表明,该设计极大地提高了编码速度.这里的研究对于JPEG 2000在实际中的应用有着重要的意义.     

基于率失真优化的递进UTCQ编码

本文提出了一种基于UTCQ量化器的递进静态图像小波编码算法。一致网格编码量化(UTCQ)用于小波系数的量化并得到了非常好的量化效果。UTCQ超集索引值构成系数位平面,率失真优化按照率失真斜率递减的顺序从系数位平面选择编码系数位。最先编码的位具有最大的率失真斜率,每编码一位都会使失真减少最大。率失真斜率的计算仅仅是利用MQ自适应算术编码器的概率状态估计表而进行的查表过程。MQ算术编码器进一步压缩率失真优化选择的系数位。率失真门限方法的编码速度比搜索最大的率失真斜率更快。该算法有较快的编码速度以及好的压缩效果。     

一种适用于JPEG2000的高速MQ编码器的VLSI实现

MQ编码器对于无损的数据压缩是一种非常有效的方法 ,它已被 JPEG2 0 0 0标准所采用。但该编码算法复杂度高 ,执行速度慢。文中提出了一种基于动态流水的高性能 MQ编码器的 VLSI结构。为了获得高速处理能力 ,首先分析了 JPEG2 0 0 0标准中 MQ编码算法的软件流程 ,并对其进行了相应的修改以适应硬件实现 ,然后采用了“动态流水”技术 ,可以根据变化的运算量来实时地安排流水操作。本 MQ编码器结构经 Xilinx FPGA实现 ,处理速度可达约 0 .6 2 5bit/ cycle( 32 .83Mbit/ sec)     

800Mbps准循环LDPC码编码器的FPGA实现

本文提出了一种准循环低密度奇偶校验码的低复杂度高速编码器结构.通过利用循环矩阵的结构特性,增加少量的硬件开销就可以提高编码器的并行度,得到一种基于并行SRAA结构的编码算法,提高了编码器的吞吐量.这种编码方法的主要优点是复杂度较低,且编码延时小.在Xilinx Virtex 4 FPGA上实现了(8176,7154)有限几何LDPC码的编码器,吞吐量达到800Mbps.     

JPEG2000中高性能Tier-1编码器的VLSI结构设计与实现

为满足JPEG2000编码器的硬件实现需求,针对其中最为复杂和耗时的Tier-1编码器,提出了一种高效的硬件实现结构.该结构采用通道并行的位平面编码器,并且在通道内部采用基于列的点跳跃算法,提升了位平面的编码速度.同时,MQ编码器与位平面编码器配合,引入5级动态流水结构,进一步提高编码效率.FPGA验证结果表明,运用该结构的Tier-1编码器,在提高70%编码效率的同时只增加了18.2%的硬件开销,取得了令人满意的结果.     

一种基于MQ编码器的图像联合压缩加密算法

为实现图像的压缩和加密同步,使用MQ编码器对内嵌零树小波压缩算法进行改进,将混合混沌序列作为流密钥对比特平面编码生成的上下文和判决进行修正,并送入MQ编码器进行熵编码。对算法进行仿真,结果表明:与原压缩算法相比,所提出算法的重构图像PSNR值至少提高了1 dB,且抗攻击性好,加解密速度快。算法实现了分辨率选择性加密,并在数据压缩的同时实现了算术加密。     

一种基于流水线的MQ编码器FPGA设计

提出了一种应用于JPEG2000标准的4级流水线MQ编码器设计方案.采用状态超前更新,前导0位超前检测和字节输出缓冲策略,解决了在上下文(CX)状态表更新、归一化及字节输出过程中的反馈和循环等问题,提高了编码效率.同时,对关键路径处算法进行优化,提高了系统工作的时钟频率.该设计使用VHDL语言在RTL级描述,并在FPGA上对其进行了仿真验证.实验表明,在Altera的StratixⅡ EP2S601020C4上,编码器的工作效率可以达到1CxD/cycle,最高工作时钟频率可达99.66 MHz.     

10 Gbps LDPC编码器的FPGA设计

该文针对准循环双对角结构的低密度奇偶校验(LDPC)码,提出了一种基于FPGA的高吞吐量编码器实现方法。提出了一种快速流水线双向递归编码算法,能显著提高编码速度;同时设计了一种行间串行列间并行的处理结构计算中间变量,在提高编码并行度的同时可有效减少存储资源的占用量;设计还针对多帧并行编码的情况优化了存储结构,有效复用了数据存储单元和RAM地址发生器,进一步提高FPGA的资源利用率。对一组码长为2304的IEEE 802.16e标准LDPC码,在Xilinx XC4VLX40芯片上,该方法可实现时钟频率200 MHz,信息吞吐量达10 Gbps以上的编码器,且占用不超过15%的芯片逻辑资源和50%左右的RAM存储资源。     

基于FBRM的自适应码率控制算法

针对EBCOT中MQ占用大量编码时间和资源,提出了一种基于码率反馈MQ自适应率控制算法。根据小波子带特性自适应地选择Coding Pass进入MQ算术编码器,先进入码流的Coding Pass反馈控制未进入MQ的Coding Pass,查找截断点,舍弃对最终码流无贡献的Coding Pass的码段。从而提升了整个EBCOT编码效率。算法几乎对整个图像压缩质量无影响,同时还大幅度地提高了整个EBCOT的编码效率。试验结果表明,文中算法有效地减少了EBCOT中MQ的计算量和存储量,易于硬件实现。     

VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000

The embedded block coding with optimized truncation (EBCOT) algorithm is the heart of the JPEG 2000 image compression system. The MQ coder used in this algorithm restricts throughput of the EBCOT because there is very high correlation among all procedures to be performed in it. To overcome this obstacle, a high throughput MQ coder architecture is presented in this paper. To accomplish this, we have studied the number of rotations performed and the rate of byte emission in an image. This study reveals that in an image, on an average 75.03% and 22.72% of time one and two shifts occur, respectively. Similarly, about 5.5% of time two bytes are emitted concurrently. Based on these facts, a new MQ coder architecture is proposed which is capable of consuming one symbol per clock cycle. The throughput of this coder is improved by operating the renormalization and byte out stages concurrently. To reduce the hardware cost, synchronous shifters are used instead of hard shifters. The proposed architecture is implemented on Stratix FPGA and is capable of operating at 145.9 MHz. Memory requirement of the proposed architecture is reduced by a minimum of 66% compared to those of the other existing architectures. Relative figure of merit is computed to compare the overall efficiency of all architectures which show that the proposed architecture provides good balance between the throughput and hardware cost.     

面向Internet传输的多描述可分级视频编码

带宽变化和丢包错误是当前Internet视频传输面临的主要问题,解决的有效途径是对信源采用可分级编码和多描述编码。研究表明,这两种编码方法具有互补性,联合起来使用能提供更好的质量自适应视频传输。传统的联合方案是用多描述编码保护可分级编码的基层信息,该文对此进行了拓展,提出了一种改进的多描述可分级联合视频编码方案。在该方案中,首先用多描述编码方法处理第一级可分级编码的基层信息,然后对得到的多描述进行第二级可分级编码。与传统方案相比,该方案的优点是可以同时兼顾压缩视频流的效率和鲁棒性。     

Efficient Error Control Decoder Architectures for Noncoherent Random Linear Network Coding

Random linear network coding is an efficient technique for disseminating information in networks, but it is highly susceptible to errors. Kötter-Kschischang (KK) codes and Mahdavifar-Vardy (MV) codes are two important families of subspace codes that provide error control in noncoherent random linear network coding. List decoding has been used to decode MV codes beyond half distance. Existing hardware implementations of the rank metric decoder for KK codes suffer from limited throughput, long latency and high area complexity. The interpolation-based list decoding algorithm for MV codes still has high computational complexity, and its feasibility for hardware implementations has not been investigated. In this paper we propose efficient decoder architectures for both KK and MV codes and present their hardware implementations. Two serial architectures are proposed for KK and MV codes, respectively. An unfolded decoder architecture, which offers high throughput, is also proposed for KK codes. The synthesis results show that the proposed architectures for KK codes are much more efficient than rank metric decoder architectures, and demonstrate that the proposed decoder architecture for MV codes is affordable.     

A Clean Slate Architecture Design for VANETs

In this paper, VANET applications have been classified according to their purpose. Furthermore, a clean-slate architecture specifically designed for VANETs has been introduced. The proposed non-layered context-aware ubiquitous architecture adapts dynamically to changes, is oriented to services (VANET applications) and has a flexible structure. The vehicle and environmental context-aware information as well as the VANET communication characteristics are designed for the proper operation of the applications. In addition, the performance of Automatic Repeat Request and Forward Error Correction (FEC) block codes with respect to the throughput efficiency has also been analyzed for a VANET following the proposed clean-slate architecture. The numerical results show that the proposed clean-slate architecture outperforms the traditional layered architecture with respect to the throughput efficiency for both error control schemes. FEC block codes are able to maintain high throughput efficiency over longer distances because the hop length extension technique is applied.     

Performance evaluation of multicast relay network using LDPC and convolutional channel codes along-with XOR network coding

In this paper,we have compared the performance of joint network channel coding(JNCC) for multicast relay network using low density parity check(LDPC) codes and Convolutional codes as channel codes while exclusive or(XOR) network coding used at the intermediate relay nodes.Multicast relay transmission is a type of transmission scheme in which two fixed relay nodes contribute in the second hop of end-to-end transmission between base transceiver station(BTS) and a pair of mobile stations.We have considered one way and two way multicast scenarios to evaluate the bit error rate(BER) and throughput performance.It has been shown that when using XOR network coding at the intermediate relay nodes,the same transmission becomes possible in less time slots hence throughput performance can be improved.Moreover we have also discussed two possible scenarios in the proposed system model,in which both diversity and multiplexing gain has been considered.It is worth notifying that BER and throughput achieved for LDPC codes is better than Convolutional codes for all the schemes discussed.     

A Constant Bound on Throughput Improvement of Multicast Network Coding in Undirected Networks

Recent research in network coding shows that, joint consideration of both coding and routing strategies may lead to higher information transmission rates than routing only. A fundamental question in the field of network coding is: how large can the throughput improvement due to network coding be? In this paper, we prove that in undirected networks, the ratio of achievable multicast throughput with network coding to that without network coding is bounded by a constant ratio of $2$, i.e., network coding can at most double the throughput. This result holds for any undirected network topology, any link capacity configuration, any multicast group size, and any source information rate. This constant bound $2$ represents the tightest bound that has been proved so far in general undirected settings, and is to be contrasted with the unbounded potential of network coding in improving multicast throughput in directed networks.      

Efficient pipelined flow classification for intelligent data processing in IoT

The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things (IoT). In recent years, researchers have tried to develop hardware-based solutions for the classification of Internet packets. Due to higher throughput and shorter delays, these solutions are considered as a major key to improving the quality of services. Most of these efforts have attempted to implement a software algorithm on the FPGA to reduce the processing time and enhance the throughput. The proposed architectures, however, cannot reach a compromise among power consumption, memory usage, and throughput rate. In view of this, the architecture proposed in this paper contains a pipeline-based micro-core that is used in network processors to classify packets. To this end, three architectures have been implemented using the proposed micro-core. The first architecture performs parallel classification based on header fields. The second one classifies packets in a serial manner. The last architecture is the pipeline-based classifier, which can increase performance by nine times. The proposed architectures have been implemented on an FPGA chip. The results are indicative of a reduction in memory usage as well as an increase in speedup and throughput. The architecture has a power consumption of is 1.294w, and its throughput with a frequency of 233 ?MHz exceeds 147 Gbps.     

AVS2视频编码标准中熵编码模块的优化设计

在对高清和超高清视频进行压缩时,编码效率不再是衡量视频压缩技术的唯一指标,为了提高视频编码器的处理速度和降低其功耗,数据吞吐率已经成为衡量视频压缩技术优劣的重要指标.作为AVS2的核心模块之一,熵编码模块在去除信源符号的统计冗余方面有着不可替代的作用.然而,在AVS2熵编码模块的设计过程中,由于没有充分考虑到数据吞吐率这一性能指标,使得其熵编码模块包含非常紧密的编码依赖关系,严重地限制着其数据吞吐率.为了解决这个问题,本文从3个方面对AVS2的熵编码模块进行了优化设计.首先,本文提出了一种快速的,与标准兼容的算术编码引擎归一化方法.该方法仅仅需要一次查表操作即可完成归一化过程.其次,本文提出了一个快速的bypass bin(概率等于0.5的二进制符号)的编解码过程,使得编解码bypass bin仅仅需要移位和加法操作即可完成.最后,本文改进了AVS2中变换系数的编码过程,来最大限度地降低变换系数之间的编码依赖关系.实验结果表明,上述3个技术可以极大地提高AVS2中的熵编码模块的数据吞吐率,同时性能损失也比较小.     

Design and Analysis of High-Throughput Lossless Image Compression Engine Using VLSI-Oriented FELICS Algorithm

In this paper, the VLSI-oriented fast, efficient, lossless image compression system (FELICS) algorithm, which consists of simplified adjusted binary code and Golomb–Rice code with storage-less $k$ parameter selection, is proposed to provide the lossless compression method for high-throughput applications. The simplified adjusted binary code reduces the number of arithmetic operation and improves processing speed. According to theoretical analysis, the storage-less $ k$ parameter selection applies a fixed $ k$ value in Golomb–Rice code to remove data dependency and extra storage for cumulation table. Besides, the color difference preprocessing is also proposed to improve coding efficiency with simple arithmetic operation. Based on VLSI-oriented FELICS algorithm, the proposed hardware architecture features compactly regular data flow, and two-level parallelism with four-stage pipelining is adopted as the framework of the proposed architecture. The chip is fabricated in TSMC 0.13-$ mu$m 1P8M CMOS technology with Artisan cell library. Experiment results reveal that the proposed architecture presents superior performance in parallelism-efficiency and power-efficiency compared with other existing works, which characterize high-speed lossless compression. The maximum throughput can achieve 4.36 Gb/s. Regarding high definition (HD) display applications, our encoding capability can achieve a high-quality specification of full-HD 1080p at 60 Hz with complete red, green, blue color components. Furthermore, with the configuration as the multilevel parallelism, the proposed architecture can be applied to the advanced HD display specifications, which demand huge requirement of throughput.