The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

Parasitic capacitance of submicrometer MOSFET's

We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer devices. Furthermore, we proposed a simple model that ensures the same accuracy as that of the Kamchouchi model     

The effect of high fields on MOS device and circuit performance

A simple analytical model for the MOS device characteristics including the effect of high vertical and horizontal fields on channel carrier velocity is presented. Analytical expressions for the drain current, saturation drain voltage, and transconductance are developed. These expressions are used to examine the effect of scaling the channel length, the gate dielectric thickness, and the bias voltage on device characteristics. Experimental results from various geometry MOS devices are used to verify the trends predicted by the model. Using the physical understanding provided by the model, we examine the effect of device geometry scaling on circuit performance. We suggest that for gate capacitance-limited circuits one should reduce the channel length, and for parasitic capacitance-limited circuits one should reduce the gate dielectric thickness to improve circuit performance.     

A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs

A new 3-D gate capacitor model is developed to accurately calculate the parasitic capacitances of nanoscale CMOS devices. The dependences on gate length and width, gate electrode and dielectric thicknesses, gate-to-contact spacing, and contact dimension and geometry are fully incorporated in this model. The accuracy is certified by an excellent match with the 3-D interconnection simulation results for three structures with strip, square, and circular contacts. The features of being free from fitting parameters and proven accuracy over various geometries make this model useful for nanoscale MOSFET parasitic capacitance simulation and analysis. Furthermore, the developed capacitor model in the form of multidimensional integral can easily be deployed in general circuit simulators. This model predicts that the parasitic capacitance $C_{rm of}$ dominates around 25% of the intrinsic gate capacitance $(C_{rm gint})$ in 80-nm MOSFETs and that the near nonscalability with gate length brings the weighting factor $C_{rm of}/C_{rm gint}$ above 30%/40%/60% in 65-/45-/32-nm devices. It actually exceeds the limitation defined by the most updated ITRS and reveals itself as a show-stopper in high-speed and high-frequency circuit design.      

Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs

A compact model for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric silicon-on-insulator MOSFETs is developed. The authors' model includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length, and the width of an MOS structure. A simple expression for the parasitic internal fringe capacitance from the bottom edge of the gate electrode is obtained and the charges induced in the source and drain regions due to this capacitance are considered. The authors demonstrate an increase in the surface potential along the channel due to these charges, resulting in a decrease in the threshold voltage with an increase in the gate-dielectric permittivity. The accuracy of the results obtained using the authors' analytical model is verified using two-dimensional device simulations.     

A floating well method for exact capacitance-voltage measurement of nano technology

Small gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology.     

Fully depleted CMOS/SOI device design guidelines for low-powerapplications

We report the fully depleted (FD) CMOS/SOI device design guidelines for low-power applications. Optimal technology, device and circuit parameters are derived and compared with bulk CMOS based design. The differences and similarities are summarized. Device design guidelines using devices with L=0.1 μm for FDSOI low-power applications are presented using an empirical drain saturation current model fitted to experimental data. The model is verified in the deep-submicron regime by two-dimensional (2-D) simulation. For L=0.1 μm FDSOI low-power technology, optimum speed and lower-power occurs at V_dd=3V_th and V_dd=1.5 V_th, respectively. Optimum buried oxide thickness is found to be between 300 and 400 nm for low-power applications. Optimum transistor sizing is when the driver device capacitance is 0.3 times the total load capacitance. Similarly optimum gate oxide thickness is when the driver device gate capacitance is 0.2-0.6 times the total load capacitance for performance and 0.1-0.2 for low-power, respectively. Finally optimum stage ratio for driving large loads is around 2-4 for both high-performance and low-power     

Anticipation of nitrided oxides electrical thickness based on XPS measurement

Plasma nitridation of thermally grown oxide films has proven to be an excellent gate dielectric in meeting the electrical requirements of the 65 nm node. As the 65 nm device performance is very sensitive to both physical thickness and nitrogen dose of these dielectric films, it is highly desirable to predict the electrical properties of such films. We present a simple physical model to forecast the capacitance-equivalent thickness (CET) of nMOS devices for 65 nm technology. The model is based on the total nitrogen dose and the dielectric physical thickness, both given by in-line X-ray photoelectron spectroscopy (XPS) measurement of the plasma nitrided gate dielectric. This model uses an estimated gate oxide dielectric constant, the gate depletion capacitance and the inversion layer capacitance. A good correlation is obtained between calculated and measured CET for plasma nitrided oxides from 19 to 30 Å CET and for a large range of incorporated nitrogen doses.     

Capacitive effects in IGBTs limiting their reliability under short circuit

The short-circuit oscillation mechanism in IGBTs is investigated in this paper by the aid of semiconductor device simulation tools. A 3.3-kV IGBT cell has been used for the simulations demonstrating that a single IGBT cell is able to oscillate together with the external circuit parasitic elements. The work presented here through both circuit and device analysis, confirms that the oscillations can be understood with focus on the device capacitive effects coming from the interaction between carrier concentration and the electric field. The paper also shows the 2-D effects during one oscillation cycle, revealing that the gate capacitance changes according with the shape of the electric field due to the charge distribution in the n-base. It has been identified that the time-varying capacitance leads to parametric oscillations together with the stray gate inductance, which limit the reliability of the IGBT.     

Modeling the equivalent oxide thickness of Surrounding Gate SOI devices with high-κ insulators

In this work, the behavior of the gate insulator capacitance of different Surrounding Gate SOI devices with square and circular cross-sections has been studied. It is shown that the equivalent oxide thickness used for planar devices is not valid for devices with bidimensional confinement. For this kind of devices, new expressions for the gate insulator capacitance and equivalent oxide thickness are obtained using an approximate model of metal–insulator–metal capacitors. These expressions depend not only on the dielectric constant but also on the geometry of the device under consideration since for non-planar devices geometry plays an important role in the behavior of the C–V characteristics. The new expressions are validated by numerical simulations of these Multiple-Gate (MuG) devices that take into account quantum effects.     

A new grounded lamination gate (GLG) for diminished fringe-capacitance effects in high-/spl kappa/ gate-dielectric MOSFETs

A grounded lamination gate (GLG) structure for high-/spl kappa/ gate-dielectric MOSFETs is proposed, with grounded metal plates in the spacer oxide region. Two-dimensional device simulations performed on the new structure demonstrate a significant improvement with respect to the threshold voltage roll-off with increasing gate-dielectric constant (due to parasitic internal fringe capacitance), keeping the equivalent oxide thickness same. A simple fabrication procedure for the GLG MOSFET is also presented.     

Alpha-particle-induced collected charge model in SOI-DRAM's

We have developed a model for collected charges induced by an alpha-particle for SOI-DRAMs which assumes that the body capacitance equals the gate capacitance and that holes do not recombine with electrons. The validity of our model was supported by three-dimensional (3-D) device simulations that considered various gate lengths, gate oxide thicknesses, and flat-band voltages. The work function difference between the gate and body materials caused a significant increase in the current gain. The vertical band of the body region should therefore be flat to suppress the collected charge. A thinner gate oxide would also suppress the collected charge during a refresh interval. This finding could not be obtained from the conventional equation     

功率VDMOS器件的ESD瞬态模型

基于对功率VDMOS器件ESD保护及初始条件的分析,建立了VDMOS器件的ESD保护等效电路,分析了ESD响应过程,得到功率VDMOS器件的ESD瞬态模型. 分析结果表明,该模型准确地描述了功率VDMOS器件的ESD瞬态放电过程,解决了以往模型中初始条件分析不足等问题. 借助该模型,获得ESD器件的等效电阻和击穿电压、VDMOS的栅极输入电阻、栅源电容、栅氧厚度等与功率VDMOS器件抗ESD能力的关系,为功率VDMOS器件的抗ESD保护设计提供重要指导.     

Analytical modelling of threshold voltage for underlap Fully Depleted Silicon-On-Insulator MOSFET

In this article, surface-potential-based analytical threshold voltage model for underlap Fully Depleted Silicon-On-Insulator MOSFET (underlap-SOI) is developed by solving two-dimensional Poisson equation. The gate underlap at source/drain (S/D) has different boundary conditions as compared to channel region under the gate dielectric that divide the whole channel into three regions. It leads us to derive the new surface potential model for three different channel regions, i.e. the region under the gate dielectric and two gate underlap regions at S/D. The effects of underlap length, channel length, body thickness, channel doping concentration, metal gate work function and gate dielectric constant on threshold voltage have been included in our model. The threshold voltage dependence on different device parameters has been studied using analytical model and simulations. The closeness between the simulation results and model results show that the analytical model accurately calculate the threshold voltage values for large range of device parameters.     

A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs

A compact, physical, short-channel threshold voltage model for undoped symmetric double-gate MOSFETs has been derived based on an analytical solution of the two-dimensional (2-D) Poisson equation with the mobile charge term included. The new model is verified by published numerical simulations with close agreement. Applying the newly developed model, threshold voltage sensitivities to channel length, channel thickness, and gate oxide thickness have been comprehensively investigated. For practical device designs the channel length causes 30-50% more threshold voltage variation than does the channel thickness for the same process tolerance, while the gate oxide thickness causes the least, relatively insignificant threshold voltage variation. Model predictions indicate that individual DG MOSFETs with good turn-off behavior are feasible at 10 nm scale; however, practical exploitation of these devices toward gigascale integrated systems requires development of novel technologies for significant improvement in process control.     

Analysis of the Effects of Fringing Electric Field on FinFET Device Performance and Structural Optimization Using 3-D Simulation

In this paper, the potential impact of parasitic capacitance resulting from fringing field on FinFET device performance is studied in detail using a 3-D simulator implemented with quantum-mechanical models. It was found that fringing field from gate to source contributes significantly to FinFET performance and speed. The strength of fringing field is closely related to device features such as gate-dielectric thickness, the spacer width, fin width and pitch, as well as the gate height. For undoped fin with underlapping (nonoverlapping source/drain) gate, a thinner spacer with higher kappa value enhances the gate control of short-channel effects (SCEs) and reduces the source-to-drain leakage current. Our results also suggest that reducing the high- gate-dielectric thickness is no longer an effective approach to improve performance in small FinFET devices due to the strong fringing effect. However, the introduction of thin metal gate in a multifin device was found beneficial to device speed without compromising on current drive and SCE.     

Current drive enhancement by using high-permittivity gate insulatorin SOI MOSFET's and its limitation

Speed enhancement effects by using a high-permittivity gate insulator in SOI MOSFETs and its limitation were investigated by a two-dimensional device simulator and circuit simulator. The SOI structure is suitable to have excellent current drive by using a high-permittivity gate insulator. Although the gate capacitance increases as a function of its dielectric constant, the current drive does not increase proportionally due to the inversion capacitance. According to the simulation results of the delay time, when the pulse waveforms driven by a CMOS inverter are propagated through 1 mm-long interconnects, the delay time significantly reduces at a dielectric constant value of around 25 (Ta₂O₅). Thus, it is worthwhile using Ta₂O₅ for gate insulator to achieve high-speed operation. Furthermore, the reduction of source parasitic series resistance is a key issue to realize the highest current drive by using a high-permittivity gate insulator in SOI MOSFET     

绝缘体上硅FinFET亚阈值摆幅研究

在新型多栅器件栅电容模型的研究中,量子电容随着沟道长度及栅氧化层厚度的不断减小而变得越发不可忽略。推导了基于绝缘体上硅(SOI)工艺技术的鳍式场效应晶体管(FinFET)的量子电容,并通过构建囊括量子电容的内部电容网络模型推导了亚阈值摆幅。采用Matlab软件,仿真验证了量子电容对亚阈值摆幅的影响。提出了亚阈值摆幅的优化方法,为如何选取合适的器件尺寸来优化某个特定设计目标的性能提供了指导。     

Unified MOSFET Short Channel Factor Using Variational Method

A new natural gate length scale for MOSFET's is presented using Variational Method. Comparison of the short channel effects is conducted for the uniform channel doping bulk MOSFET, intrinsic channel doping bulk MOSFET, SOI MOSFET and double gated MOSFET. And the results are verified by the 2D numerical simulation. Taken all the 2-D effects on front gate dielectric, back gate dielectric and silicon film into account, the data validity of electrical equivalent oxide thickness is investigated by this model, as shows that it is valid only when the gate dielectric constant is relatively small.