Study of Scaling Trends in Energy Recovery Logic: An Analytical Approach

This paper presents an analytical model to study the scaling trends in energy recovery logic. The energy performance of conventional CMOS and energy recovery logic are compared with scaling the design and technology parameters such as supply voltage, device threshold voltage and gate oxide thickness. The proposed analytical model is validated with simulation results at 90 nm and 65 nm CMOS technology nodes and predicts the scaling behavior accurately that help us to design an energy-efficient CMOS digital circuit design at the nanoscale. This research work shows the adiabatic switching as an ultra-low-power circuit technique for sub-100 nm digital CMOS circuit applications.     

The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application

The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented. Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed. Then two new circuits, i.e., CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced. In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun. The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration. Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed. Both the forward scaling of the active devices and the inverse scaling of interconnection layer, i.e., more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices. Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples.     

CMOS射频集成电路的现状与进展

随着低功耗、可移动个人无线通信的发展和CMOS工艺性能的提高,用CMOS工艺实现无线通信系统的射频前端不仅必要而且可能.本文讨论了用CMOS工艺实现射频集成电路的特殊问题.首先介绍各种收发器的体系结构,对它们的优缺点进行比较,指出在设计中要考虑的一些问题.其次讨论CMOS射频前端的重要功能单元,包括低噪声放大器、混频器、频率综合器和功率放大器.对各单元模块在设计中的技术指标,可能采用的电路结构以及应该注意的问题进行了讨论.此外,论文还讨论了射频频段电感、电容等无源器件集成的可能性以及方法.最后对CMOS射频集成电路的发展方向提出了一些看法.     

Transistor-and Circuit-Design Optimization for Low-Power CMOS

CMOS-technology scaling has moved to a power-constrained condition regardless of the application segments. Power management in advanced CMOS technology drives the need to conciliate scaling-driven fundamental material limitations with product and application evolution requirements. Flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize systems on a chip. This paper reviews issues associated with transistor scaling and co-optimization for power-management circuit-design schemes for active-and leakage-power control. This paper also addresses the derived trends and implications on I/O and analog-transistor scaling.     

Process and circuit design interlock for application-dependent scaling tradeoffs and optimization in the SoC era

Several physical phenomena in highly scaled CMOS technology have now become first-order elements affecting the electrical behavior of transistor characteristics. Effects such as STI mechanical stress, direct tunneling in gate dielectrics, gate line-edge roughness, and others can have significant influence on device characteristics. This paper elaborates on these effects to exemplify the need for closer interaction between circuit design and process development teams in order to push out application-dependent scaling limits. The paper also highlights the need for further efforts in the areas of circuit-level device modeling.     

Weighing in on logic scaling trends

In this paper, scaling trends and the associated challenges are discussed from the perspective of the 2001 International Technology Roadmap for Semiconductors (ITRS) for both high-performance and low-power logic technologies. Starting from the overall chip circuit requirements, MOSFET and front-end process integration technology requirements, scaling trends, and challenges are discussed, as well as some of the key potential solutions to the challenges, along with the long-term issues and possible solutions for mobility improvement and optimal scaling for very small transistors. Potential solutions include eventual use of high-k gate dielectrics, metal gate electrodes, and perhaps nonclassical MOSFET devices such as double-gate SOI     

An Efficient 5‐Input Exclusive‐OR Circuit Based on Carbon Nanotube FETs

The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field‐effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET‐based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET‐based 5‐input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32‐nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS‐style design.     

The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks

This paper provides evidence that, as a result of constant-field scaling, the peak$f_T$(approx. 0.3$hbox mA/muhbox m$), peak$f_ MAX$(approx. 0.2$hbox mA/muhbox m$), and optimum noise figure$ NF_ MIN$(approx. 0.15$hbox mA/muhbox m$) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40–80 Gb/s wireline transceivers.     

Crosstalk noise reduction in synthesized digital logic circuits

As CMOS technology scales into the deep submicrometer regime, digital noise is becoming a metric of importance comparable to area, timing, and power, for analysis and design of CMOS VLSI systems. Noise has two detrimental effects in digital circuits: First, it can destroy logical information carried by a circuit net. Second, it causes delay uncertainty: Non critical paths might become critical because of noise. As a result, circuit speed becomes limited by noise, primarily because of capacitive coupling between wires. Most design approaches address the crosstalk noise problem at the layout generation stage, or via postlayout corrections. With continued scaling, too many circuit nets require corrections for noise, causing a design convergence problem. This work suggests to consider noise at the gate-level netlist generation stage. The paper presents a simplified analysis of on-chip crosstalk models, and demonstrates the significance of crosstalk between local wires within synthesized circuit blocks. A design flow is proposed for automatically synthesizing CMOS circuits that have improved robustness to noise effects, using standard tools, by limiting the range of gate strengths available in the cell library. The synthesized circuits incur a penalty in area/power, which can be partially recovered in a single postlayout corrective iteration. Results of design experiments indicate that delay uncertainty is the most important noise-related concern in synthesized static CMOS logic. Using a standard synthesis methodology, critical path delay differences up to 18% of the clock cycle time have been observed in functional blocks of microprocessor circuits. By using the proposed design flow, timing uncertainty was reduced to below 3%, with area and power penalties below 20%.     

Silicon technology tradeoffs for radio-frequency/mixed-signal "systems-on-a-chip"

Silicon technology has progressed over the last several years from a digitally oriented technology to one well suited for microwave and RF applications at a high level of integration. Technology scaling, both at the transistor and back-end metallization level, has driven this progress. CMOS technology is ideally suited for low-noise amplification and receiver applications, but the fundamental breakdown voltage is lower than that of equivalent Si/SiGe HBTs. High-quality passive devices are equally important, and improvements in metallization technology are resulting in higher quality inductors. This paper summarizes the silicon technology issues associated with RF "system-on-a-chip" applications.     

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMICfront-end with a low insertion loss switch

This paper describes the design and experimental results of a 1.8-V single-chip CMOS MMIC front-end for 2.4-GHz band short-range wireless communications, such as Bluetooth and wireless LANs. The IC consists of fundamental RF building circuits-a power amplifier (PA), a low-noise amplifier (LNA), and a transmit/receive-antenna switch (SW), including almost all on-chip matching elements. The IC was fabricated using a 0.18-μm standard bulk CMOS technology which has no extra processing steps to enhance the RF performances. Two new circuit-design techniques are introduced in the IC in order to minimize the insertion loss of the SW and realize a higher gain for the PA and LNA despite the utilization of the standard bulk CMOS technology. The first is the derivation of an optimum gate width of the SW to minimize the insertion loss based on small-signal equivalent circuit analysis. The other is the revelation of the advantages of interdigitated capacitors (IDCs) over conventional polysilicon to polysilicon capacitors and the successful use of the IDCs in the LNA and PA. The IC achieves the following sufficient characteristics for practical wireless terminals at 2.1 GHz and 1.8 V: a 5-dBm transmit power at a -1-dB gain compression, a 19-dB gain, an 18-mA current for the PA, a 1.5-dB insertion loss, more than 24-dB isolation, an 11-dBm power handling capability for the SW, a 7.5-dB gain, a 4.5-dB noise figure, and an 8-mA current for the LNA     

先进的Hf基高k栅介质研究进展

随着CMOS器件特征尺寸的不断缩小,SiO2作为栅介质材料已不能满足集成电路技术高速发展的需求,利用高k栅介质取代SiO2栅介质成为微电子技术发展的必然.但是,被认为最有希望替代SiO2的HfO2由于结晶温度低等缺点,很难集成于现有的CMOS工艺中,新型Hf基高k栅介质的研究成为当务之急.据报道,在HfO2中引入N、Si、Al和Ta可大大改善其热力学稳定性,由此形成的高k栅介质具有优良的电学特性,基本上满足器件的要求.本文综述了这类先进的Hf基高k栅介质材料的最新研究进展.     

VLSI scaling methods and low power CMOS buffer circuit

Device scaling is an important part of the very large scale integration(VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit’s performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate(LPTG) approach and tested it on complementary metal oxide semiconductor(CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model(BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability.     

The incredible shrinking transistor

The steady down-scaling of CMOS device dimensions has been the main stimulus to the growth of microelectronics and the computer industry over the past two decades. The more an IC is scaled, the higher becomes its packing density, the higher its circuit speed, and the lower its power dissipation. Today, after many generations of scaling, the smallest feature in a CMOS transistor is approaching atomic dimensions and off-state leakage current per transistor has been rising because thermal energy does not scale. So how much longer can CMOS scaling continue? As the integration level of ICs moves toward 100 million transistors in the next few years, key issues of transistor design must be reexamined for 0.10-0.13-μm generation technology. In previous CMOS generations, it was possible to disregard many parasitic components like off-state leakage and gate current. But in the not-so-distant future, these undesirables will grow rapidly as the fundamental limits imposed by thermodynamics and quantum mechanics close in on the technology. Fortunately the margins in today's devices will be enough to blunt the impact of such effects for perhaps a few generations. All the same, extracting the most performance while extending the limit of CMOS will require several elaborate schemes, including multiple threshold voltages, optimum two-dimensional nonuniform doping, and near atomic level control of gate oxide thickness and source-drain profile     

The twin-transistor noise-tolerant dynamic circuit technique

This paper describes a new circuit technique for designing noise-tolerant dynamic logic. It is shown that voltage scaling aggravates the crosstalk noise problem and reduces circuit noise immunity, motivating the need for noise-tolerant circuit design. In a 0.35-μm CMOS technology and at a given supply voltage, the proposed technique provides an improvement in noise immunity of 1.8×(for an AND gate) and 2.5×(for an adder carry chain) over domino at the same speed. A multiply-accumulate circuit has been designed and fabricated using a 0.35-μm process to verify this technique. Experimental results indicate that the proposed technique provides a significant improvement in the noise immunity of dynamic circuits (>2.4x) with only a modest increase in power dissipation (15%) and no loss in throughput     

Impact of technology scaling on the tuning range and phase noise of mm-wave CMOS LC-VCOs

The impact of CMOS technology scaling, on the tuning range and phase noise performance of mm-wave LC voltage controlled oscillators (LC-VCOs) is presented. As a preliminary step, the fundamental LC-VCO elements (i) tank inductor, (ii) fixed and variable capacitor elements, and (iii) cross-coupled transistor pair are analytically modeled across the frequency range 10–50 GHz. These models are then exploited to analyze the tuning range and phase noise revealing the ultimate performance bounds for simultaneously achieving low phase noise and wide tuning range in mm-wave CMOS LC-VCOs across the CMOS technology scaling (from 130 nm down to 45 nm) are explored. The analysis demonstrates the improvement of the maximum achievable tuning range, phase noise, and figures-of-merit (FoM and FoM_T) with the technology down scaling. Finally, the performance trend of the mm-wave CMOS LC-VCOs implemented using both thin and thick gate cross-coupled pair is compared. The analysis indicates that thick gate cross-coupled pair VCOs achieve better phase noise at the expense of power consumption and maximum tuning range.     

High-frequency small signal AC and noise modeling of MOSFETs for RFIC design

High-frequency (HF) AC and noise modeling of MOSFETs for radio frequency (RF) integrated circuit (IC) design is discussed. A subcircuit RF model incorporating the HF effects of parasitics is presented. This model is compared with the measured data for both y parameter and f_T characteristics. Good model accuracy is achieved against measurements for a 0.25 μm RF CMOS technology. The HF noise predictivity of the model is also examined with measured data. Furthermore, a methodology to extract the channel thermal noise of MOSFETs from HF noise measurements is presented. By using the extracted channel thermal noise, any thermal noise models can be verified directly. Several noise models including the RF model discussed in this paper have been examined, and the results show that the RF model can predict the channel thermal noise better than the other models     

Comprehensive study on low-frequency noise characteristics insurface channel SOI CMOSFETs and device design optimization for RF ICs

Low-frequency (LF) noise, a key figure-of-merit to evaluate device technology for RF systems on a chip, is a significant obstacle for CMOS technology, especially for partially depleted (PD) silicon-on-insulator (SOI) CMOS due to the well-known kink-induced noise overshoot. While the dc kink effect can be suppressed by either using body contact technologies or shifting toward fully depleted (FD) operation, the noise overshoot phenomena still resides at high frequency for either FD SOI or poor body-tied (BT) SOI CMOSFETs. In this paper, floating body-induced excess noise in SOI CMOS technology is addressed, including the impact from floating body effect, pre-dc kink operation, and gate overdrive, followed by the proposal of a universal LF excess noise model. As the physical mechanism behind excess noise is identified, this paper concludes with the suggestion of a device design methodology to optimize LF noise in SOI CMOSFET technology     

Noise in SiGe HBT RF Technology: Physics, Modeling, and Circuit Implications

This paper presents an overview of the physics, modeling, and circuit implications of RF broad-band noise, low-frequency noise, and oscillator phase noise in SiGe heterojunction bipolar transistor (HBT) RF technology. The ability to simultaneously achieve high cutoff frequency (f/sub T/), low base resistance (r/sub b/), and high current gain (/spl beta/) using Si processing underlies the low levels of low-frequency 1/f noise, RF noise, and phase noise of SiGe HBTs. We first examine the RF noise sources in SiGe HBTs and the RF noise parameters as a function of SiGe profile design, transistor biasing, sizing, and operating frequency, and then show a low-noise amplifier design example to bridge the gap between device and circuit level understandings. We then examine the low-frequency noise in SiGe HBTs and develop a methodology to determine the highest tolerable low-frequency 1/f noise for a given RF application. The upconversion of 1/f noise, base resistance thermal noise, and shot noises to phase noise is examined using circuit simulations, which show that the phase noise corner frequency in SiGe HBT oscillators is typically much smaller than the 1/f corner frequency measured under dc biasing. The implications of SiGe profile design, transistor sizing, biasing, and technology scaling are examined for all three types of noises.     

RF CMOS transceivers for cellular telephony

This article describes system and circuit issues related to cellular transceivers, presenting design techniques that have provided high performance in CMOS technology. Following an overview of relevant GSM and WCDMA specifications, the article identifies four trends in RF design that have continued to improve the performance. Examples of CMOS transceivers, and circuit and device concepts are then described that meet the stringent requirements of cellular telephony.