Soft digital signal processing

In this paper, we propose a framework for low-energy digital signal processing (DSP), where the supply voltage is scaled beyond the critical voltage imposed by the requirement to match the critical path delay to the throughput. This deliberate introduction of input-dependent errors leads to degradation in the algorithmic performance, which is compensated for via algorithmic noise-tolerance (ANT) schemes. The resulting setup that comprises of the DSP architecture operating at subcritical voltage and the error control scheme is referred to as soft DSP. The effectiveness of the proposed scheme is enhanced when arithmetic units with a higher "delay imbalance" are employed. A prediction-based error-control scheme is proposed to enhance the performance of the filtering algorithm in the presence of errors due to soft computations. For a frequency selective filter, it is shown that the proposed scheme provides 60-81% reduction in energy dissipation for filter bandwidths up to 0.5 π (where 2 π corresponds to the sampling frequency f_s) over that achieved via conventional architecture and voltage scaling, with a maximum of 0.5-dB degradation in the output signal-to-noise ratio (SNR_o). It is also shown that the proposed algorithmic noise-tolerance schemes can also be used to improve the performance of DSP algorithms in presence of bit-error rates of up to 10^-3 due to deep submicron (DSM) noise     

Theoretical issues on LTI systems that preserve signal richness

In this paper, theoretical issues about linear time invariant (LTI) systems that preserve signal richness are explored. This paper considers two particular definitions of signal richness and finds the necessary and sufficient conditions under which an LTI system preserves the richness property. Several examples are presented to clarify the issues involved in the problem. Paraunitary (PU) and unimodular matrices can be shown not to preserve richness unless they are constant matrices (or a delayed version in the PU case). Some richness preserving properties of cascaded systems are also investigated. A structured proof of the necessary and sufficient conditions is presented. The relationship between persistent excitation (PE) and the proposed definitions of richness is also described.     

数字信号处理及DSP芯片的发展前景

简要介绍了DSP的设计流程及其实现方法,着重介绍了DSPs芯片结构特点、运算速度、应用与市场,并展望了DSPs芯片的发展前景。     

Sub-word parallelism in digital signal processing

We deal with parallelism at the data level. We describe an implementation of the architectural technique called sub-word parallelism (SWP), which increases parallelism at the data-element-level by means of partitioning a processor's data path. The specific implementation we focus on is based on the TigerSHARC DSP architecture, developed at Analog Devices, Inc. As a result of SWP, the same data path and computation units perform more than one computation on an N-element composite word. This composite word consists of more than one adjacent sub-words. SWP is quite common and exists in production versions of most major general-purpose microprocessors. We also present an implementation of an FIR filter in the TigerSHARC using data-level SWP as an example     

On-board digital signal processing technologies for present and future SCPC systems

Devices and architectures for on-board SCPC (single channel per carrier) multi-carrier demodulators suitable for use in satellites to be launched between the present and the year 2000 are discussed in the light of trends in the development of device technology towards lower on-board weight and power consumption. It is shown that at the present time (equivalent to about 1990 for on-board use). The choice of demodulation scheme depends on the number of channels available for regeneration on board the satellite. The total weight and power consumption for several suitable on-board multicarrier demodulation schemes are predicted for 1990, 1995 and 2000, as functions of the number of channels to be regenerated.     

Data-driven multicomputers in digital signal processing

New technologies of integration allow the design of powerful systems which may include several thousands of elementary processors. These multiprocessors may be used for a range of applications in signal and data processing. However, assuring the proper interaction of a large number of processors and the ultimate safe execution of the user programs presents a crucial scheduling problem. The scheduling of operations upon the availability of their operands has been termed the data-driven mode of execution and offers an elegant solution to the issue. This approach is described in this paper and several architectures which have been proposed or implemented (systolic arrays, data-flow machines, etc.) are examined in detail. The problems associated with data-driven execution are also studied. A multi-level approach to high-speed digital signal processing is then evaluated.     

Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems

A methodology for the hierarchical partitioning and mapping of digital signal processing (DSP) tasks to heterogeneous local cluster based network of very large scale integration (VLSI) processors is presented. The goal is to achieve rapid prototyping of VLSI DSP systems. The high level partitioning issues of DSP task graphs and the proposed metrics to guide the partitioning process are described in this paper. Partitioning tominimize power inefficiency in the DSP system is one important metric addressed by this work, since low power signal processing is paramount to new portable and high density multi-chip module (MCM) DSP systems. The application of theRatio Cut Partitioning approach to DSP graphs is explained. We illustrate our results with examples and show how the final partitions vary depending upon the target architecture to meet rapid prototyping requirements. We compare our approach with known techniques and show that it works much better for our target applications.     

LSIs for digital signal processing

The authors describe high-performance CMOS LSIs for digital signal-processing (DSP) technology, such as digital filter, fast Fourier transform (FFT), discrete Fourier transform (DFT), and digital phase-locked loop (DPLL), for communication use. Device design for high-speed and low-power CMOS is described and its feasibility is shown as characteristics of propagation delay time and power delay product.     

LSI's for digital signal processing

This paper describes high-performance CMOS LSI's for digital signal-processing (DSP) technology, such as digital filter, fast Fourier transform (FFT), discrete Fourier transform (DFT), and digital phase-locked loop (DPLL). First, DSP functions for communication use, functional blocks to compose DSP functions, and the types of arithmetic for LSI are discussed. It is explained that multiplier (MPL), variable-length shift register (VSR), and linear arithmetic processor (LAP) have been chosen as the most useful DSP LSI's. Device design for high-speed and low-power CMOS is described and its feasibility is shown as characteristics of propagation delay time at 430 ps and power delay product at 0.073 pJ. The 3-µm effective channel-length CMOS technology has been selected for the DSP LSI because of the high speed, 5 ns, in the case of two input NAND gates and high yield technology. The multiplier architecture is pipeline and uses the Two's-complement representative, the variable-length shift register uses the binary-select method, and the linear arithmetic processor uses the method of changing the outside connections for realization of DSP functions. Maximum operating frequency of these LSI's is more than 23 MHz at the 5-V source voltage. Power dissipation of a VSR, which has been lossy, is less than 250 mW in the 8-MHz operation. They have wider application to communication systems. High-speed CMOS technology is applied to the digital system equipment up to the second level of the PCM hierarchy.     

数字信号处理研究

简单介绍了数字信号处理的应用领域,发展历史,并给出了数字信号处理中几种常用的基本运算的过程和算法以及数字滤波器和离散时间系统的相关知识.     

数字滤波器在数字信号处理中的应用设计

在信号处理中,滤波占有十分重要的地位.数字滤波是数字信号处理的基本方法,以FIR滤波器为基础,利用MATLB程序设计语言对低通FIR数字滤波器进行了有效的设计,应用DSP 汇编语言编程实现了该滤波器.     

嵌入式通用数字信号处理模块

介绍了一种基于PCI总线以TMS320C6701 DSP为运算核心的高性能通用信号处理模块的设计和实现。详细介绍了该模块的构成原理、双机仲裁的简便方法、高速印制板布线注意事项等。该模块作为一种通用、高性能、低成本的信号处理硬件模块，可广泛满足雷达、工业、气象、医疗等领域的信号处理系统的需要。     

Blind deconvolution through digital signal processing

This paper addresses the problem of deconvolving two signals when both are unknown. The authors call this problem blind deconvolution. The discussion develops two related solutions which can be applied through digital signal processing in certain practical cases. The case of reverberated and resonated sound forms the center of the development. The specific problem of restoring old acoustic recordings provides an experimental test. The important effects of noise and non-stationary signals lead to the detailed part of the presentation. In addition, the paper presents results for the case of images degraded by some common forms of blur.     

Energy-efficient soft error-tolerant digital signal processing

In this paper, we present energy-efficient soft error-tolerant techniques for digital signal processing (DSP) systems. The proposed technique, referred to as algorithmic soft error-tolerance (ASET), employs low-complexity estimators of a main DSP block to achieve reliable operation in the presence of soft errors. Three distinct ASET techniques - spatial, temporal and spatio-temporal- are presented. For frequency selective finite-impulse response (FIR) filtering, it is shown that the proposed techniques provide robustness in the presence of soft error rates of up to P/sub er/=10/sup -2/ and P/sub er/=10/sup -3/ in a single-event upset scenario. The power dissipation of the proposed techniques ranges from 1.1 X to 1.7 X (spatial ASET) and 1.05 X to 1.17 X (spatio-temporal and temporal ASET) when the desired signal-to-noise ratio SNR/sub des/=25 dB. In comparison, the power dissipation of the commonly employed triple modular redundancy technique is 2.9 X.     

Differential algorithms of digital signal processing

Ageneral approach to constructing differential algorithms of digital signal processing (DSP) which contain the corresponding transformation functions is provided. As an example the discrete Fourier transform algorithms, implemented using this approach, and some derivative algorithms-Hartley transform, short-time Fourier transform and lapped transform, cosine transform, and Mellin, Hilbert and wavelet transforms are presented. The use of these algorithms allows increasing efficiency and processing power of DSP.