MOSFET的谐极驱动

高频开关电源都会有较大的驱动损耗,本文提出谐振驱动技术,它可以在冲放电过程中进行有效的能量恢复。在对门极驱动损耗进行简单的介绍以后,本文提出了一个新的电路,该电路有着低驱动损耗、开关速度快、驱动电压箝位和防止误导通等功能,而且它没有占空比限制。     

Subthreshold behavior optimization of nanoscale Graded Channel Gate Stack Double Gate (GCGSDG) MOSFET using?multi-objective genetic algorithms

In this paper, a multi-objective genetic algorithms-based approach is proposed to study and optimize the subthreshold behavior of Graded Channel Gate Stack Double Gate (GCGSDG) MOSFET for nanoscale CMOS digital applications. The subthreshold parameters such as threshold voltage, drain induced barrier lowering (DIBL), subthreshold swing and OFF-current have been ascertained and mathematical models have been proposed. The proposed mathematical models are used to formulate the objectives functions, which are the pre-requisite of genetic algorithm. The overall objective function is formulated by means of weighted sum approach. Thus, the proposed approach is used to search for optimal subthreshold parameters to obtain better electrical performances of the devices for digital application.     

平面栅SiC MOSFET设计研究

碳化硅MOSFETs开关速率快,耐压高,在逆变器应用领域前景广阔。平面栅MOSFETs因其成熟的工艺是最先被商业化的器件。在平面栅MOSFETs的设计中,降低导通电阻和提高芯片的电流密度是重要的开发目标。基于自主研制的1 200 V及1 700 V SiC MOSFETs,研究了载流子扩展层技术、JFET注入技术以及元胞结构对器件电学特性的影响。测试结果表明采用方形元胞设计的SiC MOSFET的电流明显大于采用条形元胞设计的电流,JFET注入对阈值电压的影响比载流子扩展层技术更小。     

一种为碳化硅MOSFET设计的高温驱动电路

由于碳化硅材料具有宽带隙、高临界电场强度、高饱和速度和高导热率的特性,其可达到比硅器件更高的耐压值、更快的开关速度和更高的工作结温,使得碳化硅器件成为理想的新一代电力电子器件。为了满足碳化硅器件在高温情况下应用的需求,驱动电路同样需要具备高温下工作的能力。对现阶段高温驱动电路发展情况进行了总结,提出一种基于变压器隔离与高温硅基分立器件的高温驱动电路,并在OrCAD PSpice环境下对电路进行仿真分析,随后在高温箱中进行实验,对提出的高温驱动电路工作性能进行评估。     

降栅压技术在MOSFET驱动中的应用

为在短路发生时有效保护金属氧化物半导体场效应管(metal oxide semiconductor field effect transistor),在60V/10A固态功率控制器的驱动电路中,设计降栅压短路保护。通过与MOSFET反串的二极管检测短路故障,一旦发生短路,启动短路保护电路,快速降低MOSFET栅源极电压至其开启电压附近,以增大MOSFET漏源极电阻并使其可控,设计电容放电时间,即可按一定速度关断功率管。仿真和实验结果表明,降栅压短路保护技术能在短路发生时迅速关断MOSFET并在关断过程中起到限流、抑制di/dt、增强抗干扰的作用。     

高频谐振逆变器的功率MOS管驱动电路

负载谐振桥式逆变器中功率MOS管工作在软开关状态,开关频率的提高,要求门极驱动电路具有充电电流大、开关速度快、驱动损耗小的特点.文章通过对传统门极驱动电路和现存的谐振驱动电路分析比较后,提出了适合高频谐振逆变器中功率MOS管的谐振电流型驱动电路,并分析了其工作过程.理论分析与实验结果表明:此驱动电路中功率MOS管的充放...     

双扩散型MOSFET栅电阻测试实现与应用

功率MOSFET的开关性能主要取决于栅极和源极间的等效电阻Rg和等效电容Ggs的乘积.讲述了双扩散型MOSFET栅电阻Rg和栅电容Cgs的等效模型和构成,介绍了金属绝缘半导体结构C-V曲线及栅电阻Rg的测试方法和设备.通过选用不同的直流偏置电压、频率、信号幅值等进行测试,确定了比较合适的栅电阻Rg测试方法.栅电阻Rg测试还可以用于生产中的不良分析.     

电力电子功率MOSFET管谐振驱动技术的分析

为了减小体积,加快动态响应速度,减少功率MOSFET管的驱动损耗,提高变换器的效率,对现有谐振驱动电路方案的优缺点进行评估。对传统驱动和谐振驱动技术方案进行比较,分析了连续电感电流、不连续电感电流和具有变压器的三种电路方案。认为驱动电路的发展方向是：既具有连续电感电流方案的简洁易控制,又具有初始化脉冲式电感电流的低导通损耗,同时尽量减少所用的有源器件。     

A 3-D Atomistic Study of Archetypal Double Gate MOSFET Structures

The double gate MOSFET architecture has been proposed as a possible solution to allow the scaling of MOSFETs to the sub-30 nm regime, particularly due to its inherent resistance to short-channel effects. The use of lightly doped, or even undoped, channels means that such devices should be inherently resistant to random dopant induced fluctuations which will be one of the major obstacles to MOSFET scaling towards the end of the Si Roadmap. Random dopants within the channel are not, however, the only source of intrinsic fluctuations within MOSFETs at this scale. In this paper we investigate the impact of discrete dopants in the source and drain, individual charges within the active region and line edge roughness on the intrinsic parameter fluctuations in double gate MOSFETs.     

基于干扰动态响应机理的SiC MOSFET驱动设计

目前碳化硅(SiC)MOSFET大多沿用Si MOSFET和IGBT的驱动设计方法.然而,由于SiC MOSFET相比Si器件具有更高的开关速度,因而栅极内阻、驱动回路电感和功率回路电感导致的栅源电压干扰情况也值得探索.该文分析栅源电压干扰产生的过程,进而归纳提炼出一种基于干扰动态响应机理的SiC MOSFET驱动参数标幺化设计方法.从开关结电容的等效电路出发,推导出功率回路和驱动回路的传递函数,基于驱动和功率双回路传递函数,研究揭示栅源电压的干扰动态响应机理.进而,引入标幺化的参数表达形式,以标准量化驱动参数对于栅源电压干扰传导路径的影响,提出基于干扰动态响应机理的SiC MOSFET驱动设计原则.最后,搭建双脉冲实验平台,验证该驱动设计原则的合理性.     

基于开关轨迹优化的SiC MOSFET有源驱动电路研究综述

随着SiC MOSFET的推广,其开关暂态过程中的超调、振荡以及电磁干扰问题越来越受到人们的重视。有源栅极驱动（AGD）电路作为一种新型驱动电路,已被广泛应用于SiC MOSFET开关轨迹的优化控制。首先,该文分析AGD电路的工作原理,给出不同驱动参数对开关特性的影响;其次,着重探讨阈值触发型AGD电路的工作模式,分别从暂态定位技术、逻辑处理架构和功率放大拓扑三方面对AGD电路进行归纳总结,并评价不同技术的优缺点,给出AGD电路设计的建议流程;最后,展望基于SiC MOSFET开关轨迹优化的AGD电路的发展趋势。     

一种改进型抑制SiC MOSFET桥臂串扰的门极驱动设计

由于传统驱动中SiC MOSFET在高开关频率的情况下其寄生参数造成的桥臂串扰更加严重,而现有的抑制串扰驱动电路大多是以增加开关损耗,增长开关延时和增加控制复杂度为代价抑制串扰。因此,根据降低串扰产生过程中驱动回路阻抗的思想,提出一种在栅源极间增加PNP三极管串联二极管和电容的新型有源密勒钳位门极驱动设计,并分析其工作原理,对改进驱动电路并联电容参数进行计算设计。最后,搭建了直流母线电压为300V的同步Buck变换器双脉冲测试实验平台,分别与传统串扰抑制电路,典型串扰抑制电路的正负向串扰电压尖峰抑制效果和开通关断速度做对比分析。实验结果表明,提出的串扰抑制驱动电路正负向电压尖峰分别比传统和典型串扰抑制电路降低了80%和40%,同时减少了32%的器件开关延时。     

3 300 V SiC MOSFET栅氧可靠性研究

碳化硅SiC(silicon carbide)功率器件因其卓越的材料性能,表现出巨大的应用前景,其中金属-氧化物-场效应晶体管MOSFET(metal oxide semiconductor field effect transistor)是最重要的器件。3 300 V SiC MOSFET可应用于轨道交通和智能电网等大功率领域,能显著提高效率,降低装置体积。在这些应用领域中,对功率器件的可靠性要求很高,为此,针对自主研制的3 300 V SiC MOSFET开展栅氧可靠性研究。首先,按照常规的评估技术对其进行了高温栅偏HTGB(high temperature gate bias)试验;其次,针对高压SiC MOSFET的特点进行了漏源反偏时栅氧电热应力的研究。试验结果表明,在高压SiC MOSFET中,漏源反偏时栅氧的电热应力较大,在设计及使用时应尤为注意。     

利用附加电感实现高频功率MOSFET谐振栅极驱动

通过在功率MOSFET栅极驱动回路增加附加电感,利用栅极电容与附加电感的能量交换实现谐振栅极驱动,从而降低驱动功率损耗.保证该电路可以在高频情况下正常运行.实验验证了该方法的正确性与实用性.     

Accurate prediction of the volume inversion impact on undoped Double Gate MOSFET capacitances

This paper demonstrates the capability of our previously published undoped Double‐Gate (DG) MOSFET explicit and analytical compact model to also forecast the effect of the volume inversion (VI) on the intrinsic capacitances. For that purpose, we present simulation results for these capacitances. We show now that the model presents an accurate dependence on the silicon layer thickness, consistent with two‐dimensional numerical simulations, for both thin and thick silicon films. As opposed to our previous work, here we test the capacitance model for three different film thicknesses and also show that the transition from VI regime to dual gate behaviour is well simulated. We demonstrate in this paper that even if the current drive and transconductance are enhanced in VI regime, our results show that intrinsic capacitances are higher as well, which may limit the high‐speed (delay time) behaviour of DG MOSFETs under VI regime. The good agreement between the numerical simulations and our model shows the high potential of our complete DG MOSFET model. Copyright © 2010 John Wiley & Sons, Ltd.     

Thermal model of MOSFET with SELBOX structure

In this article, we present the thermal characteristics of the MOSFET with SELBOX structure. It is observed that the device shows a reduction in the self-heating effect and exhibits improved static and dynamic thermal behavior. A thermal model is developed to explain the thermal behavior of SELBOX structure. The model was evaluated using simulation implemented by Silvaco TCAD tools. Results show the effectiveness of the structure for the minimization of the self-heating effect (SHE) observed in SOI devices. Further, the results obtained from the simulation studies fit into the model showing the validity of the thermal circuit model.     

基于电流源驱动的MOSFET管损耗模型及分析

对于以电压源方式驱动功率MOSFET管,随着开关频率的提高,其开关损耗将显著增加。以此为切入点对电流源驱动功率MOSFET管进行了研究。在对电流源驱动MOSFET管原理性分析的基础上,通过详细地分析功率MOSFET管的开关过程,建立MOSFET管开关损耗模型,求解得到漏极电流、漏源电压与栅源电压之间关系,证明了电流源驱动在减少开关时间和开关损耗上的优越性。在开关频率为1 MHz、输入电压为12 V、输出电压和电流分别为1.3 V和25 A的低压大电流实验平台上进行了验证,实验结果证明了所提出的MOSFET管损耗模型的正确性。     

选择区域外延槽栅结构GaN常关型MOSFET的研究

高性能GaN常关型功率开关器件的实现是目前研究的热点。槽栅结构GaN常关型MOSFET以其栅压摆幅冗余度大、栅极漏电流小等优势受到广泛关注。制备槽栅结构GaN常关型MOSFET需要的刻蚀方法会在栅极沟道引入缺陷,影响器件的稳定性。首先,提出选择区域外延方法制备槽栅结构GaN常关型MOSFET,期望避免刻蚀对栅极沟道的损伤;再通过改进选择区域外延工艺(包括二次生长界面和异质结构界面的分离及抑制背景施主杂质),使得二次生长的异质结构质量达到标准异质结构水平。研究结果表明,选择区域外延方法能够有效保护栅极导通界面,使器件具备优越的阈值电压稳定性;同时也证明了选择区域外延方法制备槽栅结构GaN常关型MOSFET的可行性与优越性。     

Gate replacement with PMOS stacking for leakage reduction in VLSI circuits

Scaling down the circuits of complementary metal oxide semiconductor increases the leakage current. Input vector control is an extremely popular method for controlling leakage without using any technological modification. However, it is less effective for larger logic depth circuits. Our study proposes a Worst Leakage State (WLS) free‐node algorithm based on gate replacement technique, in which, when the logic gate of a given circuit goes into WLS, it is replaced by a suitable variant of the gate which in turn reduces the leakage current in an idle mode of the circuit at the same input vector. These variants minimize leakage under WLS conditions. For replacement purpose, four variants (V1–V4) of a two‐input NAND gate are proposed. This technique is applied on different circuits and some benchmark circuits such as ISCAS'85 (C17) and ITC'99 (B01, B02 and B06) (total of 10 circuits), according to the proposed algorithm with variants V1–V4. The average total power is reduced to 15.04%, 15.04%, 35.7% and 31.5%, and the leakage current is reduced to 42.96%, 42.96%, 84.25% and 84.52%, respectively, for variants V1–V4. The average delay is decreased by 16.03% in V1 and V2 variants and increased by 7.74% and 13.16% for variants V3 and V4, respectively, as compared with the results of conventional circuits at 45‐nm Berkeley Predictive Technology Model technology. Copyright © 2015 John Wiley & Sons, Ltd.     

一种提高SiC MOSFET在高开关速率下栅极电压稳定性的驱动电路

高开关速率且栅极电压稳定的驱动是SiC MOSFET高频工作、进而实现功率变换系统小型化和轻量化的关键技术之一.针对如何在高开关速率下稳定驱动SiC MOSFET,并实现可靠的短路保护,根据栅源电压干扰的传导特点,基于辅助器件的跨导增益构建负反馈控制回路,提出一种SiC MOSFET栅极驱动,进而研究揭示该驱动的短路保...